SREE NARAYANA GURUKULAM COLLEGE OF ENGINEERING

DEPART MENT OF ELECTRONICS AND COMMUNICAION

LAB-MANUAL

(L-408) ELECTRONICS CIRCUITS LAB-2

LIST OF EXPERIMENTS CYCLE-1 1. EMITTER FOLLOWER 2. BI-STABLE MULIVIBARATOR 3. RC PHASE SHIFT OSCILLATOR 4. SCHMITRIGER 5. BOOST STRAP SWEEP CIRCUIT 6. DALIGTON PAIR AMPLIFIER 7. MONOSTABLE MULIVIBARATOR CYCLE-2 1. TWO STAGE R-C COUPLED AMPLIFIER 2. TUNED AMPLIFIER 3. HEARTY OSCILLATOR 4. COLPITTS OSCILLATOR 5. VOLTAGE SHOUNT FEED BACK AMPLIFIER 6. REGULATED POWER SUPPLY 7. SCR CHARACTERISTICS

EXPERIMENT NO-1 EMITTER FOLLOWER

Aim To design and setup an emitter follower and measure its input impedance, output impedance and plot its frequency response. Equipments and components required Transistors, diode, resistors, capacitors, signal generator, bread board and dc supplies. Theory Emitter follower is a common name for a common collector amplifier. It is used as a current amplifier. Its voltage gain is unity, current and power gain is much greater than unity. By virtue of high input impedance and low output impedance of this configuration, it is useful for impedance matching applications. The name of the emitter follower comes from the fact that the amplitude and phase of the signal at the emitter follows the amplitude and phase of the signal at the base.

Procedure: 1. Set up the circuit. Apply a 100 mV sine wave at the input, vary the frequency, measure the amplitude and enter it in the tabular column. 2. Plot the gain versus frequency graph. From the plot, find the bandwidth of the emitter follower. 3. To measure the Zi connect a 10K resistor in series with the function generator. Zi is equal to the ratio of the current to the voltage across the resistor. 4. To measure the output impedance, connect a pot at the output of the circuit. Adjust the pot till the voltage across it is 50% of the output voltage. Remove the pot from the circuit and measure its resistance using a multimeter.

Design Select transistor BC107. DC bias condition: Let Vcc be 12 V. Vre=50 % Vcc=6V. Assume Ic=2 mA. Vre=IR=^V.Hence R=3V. Select 3.3 std

Selection of R1 and R2 Assume current through R1=10I and R2=9I. I=2mA/100=20 micro A. Voltage drop across R2 is=6V+.6V=6.6V. 9IR2=6.6V Hence R2=37K.Select 33 K std. Voltage drop across R1=12v-6.6v=5.4V. Voltage drop across R1=10IR1=5.4 V. From this we get R1=27 K.Use 22K std. Selection of coupling capacitor Rin=R1 || R2 || (1+hfeRe) We get Rin=13K.Then Xc<=1.3K.So Cc>=1/2pifL*1.3K Assuming fL=100 Hz we get Cc=1.2 micro f.Use 1 micro f.

Result Bandwidth=. Input impedance=.. Output impedance=.

EXPERIMENT NO-2 BISTABLE MULTIVIBRATOR Aim To setup bitable multivariator using transistor and study its performance. Equipments and components required Transistors, diode, resistors, capacitors, signal generator, bread board and dc supplies. Theory Bistable multi vibrator circuits has two stable states. An external trigger switches this circuit from one stable state to another another trigger is need to switch this circuit back to the old stable state. Bistable multi vibrator is also called a fip flop or binary circuite. It is nothing but two inverters are connected back to back. Figure shows a bistable multivibrator using single biase suplay. As soon as the circuit is powered, on transistor goes to off state and other is on state both of the transistors cannot remain the same state at a time since the transistor inverters are cross coupled. 3the collector voltage of the transistor at law state and its base voltage vill be in logic high state. Reverse will be the case of the other transistor. Suppose the transistor Q1 is turned on and the transistor Q2 is turned off as soon as the Vcc supply is switched on. When a negative going trigger is applied at the collector of the transistorQ2 it goes to on state. Due to the negative action , transistor Q1 goes to off state bistable multivibrator is continuous to remain this state until the negative going trigger appear across the collector of Q2.

Circuit diagram

Design Design output requirements Amplitude of the output voltage =10V Select transistor BS 107 as T1 and T2. DC biase condition Take VCC =10v . vRE =2V.VCE(sat)=.3V and VBE(Sat)=.7V Design of RC1 and RC2 suppose Q1 of and Q2 is on at one stable state. VRC=VCC-(VRE+VCESAT)=10V-2.3V=7.7V RC=VRC/IC=7.7/2mA=3.85k.use 3.3k std. Design of RE RE = VRE/IE =2V/2Ma=1K. Design of R1 and R2 Since IC1 RC1drop is zero when Q1 is off VC1=VCC IB2 min = IC2/hFE=2mA/100 Consider an over driving factor of 5 to ensure Q2 on IB =0.1mAin order to avoid the lording R1-R2 network by the base current , assume 10Ibis following through R2 and remaining 9Ib is following through R1 Then R2=[VCC-(VBE2SAT+VRE)]/IR2=10V-2.7V=7.3V/1mA.

And R1= (VRE+VBE2 Sat)IR1=(2V+.7V)/.9Ma=3k use 3.3K Std Consider the stable state Q1 is on and Q2 is off. VC1=VCE+VRE=2.3V VB2=VR1=2.3V(R1/R1+R2)=1.1V Then VBE1= VR1-VRE=-0.9V this assure thatQ2 is off. Design of differentiating circuit Let the time period of the input squire wave is 1ms . we have RC<< 0.0016Tfor a differentiator. To avoid the loading the signal generated by the differentiator take R= ten times of the out put of the signal generator , which is usually 600ohms . use 6.8K. Then C= 235PF take 220PF Procedure 1. Verify the components, device and probe. 2. Switch ion the power supply and observe the Vc1 and Vc2. verify whether one is low and other is high. 3. Switch on the trigger signal and observe the collector and base waveforms of the transistor. Wave forms

Result Designed and setup Bistable multivibrator of frequency .., base and collector wave forms are obtained Frequency of square wave obtained=

EXPERIMENT NO-3 RC PHASE SHIFT OSCILLATOR Aim To design and set up an RC phase shift oscillator and to observe the sinusoidal output waveform. Equipments and components required Transistors, diode, resistors, capacitors, bread board and dc supplies. Theory An oscillator is an electronic circuit for generating an ac signal with a dc supply as the only requirement the frequency is determined by the circuit constants. An oscillator requires an amplifier frequency selective network and a positive feed back The circuit is set into oscillations by any noise caused in the base current. This variation in base current is amplified and 180 phase shifted in collector circuit The RC network introduces another 180 thus total phase shift becomes 360and sustained oscillations are produced.

Design of amplifier section SELECT Transistor BC107

Vcc=12v ,Ic=2mA ,Hfe=100,S=5 VRC=40% of VCC=4.8V,VRE=10% VCC=4.8V,VCE=50%VCC=6V RC=VRC/IC=4.8v/2mA=2.2K RE=VRE/IE=1.2v2mA=600,XCE=RE/10,CE=1/(2*100*68)=22 F S=(1+) /(1+Re/RTH+RE) = (1+100)/(1+(100*600/RTH+600) RTH=2525V=R1+R2----------------------------------------------------(1) VB=VE+VBESAT=1.2+0.7=1.9V VB=VCC*R2/R1+R2 R2/R1+R2=1.9v/12v------------------------------------------------------(2) Equating(1)&(2) R1=47K , R2=10K Design of network section f=1KHz R3=R4=R5+hie=R C1=C2=C3=C f=1/(2RC6+4K)----------------------------------------------(3) K=RC/R=0.7,R=RC/K=2.2K/0.7=3.1K Choose R=3.3K Substituting in (3) C=0.016=0.2F R5=R-hie=3.3-2.5=0.8k=1K Procedure 1) Set up the amplifier part of the oscillator and test the dc condition. 2) Ensure that the transistor is operating as an amplifier 3) Connect the feedback Network and observe the sine wave on CRO 4) Measure its amplitude and frequency.

Wave form

Result Designed and set up RC phase shift oscillator of frequency Amplitude of sinusoidal signal obtained=.. Frequency of sinusoidal signal obtained=..

EXPERIMENT NO-4 SCHMITT TRIGGER Aim: To set up a Schmitt Trigger circuit for a UTP of 6 V and an LTP of 4 V.

Equipments and components required Transistors, diode, resistors, capacitors, signal generator, bread board and dc supplies. Theory: The Schmitt Trigger is an emitter coupled bistsble multivibrator in which the cross coupling is removed. It is a comparator that is used to convert a periodical random analog wave into a square wave having the same frequency of the analog wave. Due to this Schmitt trigger is called a squaring circuit. Output of this circuit goes to a high level when the amplitude of the signal goes above a predetermined level called the UTP. Output of this circuit goes to a low level when the amplitude of the signal goes below a predetermined level called the LTP. The Schmitt trigger compares the input analog waveform with respect to the preset values of UTP and LTP. Hence Schmitt trigger is also known as 2-level comparator. Circuit diagram

Procedure: 1. Set up the circuit. 2. Switch on the power supply and observe Vc1 and Vc2.Verify whether 1 is low and 2 is high. 3. Feed 20 Vpp, 1 KHz sine wave at the input and observe the output waveform. 4. To observe hysterisis curve on CRO keep the time/div knob of CRO in x-y mode and feed Vin to the channel and Vo to the y-channel. Design: Output Requirements: Output voltage =8V when input is between 6 V and 4V.Select transistor BC107. Design of Re UTP=Vbe+I1re=6V LTP=Vbe+I2re=4V Assuming I1 and I2is 1 and 1.2 mA respectively we get Re=3.3K. Design of Rb Current limiting resistor Rb=(Vin-Vb)/Ib. We get Rb=40K.Use 47 K std. Design of Rc1 and Rc2 When Q1 is on,Rc1 is 4.4K.Use 4.7 K std. When Q1 is on,Rc1 is = 1.5 K. Assume current through R1=10I and R2=9I. Ib=Ic/hfe=2mA/100=20 micro A. Voltage drop across R2 is= .7V+ 1.2V=1.9V. 9IR2=1.9V. Hence R2= 33 K. Select 33 K std. Voltage drop across R1=12V- 1.9 V=10.1 V. Voltage drop across R1=10IR1=10.1 V. From this we get R1= 12 K. Use 10K std. Design of speed up capacitor C1R1=CpiR1

For BC107 Cpi is 12 pf.Substituting we get C1=5.5 pF.Use 4.7 pF.

Result: The Schmitt Trigger circuit was set up and the waveforms obtained. UTP=V LTP=V

EXPERIMENT NO-5 BOOT STRAP SWEEP CIRCUIT Aim : To setup and study Bootstrap sweep circuit. Equipments and components required Transistors, diode, resistors, capacitors, signal generator, bread board and dc supplies. Theory If the charging and discharging currents of a capacitor is made constant, the voltage across the capacitor will rise or fall linearly. Bootstrap circuit achieves current through the capacitor. When the VCC supply is switched ON, capacitor C1charges from VCC supply through diode D. Once the charging is over, the potential at the left side of the capacitor is positive and hence the diode becomes reverse biased, Transistor Q1 acts as a switch and transistor Q2 functions in emitter follower configuration. When the trigger voltage rises tohigh state, the transistor Q1 will switch to saturation. Now the transistor Q1 is madeOFF by applying a negative going pulse. The capacitor C charges throgh R. Then the potential at the base of Q 2 increases and emitter of Q2 Follows the imput since it is an emitter follower. Capacitor will charge with a constant current established by the constrant potential differnce across the resistor R and hence the charging will be very linear. RC time constant will determine the slope of the sweep. For linear charging of the capacitor to VCC circuit is designed so that T = RC Resistor R must be a high be s . value resistor since the base current of Q1 is dependent on it. To provide sufficient

base current to transistor Q1R2 should be less than hFER The capacitor must be must higher than C to function as a voltage source.

Procedure 1.Verify the condition of all components and set up the circuit.
2. Input trigger must be a square wave or pulse waveform with I ms time period for negative part of the cycle. Amplitude must be sufficiently high. 3. Observe the trigger waveform and output waveform on CRO screen 4. Vary RC product and R and observe the changes in the output wave form. s

Design Output requirements Amplitude and time period of saw tooth waveform = 10V, 1ms. Selection of transistors and diode Select BC 107 as Q1 and Q2. Select 1N4001 as D. DC bias conditions VCC = 10 V, - VEE = -10 V, IC = 2 mA. Design of C2 For the capacito, IT = CV 2 x 10-3 x 1 x 10-3 = C x 10. Then C2 = 0.2F. Use o.22F std. Design of R Since the voltage across the resistor R is always constant (VCC) R = VCC/I = 10/2 x 10-3 = 5 k. Use 5.6 k. std. Design of RB RB provides sufficient base current to the transistor. IB = IC/hFE = 2 mA/100 = 20A Since the transistor functions as a switch, base current should be more than minimum IB. Let tha actual IB be 5 times IB. Then IB = 0.1 mA. RB = = R1 = = 93 k. Select RB = 100 k std.

Design of R1 RE = VEE/IE = 10/2 mA = 5 k. Use 4.7 k std.Selection of coupling caacitor CC Take CC = 10F.

Result :

Trace time = ............... ms Retrace time = ................ ms

EXPERIMENT NO-7 MONOSTABLE MULTIVIBRATOR Aim To setup monostable multi vibrator using transistor Equipments and components required Transistors, diode, resistors, capacitors, signal generator, bread board and dc supplies. Theory This multivariator has only one stable state as its name suggests. it has one quasi state also. And external trigger force this circuit to go to quasi-table from its stable state and remain in that stage for a amound of time determined by discharging time of the capacitor.. R and C are the timing elements and C1 is the speed up capacitor. Figure shows the monostable multivibrator with single bias supply. A soon as the powerfully is switched on transistor Q1 goes to cut of state and Q2 goes to saturation state due to regenerative action. the stable state voltageVC1=VCC,VC2=VCE(SAT),VB1=-Vf The moment when a negative trigger is applied at the collector of the transistor Q1 the transistor Q2 goes to cut of state. hence VC2 jumps to VCC the sudden change in cupped to the base of the transistor Q1 and hence it is gone to on state. the collector voltage of the transistor Q1 is currently drop by an amount of Ic1Rc. When Ic1 is the current through the resistance Rc1.hence Capacitor acts as a short circuit for a sudden change, the base voltage Q2 suddenly drops by an equal amount. Now the polarity of the capacitor Across such a way that the negative is at right side now the capacitor changes from negative potential to +VCC through R and Q1.onece it become zero it further changes towards VCC. But when the positive potential at right side of the capacitor reaches the cut of voltage. Q1 turn on. thus the circuited comes back to the stable state.it will continue to the next trigger comes at a collector of Q1.the time duration of the quasi-stable state is given by the expression T=.69RC

Design Design output requirements Amplitude =12 V pulse width 1ms. Selection of transistor and diode Chose transistor BC107 and diode IN 4001 DC bias Condition VCC=12V,VRE=2V Design of RE We know RE=VRE/IE=1k Since IE=IC

Design of R R must be able to provide enough base current to keep the transistor Q2 is in saturation IB min=IC/hFE=2mA/hFE=20uA Consider the over driving factor 5. So that the transistor indeed in Saturation

Then the actual base current IB= 5IBmin=0.1mA R=(VCC-VRE-VBEsat)/0.1mA.=93K. Use 82k Design of R1 And R2 Consider the quasi Stable state(Q1is off and the Q2 is On) Assume VBE1=-1V to assure the transistor Q1 is in Cut of state. Then VB1= VR1=-1V+2V=1V Since IB1=VC2R1/R1+R2= 2.3V *R1/R1+R2 Because VC=VCE+VRE From thie R2=1.3R1 Consider the stable state (Q1 is on Q2 is Off) VC2=12V Since Q2 is off VB1= VBE (Ssat)+VRE=2.7V Also IR2=IB1+IR1 Ie. 12V-2.7V/R2=IB1+2.7V/R1Substitute the value of R2 we get 9.3R1=1.3*10-4 R12 3.64*R1 Or 1.3*10-4 *R12 -5.56R1=0 Solving the quadratic expression R1= + -5.56 31 2*1.3*10-4*R12 R1 = 42.8k use 47kstd. Then R2=55.64kuse 56k Std. Design of RC1 and RC2 RC=VCC-VC/ICSAT = 4.35k use 4.7k Std. Take RC1=RC2=RC Design of R1and C We have T= 0.69RC substituting the value of R we get c=.01uF. Design of differentiator circuit The condition is Rd Cd<0.0016Tt where Tt = time period of the trigger signal.

To avoid the loading of the signal generated by the differentiator. Take Rd=6.8K Let Tt be 2ms. Then Cd=0.01uF. Procedure 1. Test all components and probes before rigging up circuit 2. Switch ON Vcc supply and Q1 is off state and Q2 is on state VC1 should be high and VC2 low 3. Switch on trigger supply trigger have sufficient amplitude 4. Observe the collector and base wave form of both transistor .Note down all detail of the wave form such as the pulse with amplitude overshoot etc Wave forms

Result Designed and setup Monostable multivibrator of frequency 1kHz , base and collector wave forms are obtained Frequency of square wave obtained=

CYCLE-2

EXPERIMENT NO-1 TWO STAGE RECOUPLED AMPLIFIER

Aim To design, set up and study a two stage RC coupled CE amplifier using BJT. Components and equipments required Transister, dc source, capacitors, resisters, bread board, signal generator and CRO. Theory More stages of RC coupled amplifiers can be used in cascade to increase the voltage gain of an amplifier. A two stage amplifier provides an overall voltage gain of A1, A2 if A1 and A2 are the gains of first and second stages respectively. Since each stage provides a phase inversion, the final output in phase with the input. The input impedance of the second stage is in parallel with RC of the first stage. The voltage gain A1 of the first stage is : A1 = where Zin (second stage) = R1 || R2 || hFErC The voltage gain A2 of the second stage is : A2 = Design : Output requirements : Mid-bandvoltage gain of the amplifier = 100 Selection of transister Select transister BC 107 since its minimum guaranteed hFE equals the required gain (=50) of the amplifier. Assume the gains A1 = 50 and A2 = 2 since A=A1A2 DC baising conditions VCC= 12 V, IC = 2mA, VRC = 40% of VCC = 4.8 V, VRE = 10% of VCC = 1.2 V and VCE = 50% of VCC = 6 V. Design of RC VRC = IC x RC = 4.8 V. From this, we get RC = 2.4 k. Use 2.2 k. std.

Design of RE VRE = IE x RE = IC x RE = 1.2 V. From this, we get RE = 600 . Select 680 std. Design of voltage divider R1 and R2 From the data sheet of BC 107 we get hFE min is 100. IB = IC/hFE = 2 mA/100 = 20 A. Assume the current through R1 = 10 IBand that through R2 = 9 IB to avoid loading the potential divider by the base current. VR2 = Voltage across R2 = VBE + VRE i.e., VR2 = VBE + VRE = 0.7 + 1.2 = 1.9 V. Also, VR2 = 9IBR2 = 1.9 V Then, R2 = = 10.6 k. Select 10 k. std.

VR1 = voltage across R1 = VCC - VR2 = 12 V - 1.9 V = 10.1 V Also, VR1 = 10 IBR1 = 10.1. V Then, R1 = = 50 k. Select 47 k. pot std. Design of RL Gain of the first stage is given by the expression A1 = Here = 25 mV/ where (second stage) = R1 || R2 || hFE re

= 25 mV/2mA = 12.5 = 50 approx. = RC || RL / re

Substituting the values we get

Gain of the second stage is given by the expression

If the required gain = 2, substituting, we get RL = 23 . Use 22 std. Design of the coupling capacitors CC1, CC2 and CC3. XC1 at the lowest frequency (say 100 Hz.), should be equal to one tenth or less of the series impedance being driven by the signal passing through the capacitor. Here the series impedance is Rin. Then XC1 < Rin/10. Here Rin = R1 || R2 || hfere

We get Rin = 1.1 k. Then XC1 < 110 . So, CC1 > 1/2fL x 110 = 14 F. Use 15F std. Similarly XC2 < Rout/10 where Rout = RC. Then XC2 < 240. So, CC2 > 1/2 fL x 240 = 6.6F. se 10F std. Take CC2 = CC3 since the design of CC2 is same as for CC1.

Procedure 1. Test all components using a multimeter. Set up the circuit and verify dc bias conditions. 2. Apply a 100 mV peak to peak sinusoidal signal from the function generator to the circuit input. Observe the input and output waveforms on the CRO screen simultaneously. 3. Keeping the input amplitude constant, vary the frequency of the input signal from 0 Hz. to 1 MHz or more. Measure the output amplitude corresponding to different frequencies and enter it in tabular column.

4. Plot the frequency response characteristics on a graph sheet with gain on y-axis and log f on x-axis. Mark log fL and log fH corresponding to 1/ of the maximum gain. 5.Calculate the bandwidth of the amplifier using the expression

Result Gain of first stage = Gain of second stage= Band width=..

EXPERIMENT NO-2 TUNED AMPLIFIER

Aim To design and set up a turned ratio frequencey amplifier using discrete components. Also to obtain its frequency response and to calculate its Q factor. Components and equipments required Transister, IFT, resistors, capcitors, signal generator, dc sources, bread board and CRO. Theory Tuned voltage amplifier amplifies the signals of desired frequency only. The frequency of amplification is determined by a frequency selective network. These circuits are widely used in the IF and RF stages of television and radio receivers. The circuit shown in figure is a single tuned class - A RF amplifier. An intermediate frequency transformer (IFT) is used as a tank circuit for tuning to the required frequency. IFT is tuned to 455 kHz standard audio IF with a band width of 8 kHz. The selectivity of the circuit Q is given by the expression Q = resonant frequency /bandwidth. When Q increases, bandwidth decreases and selectivity increases.

Circuit diagram

Design Selection of transistor Use a high frequency transistor, BF 195 or its equivalent. For the specifications and electrical characteristics refer to appendix. DC Conditions Design of RE 6.2 k. Design of R1 and R2 Assumethe current through R1 = 10 RB and that through R2 = 9IB to avoid loading of R1 and R2 network by the base current. Base current IB = IC/hFE = 1 mA/60 = 17 Since hFE min of the transister is A. Voltage drop across R2 is VR2 = VBE + VRE = 0.6 + 6 = 6.6 V Also, VR2 = 9IBR2 = 6.6 V. From this we get R1 = 32k. Use 33 k. std. Selection of RL Take RL = 1 k, a nominal value. Design of CC1, CC2 and CE The rule for the design of coupling capacitor XC1 < Rin/10 Here Rin = R1 || R2 || hFEre Assume Vcc = 12 V, VCE = 6, VRE = 6 V and IC = 1 mA. We have RE = VRE/IE. Since IE IC, RE = 6 k. Use

We get Rin = 1.11 k. Then XCE < 0.11 k. at frequency of operation 455 kHz. So, CC1 > 1/2 L x 620 = 1772 pF. Use 2200 pF. f Procedure 1. Set up the circuit on the bread broad. Check the dc biasing conditions using a multimeter. The transister must be in active region. 2. Apply 100m. V sinusoidal signal from the signal generator to the input of the circuit, it provides maximum gain. Bayond and below the resonant frequency, the output amplitude decreases. 3. Find the band width and calculate the quality factor of teh tuned circuit using its expression.

Result Bandwidth of the amplifier = .......... Hz Q factor of the circuit = ........... EXPERIMENT NO-3

HARTY OSCILLATOR Aim To design and setup Hartley oscillator for a given amplitude and frequency . Components and equipments required Transister, , resistors, capcitors, , dc sources, bread board and CRO. Theory LC oscillators are preferred for high frequency generation. Hartley oscillators have LC tank Circuit for frequency selection . the voltage divider bias used for the amplifier in CE configuration. Amplifier section provides 180o phase shift to the signal current. The tank circute provides another 180o phase shift to satisfy the Brakhausen Criterian. High frequency transistors are preferred for a better performance. Re is bypassed by CE to prevent AC signal degradation and thus to improve the gain of the amplifier. Hartley oscillator Frequency of oscillation is determine by the resonant circuit consist capacitor C1 and inductance L1 and L2. It is given by F= 1/2LeqC, where Leq=L1+L2. The output voltage appears across L1 and the output voltage Appears across L2. so the feedback factor of the oscillator is given by =L2/L1. this means that the gain of the amplifier section is A=L1/L2. this means thats the hfe of the transistor should be >=L1/L2 to start the oscillation

Circuit diagram

Design of amplifier section SELECT Transistor BC107 Vcc=12v ,Ic=2mA ,Hfe=100,S=5 VRC=40% of VCC=4.8V,VRE=10% VCC=4.8V,VCE=50%VCC=6V RC=VRC/IC=4.8v/2mA=2.2K RE=VRE/IE=1.2v2mA=600,XCE=RE/10,CE=1/(2*100*68)=22 F S=(1+) /(1+Re/RTH+RE) = (1+100)/(1+(100*600/RTH+600) RTH=2525V=R1+R2----------------------------------------------------(1) VB=VE+VBESAT=1.2+0.7=1.9V VB=VCC*R2/R1+R2 R2/R1+R2=1.9v/12v------------------------------------------------------(2) Equating(1)&(2) R1=47K , R2=10K Design of LC Network

Hartley oscillator Frequency=455kHz F= 1/2LeqC, where Leq=L1+L2. Where C=.1uf then we get L1+L2=12.2uH

L1=L2=6.1uH use 5.6uH Procedure 1. Set up the amplifier part of Hartley and colpitts oscillator on a bread board. check condition of amplifier ensure that the circuit function as an amplifier 2. Complete the circuit connecting the feed back circuit and observe output sinusoidal wave Wave forms

Result Designed and set up Hartley and Colpitts oscillator of frequency 455kHz Amplitude of Hartley oscillator obtained =.. Frequency of Hartley oscillator obtained =.. EXPERIMENT NO-4 COLLPITTS OSCILLATOR Aim To design and setup colpitts oscillator for a given amplitude and frequency .

Components and equipments required Transister, , resistors, capcitors, , dc sources, bread board and CRO. Theory LC oscillators are preferred for high frequency generation. Hartley and colpitts oscillators have LC tank Circuit for frequency selection . the voltage divider bias used for the amplifier in CE configuration. Amplifier section provides 180o phase shift to the signal current. The tank circute provides another 180o phase shift to satisfy the Brakhausen Criterian. High frequency transistors are preferred for a better performance. Re is bypassed by CE to prevent AC signal degradation and thus to improve the gain of the amplifier. Colpitts oscillator The frequency of osilation is given by the expression= 1/2LCeq Where Ceq=C1C2/C1+C2 C1 is series with C2 The output voltage appears across C1 and the the feed back voltage appears across C2.so the feedback factor of the oscillator is given by =C1/C2.this means that the gain of the amplifier section has to be a C2/C1 to Start the oscillation.

Circuit diagram

Design of amplifier section SELECT Transistor BC107 Vcc=12v ,Ic=2mA ,Hfe=100,S=5 VRC=40% of VCC=4.8V,VRE=10% VCC=4.8V,VCE=50%VCC=6V RC=VRC/IC=4.8v/2mA=2.2K RE=VRE/IE=1.2v2mA=600,XCE=RE/10,CE=1/(2*100*68)=22 F S=(1+) /(1+Re/RTH+RE) = (1+100)/(1+(100*600/RTH+600) RTH=2525V=R1+R2----------------------------------------------------(1) VB=VE+VBESAT=1.2+0.7=1.9V VB=VCC*R2/R1+R2 R2/R1+R2=1.9v/12v------------------------------------------------------(2) Equating(1)&(2) R1=47K , R2=10K Design of LC Network Colpitts oscillator Frequency=455kHz 1/2LCeq, where

Where C=.1uf then we get Ceq=C1C2/C1+C2 C1=C2=.1uF Then L=12.2uH use 10uH Procedure 3. Set up the amplifier part of Hartley 4. oscillator on a bread board. check condition of amplifier ensure that the circuit function as an amplifier 5. Complete the circuit connecting the feed back circuit and observe output sinusoidal wave Wave forms

Result Designed and set up Colpitts oscillator of frequency 455kHz Amplitude Colpitts oscillator obtained=.. Frequency of Colpitts oscillator obtained= EXPERIMENT NO-5 VOLTAGE SHUNT FEED BACK AMPLIFIER Aim:

To design ,set up and study voltage shunt feed back amplifier Components and equipments required Transister, resistors, capcitors, signal generator, dc sources, bread board and CRO. Theory The out put of the voltage or current is sampled and feed back to in put of the amplifier in series or shunt to the input source. Here voltage is sampled and feed back to in put current. Circuit digram

Design Select Transistor BC107 Vcc=12v ,Ic=2mA ,Hfe=100,S=5 VRC=40% of VCC=4.8V,VRE=10% VCC=4.8V,VCE=50%VCC=6V RC=VRC/IC=4.8v/2mA=2.2K

RE=VRE/IE=1.2v2mA=600, Design of CE capacitor XCE=RE/10,CE=1/(2*100*68)=22 F S=(1+) /(1+Re/RTH+RE) = (1+100)/(1+(100*600/RTH+600) RTH=2525V=R1+R2----------------------------------------------------(1) VB=VE+VBESAT=1.2+0.7=1.9V VB=VCC*R2/R1+R2 R2/R1+R2=1.9v/12v------------------------------------------------------(2) Equating(1)&(2) R1=47K , R2=10K Design of coupling capacitor CC1 and CC2 XC1at the lowest frequency should be equal to one-tenth of the series impedance that being driven by signal passing through the capacitor. Here Rin is the series impedance Then XC1 RIN/10. Here RIN=R1 II R2 II hfe *re We get RIN =1.1K. Then XC1 110

So CC1 1/2fL*110. Use 15F std Similarly XC2 ROUT/10 where ROUT=RC.then XC2 240 So,CC2 1/2fL*240=6.6F std Rf=1/ , =0.03 then Rf=3.3k Xcf=Rf/10,Cf=1/28 fLXcf =10uf Procedure 1. set up voltage series feed back circuits and verify dc bias conditions. To check dc bias conditions, remove the input signal and capacitors in the circuit 2. Connect the capacitors in the circuit. Apply 100 mV peak to peak sinusoidal signals from the function generator to the circuit input. Observe the input and output wave forms on the CRO screen simultaneously 3. Keeping the input voltage constant at 100 mV, vary the input frequency from 0 to 1 MHZ. Measure the output amplitude corresponding to different frequencies

4. Plot the frequency response characteristics on a graph sheet with gain in dB on the y axis and log f on the X axis. Mark log f L and log f H corresponding to 0.707 of the maximum gain 5. Calculate the band width of the amplifier ie, BW = fH fL

Result : Designed and voltage shunt feed back amplifier and plot the frequency response curve Bandwidth BW= .. Maximum gain=.. EXPERIMENT NO-6 ZENER REGULATOR WITH EMITTER FOLLOWER OUTPUT Aim:

To study the performance of a zener diode regulator with emitter follower output and to plot line regulation and load regulation characteristics for the following specifications. Components and equipments required Transistor, zener , resistor, rheostat, dc source, voltmeter, ammeter and bread board. Theory The limitations of zener diode regulations are 1. The changes in zener current flowing through the zener impedance causes changes in output voltage. 2. The maximum load current that can be supplied is limited. 3. Large amount of power is wasted in zener diode and series resistance. These defects have been overcome in a zener follower. It is a circuit that combines a zener regulator and an emitter follower. The dc output voltage of the emitter follower is V0 = VZ - VBE. When input voltage changes, zener voltage remains the same and so does the output voltage. In an ordinary zener regulator, if the load current required is in the order of amperes, zener should also have tha same rating. But in the zener follower it needs to produce a current IL/. nother advantage of this circuit is its low output impedance. The expression for the output can also be expressed as V0 = VZ - VBE. This means that when the input voltage increases due to some reasons, output will be made constant by the transistor by dropping excess voltage across the transistor.

Procedure 1. Set up the circuit on the bread board after identifying the component leads. Verify the circuit using a multimeter. 2. Keep the load current at 500 mA and note down output voltage for different input voltages from 0 V to 30 V in steps of 1 V. Plot line regulation characteristics with Vin along x-axis and V0 along Y-axis. Calculate % line regulation characteristics with Vin along x-axis and V0 along y-axis. Calculate % line regulation using the expression V0/Vi. 3. Keep the input voltage at 15 V and note down output voltage for different values of load current varying from 0 to 500 mA in equal steps using a rheostat. Plot load regulation characteristics with IL along x-axis and V0 along y-axis. 4. Mark VNL and VFL on the load regulation characteristics and calculate load regulation as per the equation.

Details of 2N 3055 : Type : Si-NPN Application : AF Power Maximum ratings : W Nominal Ratings : = 4 V, = 4 A, = 20-70. = 100 V, = 60 V, = 7 V, max. = 15 A, P = 115

Selection of zener diode We know = = 60 + = 9.1 V, Select = SZ9 Izener

Since the required output = 8.5 V, Selection of Load resister RL = / = 500 mA,

Since the required

= 17

The power rating of the resister = I2RL = (0.5)2 17 = 4.25 W Use a 17, 5 W resistor or 800 , 1 A rheostat Base current of the transistor is IB = Current through the serious resistor / / = 50 mA + = 60 mA since the current through

the zener to keep it in the breakdown region is 10 mA. Selection of resistor RB RB should be selected considering the worst conditions Vi(max) and Vi (min.) = = Because = 182 = 15 = 20 V and
2

= 10 V. RB = 0.36 W)

Select RB = 100 , 0.5 W. (Because

Observation

Result: Design and set up zener regulator with emitter follower out put And plot the line regulation and load regulating graph

SCR CHARACTERISTICS EXPERIMENT NO-7 Aim : To study and plot the V-I characteristics of an SCR Components and equipments required SCR, ammeter , resistor, rheostat, dc source, voltmeter, ammeter and bread board. Theory : Silicon control rectifier is a four layer PNPN device. It has three terminals namely anode(A) cathode(K) and gate (G) diode) plus a third control lead or gate. As the name implies, it is a rectifier one that can be triggered to the ON state by applying a small positive voltage ( VTM ) to the gate lead. Once gated ON, the trigger signal may be removed and the SCR will remain conducting as long as current flows through the device. Volt-ampere characteristics curve of an SCR. The vertical axis + I represents the Device current, and the horizontal axis +V is the voltage applied across the device anode to cathode. The parameter Biasing The application of an external voltage to a semiconductor is referred to as a bias. Forward Bias Operation A forward bias, shown below as +V, will result when a positive potential is applied to the anode and negative to the cathode. Even after the application of a forward bias, the device remains non-conducting until the positive gate trigger Voltage is applied. After the device is triggered ON it reverts to a low impedance state and current flows through the unit. The unit Will remain conducting after the gate voltage has been removed. In the ON state (represented by +I), the current must be limited by the load, or damage to the SCR will result. Reverse Bias Operation The reverse bias condition is represented by -V. A reverse bias exists when the potential applied across the

SCR results in the cathode being more positive than the anode. In this condition the SCR is non-conducting and the application of a trigger voltage will have no effect on the device. In the reverse bias mode, the knee of the curve is known as the Peak Inverse Voltage PIV (or Peak Reverse Voltage - PRV) and this value cannot be exceeded or the device will break-down and be destroyed. A good Rule-of -Thumb is to select a device with a PIV of at least three times the RMS value of the applied voltage.

Procedure Set up the circuit switch on supply keep low voltage Switch on gate dc supply adjusting the potentiometer minimum value of gate voltage Increase the gate current with the help of potentiometer in the gate circuit and watch the triggering of scr observing the dc ammeters connected in series with the load record reading in the meter Repeat the above step with various values of current 2.5mA, 3mA,3.5mA And plot the V-I characteristics of scr current in y- axis and voltage in xaxis

Graph

Result:
Studied the working of SCR and plot its V-I characteristics