Design of Low Power LNA For GPS Application: Varish Diddi, Kumar Vaibhav Srivastava and Animesh Biswas

2011 International Conference on Circuits, System and Simulation IPCSIT vol.
7 (2011) (2011) IACSIT Press, Singapore
Design of Low Power LNA for GPS Application

Varish Diddi 1, Kumar Vaibhav Srivastava 1 and Animesh Biswas 1
1
Department of Electrical Engineering, Indian Institute of Technology Kanpur (IITK)
Abstract. This paper presents design of Low Noise Amplifier (LNA) which operates at 1.6 GHz for Global Positioning System (GPS) application on IHP SiGe BiCMOS 0.25m node. LNA performance is optimized for the power constraint of 2 mW. Simultaneous noise and power match is achieved. The cascode topology with resonating load is used to maximize gain at 1.6 GHz. LNA achieves gain of 14.8 dB and noise figure of 0.96 dB. The LNA exhibits IIP3 of -15.3 dBm for 2-tone test frequencies of 1.6 GHz and 1.62 GHz. The 1 dB compression point of LNA is -20.6 dBm at 1.6 GHz. Cadence tool is used for design and optimization of LNA. Keywords: Low power LNA, SiGe BiCMOS, Heterojunction Bipolar Transistor (HBT), Global Positioning System (GPS)
1. Introduction
Global Positioning System (GPS) receivers are employed in acquisition, tracking and decoding functions. They have become standard feature of cellular and low-cost embedded applications. GPS receiver, like all other wireless receivers, invariably uses low-noise amplifier (LNA) in first few stages depending on receiver architecture. The important goals of low-noise amplifier design are low noise figure, high gain, good inputoutput matching and linearity. The challenge is to achieve all above at low power consumption [1]-[2]. SiGe BiCMOS technology is coming up as strong contender for high frequency applications to traditional GaAs technology. The technology employs SiGe heterojunction bipolar transistor (HBT). HBTs are bandgap engineered by graded doping of germanium in base. The device is found to exhibit excellent current gain, noise performance and linearity at modest power levels [3]. The cutoff frequency (ft) and maximum oscillation frequency (fmax) of the technology used (0.25 m) are 180 GHz and 220 GHz respectively. The fabrication of HBT is compatible with traditional CMOS process and hence lead to higher integration and lower cost. Thus HBTs are excellent choice for radio frequency application. In this paper we present a low-power, high gain low noise cascode amplifier for L-band application. At 1.6 GHz the LNA achieves gain of 14.8 dB with noise figure of 0.96 dB, consuming only 2 mW of dc power. Section II presents the design approach and section III gives the simulation results.
2. Design of Low Noise Amplifier

The cascode topology is chosen to implement LNA. This is a combination of common-emitter (CE) and common-base (CB) configuration [4]. The transistor in CE mode acts as tranconductor while the other in CB mode acts as current buffer. One of the advantages of cascode topology is its high gain. The small signal equivalent of cascade circuit is shown in Fig. 1. Since the current gain is only due to transistor Q1 the effective transconductance (Gm) is given by:
Gm = g m1
(1)
If gm2ro1>>o and o>>1, then the output resistance is given by:

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Ro = o ro 2
(2)
(3)
where o is current gain. The voltage gain is given by:

Av Gm Ro g m1ro 2 o
Fig. 1 Small signal equivalent of cascode
Thus the gain of cadcode is o times greater than that of single transistor CE stage, if we consider ro1 ro2. In this configuration input is at the base of Q1 and output is taken from collector of Q2. The cascode amplifier has higher reverse isolation. Also the miller effect of cascode configuration is very small. This enhances the stability and improves the high frequency operation of amplifier. LNA design starts with biasing of transistors [5]-[6]. There exists a trade-off between gain and noise performance while choosing collector current density (Jc). Then device size is chosen so that simultaneous power and noise matching is accomplished. For this the device is sized such that the real part of optimum impedance (Zopt) becomes equal to source resistance (Rs) i.e. (4) Both the steps above decide the total bias current. But in this case the total power is fixed to be 2 mW and for the given Vcc of 2 V the bias current is already fixed to be around 1 mA. So the current density and device size have to be simultaneously optimized [7]. For a fixed current when device size is increased the ft goes down and so does the gain. Re{Zopt} also decreases with increasing the device size. This variation is shown in Fig. 2.
Re{Zopt} = Rs
Fig. 2 Variation of ft and Re{Zopt} with device size. Device size is normalized with respect to m (8[0.210.84m2])
Sometimes a compromise is made by choosing Re{Zopt} other than Rs to obtain higher gain [7]. But here the device size is chosen such that the optimum source resistance is 50 . The circuit diagram is shown in
40
Fig. 3. The values of components used are given in Table I. The components Le and Lb are used for narrowband input matching [2], [5]. The values are calculated as below.
Le =
Lb =
Rs 2 ft
(5) (6)
1 Le 2C be
But because of parasitic the miller effect the values of Le and Lb are usually higher than calculated [9]. The RL used as load reduces the quality factor of resonating load thus leading to gain spread and is also used as matching element for output matching.
V cc CL RL C out V b2 rfin Cb Lb Q1 Rb Le V b1 Q2 rf out
LL
Fig. 3. LNA circuit employing cascade topology Table 1. List of Values of Components Component Value Cb 3.1 pF Lb 11 nH Le 1.8 nH Rb 20 k LL 3 nH CL 2.3 pF RL 640 Cout 590 fF Q1 120[0.210.84] m2 Q2 120[0.210.84] m2
3. LNA Simulation Results

The LNA designed above was simulated in Cadence tool. Various results were obtained through simulation. Fig. 4 gives the gain of LNA (S21). We see that the gain peaks at 1.6 GHz reaching a value of 14.8 dB. The high gain gain is achieved due to resonating load and the spread in gain is due to the use of RL resistor. The Fig. 5 plots input return loss (S11), output return loss (S22) and reverse isolation (S12). The noise figure is plotted in Fig. 6. A very low noise figure of 0.73 dB is obtained at 1.6 GHz. High S21 and low NF is the result of simultaneous power and input matching. The stability of the LNA designed has also been investigated. Rollets stability factor (Kf) is given in Fig. 7. The parameter delta ( ) defined by eqn. (7) is plotted in Fig. 8. As Kf is greater than unity and is less than unity over the frequency range from 1.2 GHz to 2 GHz, the LNA is found to be stable over this range [1]. = S 11S 22 S 21S 12 (7)
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Fig. 4 Gain (dB) of LNA versus frequency (GHz)
Fig. 5 Input return loss (S11), output return loss (S22) and reverse isoloation (S12) versus frequency (GHz)
Fig. 6 Noise Figure (dB) of LNA versus frequency (GHz)
Fig. 7 Rollets stability factor (Kf) versus frequency (GHz)

42
Fig. 8 The parameter delta ( ) versus frequency (GHz)
4. Conclusions
A high gain, Low-noise amplifier is designed in cascode configuration using SiGe BiCMOS technology. The LNA has a dc power constraint of 2 mW. It exhibits gain of 14.8 dB, noise figure of 0.96 dB at 1.6 GHz.
5. Acknowledgements
Authors would like to acknowledge Prof. S. Qureshi for providing laboratory facilities and IHP microelectronics, Germany for providing process design kit.
6. References
[1] D. K. Shaeffer and T. H. Lee, A 1.5-V, 1.5-GHz CMOS low noise amplifier, IEEE J. Solid-State Circuits, vol. 32, pp. 745-759, May 1997. [2] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge, U.K.: Cambridge Univ. Press, 1998. [3] Cressler, J. D. and Niu, G., Silicon-Germanium Heterojunction Bipolar Transistors, Boston: Artech House, 2003. [4] P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th edition, John Wiley and sons, 2001. [5] J. Rogers, C. Plett, Radio Frequency Integrated Circuit Design, Artech House, 2003. [6] S. P. Voinigescu, M. Maliepaard, J. Showell, G. Babcock, D. Marchesan, M. Schroeter, P. Schvan, and D. L. Harame, A scalable high-frequency noise model for bipolar transistors with application to optimal transistorsizing for low-noise amplifier design, IEEE J. Solid-State Circuits, vol.32, pp. 14301439, Sept. 1997. [7] Thrivikraman, T. K., Kuo, W. M. L., Comeau, J. P., Sutton, A. K., Cressler, J. D., Marshall, P. W., and Mitchell, M. A., "A 2 mW, sub-2 dB noise figure, sige low-noise amplifier for X-band high-altitude or space-based radar applications," in Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE, pp. 629-632, 2007. [8] A. Bevilacqua and A. Niknejad, An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers, in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 2004, pp. 382383.
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2011 International Conference on Circuits, System and Simulation IPCSIT vol.

7 (2011) (2011) IACSIT Press, Singapore

Design of Low Power LNA for GPS Application

Department of Electrical Engineering, Indian Institute of Technology Kanpur (IITK)

2. Design of Low Noise Amplifier

If gm2ro1>>o and o>>1, then the output resistance is given by:

where o is current gain. The voltage gain is given by:

Fig. 1 Small signal equivalent of cascode

3. LNA Simulation Results

Fig. 4 Gain (dB) of LNA versus frequency (GHz)

Fig. 6 Noise Figure (dB) of LNA versus frequency (GHz)

Fig. 7 Rollets stability factor (Kf) versus frequency (GHz)

Fig. 8 The parameter delta ( ) versus frequency (GHz)

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