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XC2C64A CoolRunner-II CPLD

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DS311 (v2.3) November 19, 2008

Product Specification

Features
Optimized for 1.8V systems - As fast as 4.6 ns pin-to-pin logic delays - As low as 15 A quiescent current Industrys best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation 1.5V to 3.3V Available in multiple package options - 44-pin VQFP with 33 user I/Os - 48-land QFN with 37 user I/Os - 56-ball CP BGA with 45 user I/Os - 100-pin VQFP with 64 user I/Os - Pb-free available for all packages Advanced system features - Fastest in system programming 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Two separate I/O banks - RealDigital 100% CMOS product term generation - Flexible clocking modes Optional DualEDGE triggered registers - Global signal options with macrocell control Multiple global clocks with phase selection per macrocell Multiple global output enables Global set/reset - Efficient control term clocks, output enables, and set/resets for each macrocell and shared across function blocks - Advanced design security - Optional bus-hold, 3-state, or weak pullup on selected I/O pins - Open-drain output option for Wired-OR and LED drive - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels - PLA architecture Superior pinout retention 100% product term routability across function block - Hot pluggable

Description
The CoolRunner-II 64-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. This device consists of four Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain, and programmable grounds. A Schmitt trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers can be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset, and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. The CoolRunner-II 64-macrocell CPLD is I/O compatible with standard LVTTL and LVCMOS18, LVCMOS25, and LVCMOS33 (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II 64A macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.

Refer to the CoolRunner-II family data sheet for architecture description.

20042008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS311 (v2.3) November 19, 2008 Product Specification

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XC2C64A CoolRunner-II CPLD

RealDigital Design Technology

Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II CPLDs employ RealDigital, a design technique that makes use of CMOS technology in both the fabrication and design methodology. RealDigital design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx CoolRunner-II CPLDs achieve both high performance and low power operation.

LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applications. CoolRunner-II CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XC2C64A IOSTANDARD Output Attribute VCCIO LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15(1)
1.

Input VCCIO 3.3 3.3 2.5 1.8 1.5

Input VREF N/A N/A N/A N/A N/A

Board Termination Voltage VT N/A N/A N/A N/A N/A

3.3 3.3 2.5 1.8 1.5

Supported I/O Standards

The CoolRunner-II 64 macrocell features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an

LVCMOS15 requires Schmitt-trigger inputs.

20

15

ICC (mA)

10

0 0 50 100 150 200 250

Frequency (MHz)
DS092_01_092302

Figure 1: ICC vs Frequency Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25C)(1) Frequency (MHz) 0 Typical ICC (mA) 0.017 25 1.8 50 3.7 75 5.5 100 7.48 150 11.0 175 12.7 200 14.6 225 15.3 240 17.77

Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block).

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DS311 (v2.3) November 19, 2008 Product Specification

XC2C64A CoolRunner-II CPLD

Absolute Maximum Ratings

Symbol VCC VCCIO VJTAG(2) VCCAUX VIN(1) VTS(1) VSTG(3) TJ Description Supply voltage relative to ground Supply voltage for output drivers JTAG input voltage limits JTAG input supply voltage Input voltage relative to ground(1) Voltage applied to 3-state output(1) Storage Temperature (ambient) Junction Temperature Value 0.5 to 2.0 0.5 to 4.0 0.5 to 4.0 0.5 to 4.0 0.5 to 4.0 0.5 to 4.0 65 to +150 +150 Units V V V V V V C C

Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins might undershoot to 2.0V or overshoot to +4.5V, provided this overshoot or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free packages, see XAPP427.

Recommended Operating Conditions

Symbol VCC VCCIO Parameter Supply voltage for internal logic and input buffers Commercial TA = 0C to +70C Industrial TA = 40C to +85C Min 1.7 1.7 3.0 2.3 1.7 1.4 1.7 Max 1.9 1.9 3.6 2.7 1.9 1.6 3.6 Units V V V V V V V

Supply voltage for output drivers @ 3.3V operation Supply voltage for output drivers @ 2.5V operation Supply voltage for output drivers @ 1.8V operation Supply voltage for output drivers @ 1.5V operation

VCCAUX

JTAG programming pins

DC Electrical Characteristics Over Recommended Operating Conditions

Symbol ICCSB ICCSB ICC(1) CJTAG CCLK CIO IIL(2) IIH(2) Parameter Standby current Commercial Standby current Industrial Dynamic current JTAG input capacitance Global clock input capacitance I/O capacitance Input leakage current I/O High-Z leakage Test Conditions VCC = 1.9V, VCCIO = 3.6V VCC = 1.9V, VCCIO = 3.6V f = 1 MHz f = 50 MHz f = 1 MHz f = 1 MHz f = 1 MHz VIN = 0V or VCCIO to 3.9V VIN = 0V or VCCIO to 3.9V Typical 31 43 Max. 100 165 500 5 10 12 10 +/1 +/1 Units A A A mA pF pF pF A A

Notes: 1. 16-bit up/down, Resetable binary counter (one counter per function block) tested at VCC=VCCIO= 1.9V. 2. See Quality and Reliability section of the CoolRunner-II family data sheet.

DS311 (v2.3) November 19, 2008 Product Specification

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XC2C64A CoolRunner-II CPLD

LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications

Symbol VCCIO VIH VIL VOH VOL Parameter Input source voltage High level input voltage Low level input voltage High level output voltage IOH = 8 mA, VCCIO = 3V IOH = 0.1 mA, VCCIO = 3V Low level output voltage IOL = 8 mA, VCCIO = 3V IOL = 0.1 mA, VCCIO = 3V Test Conditions Min. 3.0 2 0.3 VCCIO 0.4V VCCIO 0.2V Max. 3.6 3.9 0.8 0.4 0.2 Units V V V V V V V

LVCMOS 2.5V DC Voltage Specifications

Symbol VCCIO VIH VIL VOH VOL
1.

Parameter Input source voltage High level input voltage Low level input voltage High level output voltage

Test Conditions

Min. 2.3 1.7 0.3

Max. 2.7
VCCIO +

Units V V V V V V V

0.3(1)

0.7 0.4 0.2

IOH = 8 mA, VCCIO = 2.3V IOH = 0.1 mA, VCCIO = 2.3V IOL = 8 mA, VCCIO = 2.3V IOL = 0.1 mA, VCCIO = 2.3V

VCCIO 0.4V VCCIO 0.2V -

Low level output voltage

The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V without physical damage.

LVCMOS 1.8V DC Voltage Specifications

Symbol VCCIO VIH VIL VOH VOL
1.

Parameter Input source voltage High level input voltage Low level input voltage High level output voltage

Test Conditions IOH = 8 mA, VCCIO = 1.7V IOH = 0.1 mA, VCCIO = 1.7V IOL = 8 mA, VCCIO = 1.7V IOL = 0.1 mA, VCCIO = 1.7V

Min. 1.7 0.65 x VCCIO 0.3 VCCIO 0.45 VCCIO 0.2 -

Max. 1.9
VCCIO + 0.3(1)

Units V V V V V V V

0.35 x VCCIO 0.45 0.2

Low level output voltage

The VIH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V without physical damage.

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DS311 (v2.3) November 19, 2008 Product Specification

XC2C64A CoolRunner-II CPLD

LVCMOS 1.5V DC Voltage Specifications

Symbol VCCIO VT+ VTVOH VOL High level output voltage Parameter(1) Input source voltage Input hysteresis threshold voltage Test Conditions IOH = 8 mA, VCCIO = 1.4V IOH = 0.1 mA, VCCIO = 1.4V Low level output voltage IOL = 8 mA, VCCIO = 1.4V IOL = 0.1 mA, VCCIO = 1.4V
Notes: 1. Hysteresis used on 1.5V inputs.

Min. 1.4 0.5 x VCCIO 0.2 x VCCIO VCCIO 0.45 VCCIO 0.2 -

Max. 1.6 0.8 x VCCIO 0.5 x VCCIO 0.4 0.2

Units V V V V V V V

Schmitt Trigger Input DC Voltage Specifications

Symbol VCCIO VT+ VTParameter Input source voltage Input hysteresis threshold voltage Test Conditions Min. 1.4 0.5 x VCCIO 0.2 x VCCIO Max. 3.9 0.8 x VCCIO 0.5 x VCCIO Units V V V

DS311 (v2.3) November 19, 2008 Product Specification

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XC2C64A CoolRunner-II CPLD

AC Electrical Characteristics Over Recommended Operating Conditions

-5 Symbol TPD1 TPD2 TSUD TSU1 TSU2 THD TH TCO FTOGGLE(1) FSYSTEM1(2) FSYSTEM2(2) FEXT1(3) FEXT2(3) TPSUD TPSU1 TPSU2 TPHD TPH TPCO TOE/TOD TPOE/TPOD TMOE/TMOD TPAO TAO TSUEC THEC TCW TPCW TAPRPW TCONFIG(4) Parameter Propagation delay single p-term Propagation delay OR array Direct input register clock setup time Setup time (single p-term) Setup time (OR array) Direct input register hold time P-term hold time Clock to output Internal toggle rate(1) Maximum system frequency(2) Maximum system frequency(2) Maximum external frequency(3) Maximum external frequency(3) Direct input register p-term clock setup time P-term clock setup time (single p-term) P-term clock setup time (OR array) Direct input register p-term clock hold time P-term clock hold P-term clock to output Global OE to output enable/disable P-term OE to output enable/disable Macrocell driven OE to output enable/disable P-term set/reset to output valid Global set/reset to output valid Register clock enable setup time Register clock enable hold time Global clock pulse width High or Low P-term pulse width High or Low Asynchronous preset/reset pulse width (High or Low) Configuration time Min. 2.4 2.0 2.4 0 0 0.9 0.6 1.0 1.3 1.5 3.0 0 1.4 5.0 5.0 Max. 4.6 5.0 3.9 500 263 238 169 159 6.0 8.0 9.0 9.0 7.3 6.0 50.0 Min. 3.3 2.5 3.3 0 0 1.7 0.9 1.7 1.4 1.7 3.7 0 2.2 7.5 7.5 -7 Max. 6.7 7.5 6.0 300 159 141 118 108 8.4 10.0 11.0 11.0 9.7 8.3 50.0 Units ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s

Notes: 1. FTOGGLE is the maximum frequency of a dual edge triggered T flip-flop with output enabled. 2. FSYSTEM (1/TCYCLE) is the internal operating frequency for a device fully populated with 16-bit up/down, Resetable binary counter (one counter per function block). 3. FEXT (1/TSU1+TCO) is the maximum external frequency. 4. Typical configuration current during TCONFIG is 2.3 mA.

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DS311 (v2.3) November 19, 2008 Product Specification

XC2C64A CoolRunner-II CPLD

Internal Timing Parameters

-5 Symbol
Buffer Delays

-7 Max. Min. Max. Units

Parameter(1)

Min.

TIN TDIN TGCK TGSR TGTS TOUT TEN

P-term Delays

Input buffer delay Direct data register input delay Global clock buffer delay Global set/reset buffer delay Global 3-state buffer delay Output buffer delay Output buffer enable/disable delay

1.7 2.6 1.6 2.4 2.7 1.9 5.3

2.4 4.0 2.5 3.5 3.9 2.8 6.1

ns ns ns ns ns ns ns

TCT TLOGI1 TLOGI2

Macrocell Delay

Control term delay Single P-term delay adder Multiple P-term delay adder

2.0 0.5 0.4

2.5 0.8 0.8

ns ns ns

TPDI TSUI THI TECSU TECHO TCOI TAOI TCDBL

Feedback Delays

Input to output valid Setup before clock Hold after clock Enable clock setup time Enable clock hold time Clock to output valid Set/reset to output valid Clock doubler delay

1.4 0.0 0.9 0 -

0.5 0.4 1.7 0

1.8 0.0 1.3 0 -

0.7 0.7 2.0 0

ns ns ns ns ns ns ns ns

TF TOEM THYS15 TOUT15 TSLEW15 THYS18 TOUT18 TSLEW

Feedback delay Macrocell to global OE delay

1.5 1.7

3.0 1.7

ns ns

I/O Standard Time Adder Delays 1.5V CMOS

Hysteresis input adder Output adder Output slew rate adder

4.0 0.9 4.0

6.0 1.5 6.0

ns ns ns

I/O Standard Time Adder Delays 1.8V CMOS

Hysteresis input adder Output adder Output slew rate adder

3.0 0 3.5

4.0 0 5.0

ns ns ns

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XC2C64A CoolRunner-II CPLD

Internal Timing Parameters (Continued)

-5 Symbol Parameter(1) Min. Max. Min. -7 Max. Units

I/O Standard Time Adder Delays 2.5V CMOS

TIN25 THYS25 TOUT25 TSLEW25 TIN33 THYS33 TOUT33 TSLEW33

1.

Standard input adder Hysteresis input adder Output adder Output slew rate adder

0.5 2.5 0.8 4.0

0.6 3.0 0.9 5.0

ns ns ns ns

I/O Standard Time Adder Delays 3.3V CMOS/TTL

Standard input adder Hysteresis input adder Output adder Output slew rate adder

0.5 2.0 1.2 4.0

0.6 3.0 1.4 5.0

ns ns ns ns

1.5 ns input pin signal rise/fall.

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DS311 (v2.3) November 19, 2008 Product Specification

XC2C64A CoolRunner-II CPLD

Switching Characteristics
VCC = VCCIO = 1.8V, T = 25oC
5.5

Typical I/O Output Curves

Vdde1

I/O Output Current (mA)

1.5V 1.8V 2.5V 3.3V

5.0

4.5

TPD2 (ns)

4.0

3.5

3.0 1 2 4 8 16

Vo Output Volts

Figure 4: Typical I/O Output Curves

Number of Outputs Switching

DS092_02_092302

Figure 2: Derating Curve for TPD

AC Test Circuit
VCC R1 Device Under Test R2 CL Test Point

Output Type LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15

R1 268 275 188 112.5 150

R2 235 275 188 112.5 150

CL 35 pF 35 pF 35 pF 35 pF 35 pF

Notes: 1. CL includes test fixtures and probe capacitance. 2. 1.5 ns maximum rise/fall times on inputs.
DS311_03_102108

Figure 3: AC Load Circuit

DS311 (v2.3) November 19, 2008 Product Specification

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XC2C64A CoolRunner-II CPLD

Pin Descriptions
Function Block 1 1 1 1 1 1 1 1 1(GTS1) 1(GTS0) 1(GTS3) 1(GTS2) 1(GSR) 1 1 1 2 2 2 2 2 2 2(GCK0) 2(GCK1) 2 2(GCK2) 2 2 2 2 2 2 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PC44(1) 44 43 42 40 39 38 37 36 1 2 3 4 5 6 7 8 9 VQ44 38 37 36 34 33 32 31 30 39 40 41 42 43 44 1 2 3 14 15 13 11 12 6 7 8 9 10 2 1 48 47 46 5 4 QFG48 CP56 F1 E3 E1 D1 C1 A3 A2 B1 A1 C3 G1 F3 H1 G3 J1 K1 K4 K2 K3 H3 K5 VQ100 13 12 11 10 9 8 7 6 4 3 2 1 99 97 94 92 14 15 16 17 18 19 22 23 24 27 28 29 30 32 33 34 I/O Banking Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1

10

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DS311 (v2.3) November 19, 2008 Product Specification

XC2C64A CoolRunner-II CPLD

Pin Descriptions (Continued)

Function Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
1. 2. 3.

Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PC44(1) 35 34 33 29 28 27 26 25 24 11 12 14 18 19 20 22 -

VQ44 29 28 27 23 22 21 20 19 18 5 6 8 12 13 14 16 -

QFG48 45 44 43

CP56 C4 A4 C5 A7

VQ100 91 90 89 81 79 78 77 76 74 72 71 70 68 67 64 61 35 36 37 39 40 41 42 43 49 50 52 53 55 56 58 60

I/O Banking Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 2 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1 Bank 1

39 38

C8 A8 A9 -

37 36 35 34

A5 A10 B10 C10 D8

33 32

E8 D10 -

17 18

K6 H5 K7 H7 -

20

H8 -

24 25 26 27 28

K8 H10 G10 F10

30

E10

This is an obsolete package type. It remains here for legacy support only. GTS = global output enable, GSR = global set reset, GCK = global clock. GCK, GSR, and GTS pins can also be used for general purpose I/Os.

DS311 (v2.3) November 19, 2008 Product Specification

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XC2C64A CoolRunner-II CPLD

XC2C64A Global, JTAG, Power/Ground, and No Connect Pins

Pin Type TCK TDI TDO TMS VCCAUX (JTAG supply voltage) Power internal (VCC) Power bank 1 I/O (VCCIO1) Power bank 2 I/O (VCCIO2) Ground No connects PC44(1) 17 15 30 16 41 21 13 32 10, 23, 31 VQ44 11 9 24 10 35 15 7 26 4,17,25 QFG48 23 21 40 22 3 29 19 42 16, 31, 41 CP56 K10 J10 A6 K9 D3 G8 H6 C6 H4, F8, C7 VQ100 48 45 83 47 5 26,57 38, 51 88, 98 21, 31, 62, 69, 84,100 20, 25, 44, 46, 54, 59, 63, 65, 66, 73, 75, 80, 82, 85, 86, 87, 93, 95, 96 33 33 37 45 64

Total user I/O

1.

This is an obsolete package type. It remains here for legacy support only.

Ordering Information
Device Ordering No. Pin/Ball JA JC and Part Marking No. Spacing (C/Watt) ({C/Watt) XC2C64A-5QFG48C XC2C64A-7QFG48C XC2C64A-5VQ44C XC2C64A-7VQ44C XC2C64A-5CP56C XC2C64A-7CP56C XC2C64A-5VQ100C XC2C64A-7VQ100C XC2C64A-5VQG44C XC2C64A-7VQG44C XC2C64A-5CPG56C XC2C64A-7CPG56C XC2C64A-5VQG100C XC2C64A-7VQG100C XC2C64A-7VQ44I XC2C64A-7QFG48I XC2C64A-7CP56I XC2C64A-7VQ100I 0.5mm 0.5mm 0.8mm 0.8mm 0.5mm 0.5mm 0.5mm 0.5mm 0.8mm 0.8mm 0.5mm 0.5mm 0.5mm 0.5mm 0.8mm 0.5mm 0.5mm 0.5mm 31.2 31.2 46.6 46.6 65.0 65.0 53.2 53.2 46.6 46.6 65.0 65.0 53.2 53.2 46.6 31.2 65.0 53.2 21.2 21.2 8.2 8.2 15.0 15.0 14.6 14.6 8.2 8.2 15.0 15.0 14.6 14.6 8.2 21.2 15.0 14.6 Package Type Quad Flat No Lead Quad Flat No Lead Very Thin Quad Flat Pack Very Thin Quad Flat Pack Chip Scale Package Chip Scale Package Very Thin Quad Flat Pack Very Thin Quad Flat Pack Very Thin Quad Flat Pack; Pb-free Very Thin Quad Flat Pack; Pb-free Chip Scale Package; Pb-free Chip Scale Package; Pb-free Very Thin Quad Flat Pack; Pb-free Very Thin Quad Flat Pack; Pb-free Very Thin Quad Flat Pack Quad Flat No Lead; Pb-free Chip Scale Package Very Thin Quad Flat Pack Package Body Dimensions 7mm x 7mm 7mm x 7mm 10mm x 10mm 10mm x 10mm 6mm x 6mm 6mm x 6mm 14mm x 14mm 14mm x 14mm 10mm x 10mm 10mm x 10mm 6mm x 6mm 6mm x 6mm 14mm x 14mm 14mm x 14mm 10mm x 10mm 7mm x 7mm 6mm x 6mm 14mm x 14mm Comm(C) I/O Ind. (I)(1) 37 37 33 33 45 45 64 64 33 33 45 45 64 64 33 37 45 64 C C C C C C C C C C C C C C I I I I

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DS311 (v2.3) November 19, 2008 Product Specification

XC2C64A CoolRunner-II CPLD

Device Ordering No. Pin/Ball JA JC and Part Marking No. Spacing (C/Watt) ({C/Watt) XC2C64A-7VQG44I XC2C64A-7CPG56I XC2C64A-7VQG100I 0.8mm 0.5mm 0.5mm 46.6 65.0 53.2 8.2 15.0 14.6

Package Type Very Thin Quad Flat Pack; Pb-free Chip Scale Package; Pb-free Very Thin Quad Flat Pack; Pb-free

Package Body Dimensions 10mm x 10mm 6mm x 6mm 14mm x 14mm

Comm(C) I/O Ind. (I)(1) 33 45 64 I I I

Notes: 1. C = Commercial (TA = 0C to +70C); I = Industrial (TA = 40C to +85C).

Standard Example: XC2C128 Device Speed Grade Package Type Number of Pins Temperature Range

-4 TQ

144

Pb-Free Example: XC2C128 Device Speed Grade Package Type Pb-Free Number of Pins Temperature Range

-4 TQ

144

Device Part Marking

Device Type Package Speed Operating Range

XC2Cxxx TQ144 7C

This line not related to device part number

Part marking for non-chip scale package

DS311_05_102108

Figure 5: Sample Package with Part Marking Note: Due to the small size of chip scale and quad flat no lead packages, the complete ordering part number cannot be included on the package marking. Part marking on chip scale and quad flat no lead packages by line are: 1. X (Xilinx logo) then truncated part number 2. Not related to device part number 3. Not related to device part number 4. Device code, speed, operating temperature, three digits not related to device part number. Device codes: C3 = CP56, C4 = CPG56, Q2 = QFG48.

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XC2C64A CoolRunner-II CPLD

Package Pinout Diagrams

I/O(2) I/O(2) I/O I/O I/O I/O I/O I/O I/O VAUX I/O(1)

I/O(2) I/O I/O GND I/O I/O VCCIO1 I/O TDI TMS TCK

12 13 14 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

VQ44 Top View

33 32 31 30 29 28 27 26 25 24 23

I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O

(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset

K
I/O(2) I/O(2) I/O I/O I/O I/O I/O I/O I/O VAUX I/O(1)

I/O(2) I/O(2)

I/O(2)

I/O

I/O

I/O

I/O

I/O

I/O

TMS

TCK

J H
I/O(1) I/O(1) I/O(1) I/O(3) I/O I/O I/O VCCIO2 Gnd TDO I/O

TDI

I/O

I/O

GND

I/O

VCCIO1

I/O

I/O

I/O

6 5 4 3 2 1 44 43 42 41 40

I/O(2) I/O I/O GND I/O I/O VCCIO1 I/O TDI TMS TCK

18 19 20 21 22 23 24 25 26 27 28

7 8 9 10 11 12 13 14 15 16 17

PC44 Top View

39 38 37 36 35 34 33 32 31 30 29

G F E D C B A

I/O

I/O

VCC

I/O

I/O

I/O

CP56 Bottom View

GND

I/O

I/O I/O(1) I/O(1) I/O(3) I/O(1)

I/O

I/O

I/O

VAUX I/O I/O I/O VCCIO2 GND

I/O

I/O

I/O

I/O

I/O I/O(1)

I/O

I/O

I/O

TDO

I/O

I/O

I/O

I/O

I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O

(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset

(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset

Figure 7: PC44 Package (Obsolete package shown for legacy support only)

Figure 9: CP56 Package

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DS311 (v2.3) November 19, 2008 Product Specification

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Figure 6: VQ44 Package

I/O(2) I/O I/O Gnd I/O I/O Vccio1 I/O TDI TMS TCK I/O
(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset

13 14 15 16 17 18 19 20 21 22 23 24

I/O(1) I/O(1) I/O(1) I/O(3) I/O I/O I/O VCCIO2 GND TDO I/O

I/O(1) I/O(1) VAUX I/O I/O I/O I/O I/O I/O I/O I/O(2) I/O(2)

48 47 46 45 44 43 42 41 40 39 38 37

I/O(1) I/O(1) I/O(3) I/O I/O I/O Vccio2 Gnd TDO I/O I/O I/O
1 2 3 4 5 6 7 8 9 10 11 12

QFG48 Top View

36 35 34 33 32 31 30 29 28 27 26 25

I/O I/O I/O I/O I/O Gnd I/O Vcc I/O I/O I/O I/O

44 43 42 41 40 39 38 37 36 35 34

Figure 8: QFG48 Package

XC2C64A CoolRunner-II CPLD

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

GND I/O(3) VCCIO2 I/O NC NC I/O NC I/O I/O I/O I/O VCCIO2 NC NC NC GND TDO NC I/O NC I/O I/O I/O I/O

I/O(1) I/O(1) I/O(1) I/O(1) VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND I/O(2) I/O(2) I/O NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

VQ100 Top View

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

(1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset

Figure 12: VQ100 Package

Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS.

DS311 (v2.3) November 19, 2008 Product Specification

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VCCIO1 I/O I/O I/O I/O I/O NC TDI NC TMS TCK I/O I/O

VCC I/O(2) I/O I/O I/O GND I/O I/O I/O I/O I/O I/O

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NC I/O NC I/O I/O I/O GND I/O I/O NC NC I/O NC GND I/O I/O NC I/O Vcc I/O I/O NC I/O I/O VCCIO1

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XC2C64A CoolRunner-II CPLD

Additional Information
Additional information is available for the following CoolRunner-II CPLD topics at www.xilinx.com/support/documentation/coolrunner-ii.htm: Device pinouts in the density specific data sheets Termination, power sequencing, voltage thresholds, and slew rate data in the CPLD IO User Guide Reliability data in the Device Reliability Report Packaging thermal and electrical data in the Device Package User Guide

Package drawings and dimensions are available at:

www.xilinx.com/support/documentation/package_specifications.htm

Revision History
The following table shows the revision history for this document. Date 5/15/04 8/30/04 10/01/04 11/08/04 11/29/04 12/14/04 01/18/05 03/07/05 06/28/05 01/30/06 03/20/06 02/15/07 03/08/07 11/19/08 Version 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 Initial Xilinx release. Pb-free documentation Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics. Product Release. No change to documentation. Change to QFG package drawing (Figure 8). Pin 29 relabelled. Changes to Figure 4, Typical I/O Output Curves; Changes to tOUT25 and tOUT33, Internal Timing Parameters, page 8. Changes to ICCSB, fTOGGLE, tPSU1, tPSU2, tPHD, tCW, tSLEW25, and tSLEW33 Format change to specifications IIL and IIH, page 3. Improvement to pin-to-pin logic delay, page 1. Modifications to Table 1, IOSTANDARDs. Move to Product Specification. Change to TIN25, TOUT25, TIN33, and TOUT33. Modified footnote 1 from AC Specifications Table to remove incorrect equation. Add Warranty Disclaimer. Add note to Pin Descriptions that GCK, GSR, and GTS pins can also
be used for general purpose I/O.

Revision

Change to VIH specification for 2.5V and 1.8V LVCMOS. Change TF specification on -7 speed grade from 2.0 to 3.0 ns. Fixed typo in note for VIL for LVCMOS18; removed note for VIL for LVCMOS33. Added note to Pin Description tables to indicate the PC44 packages are obsolete. Removed part numbers for devices in PC44 packages the Features section and from the ordering information. See Product Discontinuation Notice xcn07022.pdf.

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DS311 (v2.3) November 19, 2008 Product Specification