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Verilog Implementation of Single Cycle Microprocessor

This document contains Verilog code for implementing various components of a single cycle microprocessor including an ALU, ALU control unit, register file, data memory, PC, adder, multiplexers, shift left module, sign extension module, main control unit, and instruction memory. The code samples provided implement the logic for each component module using basic Verilog constructs like always blocks, case statements, and assign statements.

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Abhinav Jha
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590 views13 pages

Verilog Implementation of Single Cycle Microprocessor

This document contains Verilog code for implementing various components of a single cycle microprocessor including an ALU, ALU control unit, register file, data memory, PC, adder, multiplexers, shift left module, sign extension module, main control unit, and instruction memory. The code samples provided implement the logic for each component module using basic Verilog constructs like always blocks, case statements, and assign statements.

Uploaded by

Abhinav Jha
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Verilog Implementation of single cycle Microprocessor Assignment CMA Lab

ByAbhinav Jha (08-EE-243) Mommadh Rifadh (08-EE-216)

CODE FOR ALU

module ALU(ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output Zero; assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 always @(ALUctl, A, B) begin //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1 : 0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; endcase end endmodule

CODE FOR ALU CONTROL

module ALUControl(ALUOp, FuncCode, ALUCtl); input [1:0] ALUOp; input [5:0] FuncCode; output reg [3:0] ALUCtl; always @(ALUOp, FuncCode) begin if ( ALUOp == 2 ) case (FuncCode) 32: ALUCtl<=2; // add 34: ALUCtl<=6; //subtract 36: ALUCtl<=0; // and 37: ALUCtl<=1; // or 39: ALUCtl<=12; // nor 42: ALUCtl<=7; // slt default: ALUCtl<=15; // should not happen endcase else case (ALUOp) 0: ALUCtl<=2; 1: ALUCtl<=6; default: ALUCtl<=15; // should not happen endcase end endmodule

CODE FOR REGISTER FILE

module RegFile(ra1, rd1 , ra2 , rd2 , clk , RegWrite , wa ,wd ); input[4:0] ra1; output[31:0] rd1; input[4:0] ra2; output[31:0] rd2; input clk; input[4:0] wa; input[31:0] wd; reg [31:0] registers[31:0]; assign rd1 = registers[ra1]; assign rd2 = registers[ra2]; always@ ( posedge clk ) if (RegWrite) registers[wa] <= wd; endmodule

CODE FOR DATA MEMORY

module data_mem(clk,read,write,address,write_data,read_data); input clk , read , write; input [31:0] address, write_data; output reg[31:0] read_data; reg [31:0] mem[255:0]; always@(read,write,address,write_data) begin if (read) read_data=mem[address]; end always @(posedge clk) begin if (write) mem[address]<=write_data; end endmodule

CODE FOR PC

module pc(clk,reset,data_in,data_out); input clk,reset; input [31:0] data_in; output reg data_out; always@(posedge clk) if(reset) data_out<=0; else data_out<=data_in; endmodule

CODE FOR ADDER

module adder(A,B,sum); input [31:0] A,B; output [31:0] sum; assign sum=A+B; endmodule

CODE FOR mux1

module mux1(a, b, sel,y); input [4:0] a; input [4:0] b; input sel; output reg [4:0] y; always@* case(sel) 0:y=a; 1:y=b; endcase endmodule

CODE FOR mux2

module mux2(a, b, sel,y); input [31:0] a; input [31:0] b; input sel; output reg [4:0] y; always@* case(sel) 0:y=a; 1:y=b; endcase endmodule

CODE FOR shift left

module shift_left(x, y); input [31:0] x; output [31:0] y; assign y={x[29:0],2'b00}; endmodule

CODE FOR SIGN EXTEND


module sign_extend(x, y); input [15:0] x; output [31:0] y; assign y={ x[15], x[15], x[15], x[15], x[15], x[15], x[15], x[15], x[15], x[15], x[15], x[15], x[15], x[15], x[15], x[15],x}; endmodule

MAIN CONTROL UNIT


module main_control_unit(opcode,RegDst,Jump,MemRead,MemtoRrg,ALUop,Memwrite,AluSrc,Regwrite); input [5:0] opcode; output reg RegDst,Jump,branch,MemRead,MemtReg,MemWrite,ALUsrc,regWrite; output reg[1:0] ALUop; always @(opcode) case(opcode) 6b000000; / /R_format begin RegDst=1b1;ALUsrc=1b0;MemRead=1b0; MemWrite=1b0;Branch=1b0;ALUop=2b10; Jump=1b0; end 6b100011; //load word begin RegDst=1b0;ALUsrc=1b1;MemtoReg=1b1 RegWrite=1b1;MemRead=1b1; MemWrite=1b0;Branch=1b0;ALUop=2b00; Jump=1b0; end 6b101011; //store word begin RegDst=1bx;ALUsrc=1b1;MemtoReg=1bx RegWrite=1b0;MemRead=1b0; MemWrite=1b1;Branch=1b0;ALUop=2b00; Jump=1b0; end 6b000100; //beq begin RegDst=1bx;ALUsrc=1b0;MemtoReg=1bx RegWrite=1b0;MemRead=1b0; MemWrite=1b0;Branch=1b1;ALUop=2b01; Jump=1b0; end 6b000010; //jump begin RegDst=1bx;ALUsrc=1bx;MemtoReg=1bx RegWrite=1b0;MemRead=1b0; MemWrite=1b0;Branch=1bx;ALUop=2bxx; Jump=1b1; end endcase endmodule

CODE FOR Instruction Memory

module instruction_memory(read_adder, instruction); input [31:0] read_adder; output [31:0] instruction; reg [31:0] ROM; always @(read_adder) case (read_adder) 00: ROM=32'h8c_08_00_00; 04: ROM=32'h8c_09_00_01; 08: ROM=32'h01_09_50_20; 12: ROM=32'hAC_0A_00_02; 16: ROM=32'h8c_10_00_64; 20: ROM=32'h8c_11_00_65; 24: ROM=32'h02_30_88_22; 28: ROM=32'h12_29_00_18; 128: ROM=32'h01_10_90_24; 132: ROM=32'h02_4A_90_25; 136: ROM=32'h01_31_90_2A; 140: ROM=32'h08_00_00_00; endcase assign instruction=ROM; endmodule

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