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Low Power Design: Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

The document discusses power consumption in CMOS circuits. It states that power is determined by the number of nodes toggling, clock frequency, supply voltage, and load capacitance. It recommends strategies like reducing supply voltage, clock frequency, unnecessary toggling, and using low-leakage cells when performance is not critical to minimize power consumption. For energy efficiency in battery-powered systems, it also suggests techniques that do not increase computation cycles like clock gating.

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71 views14 pages

Low Power Design: Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

The document discusses power consumption in CMOS circuits. It states that power is determined by the number of nodes toggling, clock frequency, supply voltage, and load capacitance. It recommends strategies like reducing supply voltage, clock frequency, unnecessary toggling, and using low-leakage cells when performance is not critical to minimize power consumption. For energy efficiency in battery-powered systems, it also suggests techniques that do not increase computation cycles like clock gating.

Uploaded by

sibint_2
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Low Power Design

Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

Power Consumption
Why is power consumption important? Battery powered devices
Maximize battery life

Minimize cost of wall-powered systems


Plastic packaging is 10x cheaper than ceramic packaging but can only dissipate 1 - 2 W
What happens if the chip gets too hot?

Need a fan to cool somewhere above 10 W Difficult to air cool at all somewhere above 50-100 W Cost of power supply

`Green systems
Minimize pollution by reducing demand from power stations
Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

Power Consumption
Power is increasingly the MAJOR constraint on system performance
The major constraint used to be #transistors/die. Now it is power. Wireless systems
System Performance is limited by how much data can be communicated and processed on a single battery charge
Want this capacity to permit a battery life of more than a day

Desktop systems
Without attention, power consumption of circa 2008-2010 CPUs would be 1kw or more Impossible to air cool Without attention, power consumptions of chips like HDTV decoders would be 100+W Expensive to cool

Server farms and Supercomputers


Without attention, power consumption of next generation server firms would be > 20 kW requires two power resubstations, not one

Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

Power Consumption
Static CMOS Circuits:
Static Power (when circuit not switching) Leakage Sub-threshold Drain to source Gate Some libraries are starting to include low-leakage cells, or cells that can be switching to a low leakage state Dynamic Power (when logic transitions occur) `through current small during switching Toggling power when output node changes logic state

Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

CMOS Circuit
Circuit during switching event E.g. Inverter driving a load:
Power dissipated in resistors in 010 cycle = potential energy stored and released on capacitor during that cycle
Q=CVdd E=QVdd = CVdd2 P = E/T = CVdd2/T = Nswitch CVdd2 fclock

Alternative derivation:
Vdd Vdd

Q CVout dVout I C dt

When Vout 01, energy dissipated in top resistor:


E

(Vdd Vout) Idt (Vdd Vout)CdVout


0 0
Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

CVdd 2

Minimizing Power Consumption


Power consumption in a CMOS module: Power = Nswitch f Vcc2 Cload + leakage power
Sum over all nodes in circuit f = clock frequency Nswitch = average % of clock periods in which node toggles (I.e. 010 or 101) Cload = capacitance of node

Nswitch
Clock : Maximum for glitch-free logic: Logic typically has Nswitch ~ 0.1
Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

Minimizing Energy
Energy = Power.dt Energy consumption in a CMOS module: Energy = cycles nodes Nswitch f Vcc2 Cload + leakage power
f = clock frequency Nswitch = average % of clock periods in which node toggles (I.e. 010 or 101) Cload = capacitance of node

Note: Power reduction techniques do not save energy/complex operation if more cycles are needed to complete that operation
Important in energy-constrained (e.g. battery driven) systems
Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

Approaches to minimizing power consumption


Approaches to minimizing power consumption
Reduce Supply Voltage
E.g. Use low-Vdd cells in non critical paths Does reducing the clock frequency reduce the energy required to perform a complex operation? Battery-powered devices do not necessarily benefit from reducing clock frequency Reduce clock frequency or stop clock when module is idle
Usually a system design, not module level design

Reduce clock frequency

Reduce useless toggling


Use designer knowledge to identify useless switching and redesign to reduce it

Use an algorithm that reduces total number of toggles required to compute a result
Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

Approaches to minimizing power consumption


Static Power
Significant issue at 65 nm transistor sizes and smaller When performance is not an issue, use a low leakage cell library Use low leakage cells in non-critical paths Use cells with sleep transistors to reduce leakage in modules that are idle for long periods

gate

Sleep
Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

Reducing Useless toggling


Example:

reg [31:0] A, B, D; + always@(posedge clock) C begin Wasted power when C low if (C) D <= A+B; else D <= A; end 0 A
Possible ways to reduce power: B 0 + C C

A B

C
Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

Toggling Reduction
If C is low a lot
A 0 0 C assign E=C?A:0; assign F=C?B:0; D always@(posedge clock) if (C) D <= E+F; else D <= A;

+
C

Only useful if C is low more than 50% of the time.

Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

Power Reduction
Other Alternatives:
Gate the clock to register D
Smallest overhead Complicates clock design and timing Usually gated clocks only done at block level (.e.g an FPU) Used instead of 0 input to mux Must consider power overhead of register (including extra Cload on clock) Not likely to be beneficial here Might be beneficial for a larger design (e.g. multiplier)

Store previous value of A and B in a register

Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

Summary
What determines power consumed in a CMOS circuit? What strategies can you use to reduce power consumption? If Energy is the issue rather than power, what strategies are available to you?

Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

Summary
Complementary MOS transistors gives dense circuits and lower power than other circuit families
Standard Cell designs use Static CMOS Transistor speed approximated using `on resistance Ron proportional to electron/hole mobility and W/L

Hole mobility = half electron mobility


Inverter Wp = 2 Wn to make trise = tfall

To drive larger loads, increase transistor width proportionally

Power consumption important in many designs Power = Nswitch f Vcc2 Cload


Lowering voltage by one-half, quarters the power but halves the speed Turn clock frequency down when performance not needed Reduce Nswitch through good design

Synopsys University Courseware 2008 Synopsys, Inc. Lecture - 9 Developed By: Paul D. Franzon

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