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Multiple GROUP Declarations in ALF

This document discusses the use of multiple GROUP declarations in ALF timing specifications to define many-to-many timing relationships. It provides two examples of how three or more GROUP declarations could be used: 1) To specify delays between multiple busses in a cell. 2) To specify delays between an input bus and two output busses connected by a matrix pin or bidirectional pin. The document concludes that additional GROUP declarations merely allow for additional busses/pins to be specified without implying special relationships between delays.

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John Michael Williams
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78 views5 pages

Multiple GROUP Declarations in ALF

This document discusses the use of multiple GROUP declarations in ALF timing specifications to define many-to-many timing relationships. It provides two examples of how three or more GROUP declarations could be used: 1) To specify delays between multiple busses in a cell. 2) To specify delays between an input bus and two output busses connected by a matrix pin or bidirectional pin. The document concludes that additional GROUP declarations merely allow for additional busses/pins to be specified without implying special relationships between delays.

Uploaded by

John Michael Williams
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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J. M.

Williams

ALF Many-Many-Many Group Timing

v. 1.1

2004-03-03

Multiple GROUP declarations in ALF (by [email protected])


Context: In an ALF timing specification, many-to-many timing arcs
may be defined as in the following example, adapted from Fig. 28 of Library Harmonization for Timing, Draft v. 0.3 of 2004-02-23:
CELL ManyMany1 { GROUP AddressBit { 0 : 2 } GROUP DataBit { 1 : 4 } // PIN [2:0] Abus { DIRECTION = input; } PIN [1:4] Dbus { DIRECTION = output; } // VECTOR ( 01 Abus[AddressBit] -> 01 Dbus[DataBit] ) { DELAY = 1.0 { FROM { PIN = Abus[AddressBit]; } TO { PIN = Dbus[DataBit]; } } } }

The arcs in cell ManyMany1 are assigned a rise delay of 1.0 as shown in Fig. 1, with coloring to clarify the internal "fanouts" affected.

Figure 1. ALF many-to-many timing with two GROUPs declared. The arcs from different inputs are color-coded.

Problems:
A. What would be the use of three (or more) GROUP declarations in this context? B. What might be the meaning, if any, of a "many-many-many" (many3) timing specification?

J. M. Williams

ALF Many-Many-Many Group Timing

v. 1.1

2004-03-03

Solution A: Three or more GROUPs merely mean that there are three or more busses in the cell to be iterated; no special relationship need be implied among the different delays. The example cell ManyMany2 (possibly a sort of demultiplexor) shows the use of three GROUP declarations:
CELL ManyMany2 { GROUP DataInBit { 0 : 3 } GROUP DataOutBit1 { 1 : 4 } GROUP DataOutBit2 { 0 : 1 } // PIN [3:0] Din { DIRECTION = input; } PIN [1:4] Dout1 { DIRECTION = output; } PIN [1:0] Dout2 { DIRECTION = output; } // VECTOR ( 01 Din[DataInBit] -> 01 Dout1[DataOutBit1] ) { DELAY = 2.0 { FROM { PIN = Din[DataInBit]; } TO { PIN = Dout1[DataOutBit1]; } } } VECTOR ( 01 Din[DataInBit] -> 01 Dout2[DataOutBit2] ) { DELAY = 1.0 { FROM { PIN = Din[DataInBit]; } TO { PIN = Dout2[DataOutBit2]; } } } }

The arcs in cell ManyMany2 are assigned a rise delay either of 1.0 or 2.0, as shown in Fig. 2.

Figure 2. ALF many-to-many timing with three GROUPs declared. The two different delays are shown in different colors.

J. M. Williams

ALF Many-Many-Many Group Timing

v. 1.1

2004-03-03

Solution B.1: A many3 specification may be interpreted as use of three GROUP declarations in the context of a MATRIX pin. The cell ManyMany3 shows an example of three GROUP declarations in this interpretation of a many3 specification:
CELL ManyMany3 { GROUP DataInBit { 1 : 0 } GROUP DataOut1 { 3 : 1 } GROUP DataOut2 { 3 : 2 } // PIN [1:0] BitIn { DIRECTION = input; } PIN [3:1] MxOut[2:1] { DIRECTION = output; } // // Temporaries, to assign matrix pin: PIN[2:1] MxOut_tmp1, MxOut_tmp2; MxOut_tmp1 = MxOut[1]; MxOut_tmp2 = MxOut[2]; // // GROUPed arcs to MxOut[1]: // VECTOR ( 01 BitIn[DataInBit] -> 01 MxOut_tmp1[DataOut1] ) { DELAY = 1.0 { FROM { PIN = BitIn[DataInBit]; } TO { PIN = MxOut_tmp1[DataOut1]; } } } // // GROUPed arcs to MxOut[2]: // VECTOR ( 01 BitIn[DataInBit] -> 01 MxOut_tmp2[DataOut2] ) { DELAY = 2.0 { FROM { PIN = BitIn[DataInBit]; } TO { PIN = MxOut_tmp2[DataOut2]; } } } // // Leftover arcs to MxOut[2]: // VECTOR ( 01 BitIn[DataInBit] -> 01 MxOut_tmp2[0] ) { DELAY = 3.0 { FROM { PIN = BitIn[DataInBit]; } TO { PIN = MxOut_tmp2[0]; } } } }

Fig. 3 shows the timing arcs in this case. The schematic arrangement of the output nodes is arbitrary.

J. M. Williams

ALF Many-Many-Many Group Timing

v. 1.1

2004-03-03

Figure 3. ALF many-to-many timing with three GROUPs and MATRIX pin declared. Different delays are shown in different colors.

Solution B.2: A many3 specification may be interpreted as use of three GROUP declarations in the context of a bidirectional pin. The cell ManyMany4 shows an example of three GROUP declarations in this interpretation of a many3 specification:
CELL ManyMany4 { GROUP InBit { 0 : 2 } GROUP BidirBit { 1 : 3 } GROUP OutBit { 1 : 3 } // PIN [2:0] Din { DIRECTION = input; } PIN [1:3] Dbidir { DIRECTION = both; } PIN [3:1] Dout { DIRECTION = output; } // VECTOR ( 01 Din[InBit] -> 01 Dbidir[BidirBit] ) { DELAY = 1.0 { FROM { PIN = Din[InBit]; } TO { PIN = Dbidir[BidirBit]; } } } VECTOR ( 01 Dbidir[BidirBit] -> 01 Dout[OutBit] ) { DELAY = 2.0 { FROM { PIN = Dbidir[BidirBit]; } TO { PIN = Dout[OutBit]; } } } }

Fig. 4 shows the timing arcs in this case. The input and output pins imply the timing directions.

J. M. Williams

ALF Many-Many-Many Group Timing

v. 1.1

2004-03-03

Figure 4. ALF many-to-many timing with three GROUPs and bidirectional intermediate pin declared. The two different delays are shown in different colors.

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