CpE/CS 487: Digital System Design

Fall 2009

Lecture 1 Course organization and introduction

Prof. Haibo He Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07086

Course organization Instructor:

Prof. Haibo He Office: Burchard 412 Email: hhe@stevens.edu Phone: (201) 216-8057

Course schedule:
Tuesday & Thursday, 12:00 pm ~ 1:15pm

Course web site:

http://www.ece.stevens-tech.edu/~hhe/cpe487f09/class_index.htm

Office hours:
Thursday, 2: 00 pm ~ 4: 00 pm. Other hours by appointments.
2

Grading and exam information

Grading Information
-- Attendance (5%) -- Midterm examination (25%) -- Homework (20%) -- Laboratory Assignments (20%) -- Final examination (30%)

Exam time:
Midterm: TBA Final: TBD

All examinations are closed books and notes. However, students are allowed to have - one sheet for midterm/ two sheets for final - with formulas as a help during each exam.
3

Textbook and references

Textbook:

(1) VHDL - A Starter's Guide, Second Edition, Sudhakar Yalamanchili, Publisher: Prentice Hall, ISBN: 0-13-145735-7, 2005.
Recommended references (Not required): (1) A VHDL Primer, 3rd edition, J. Bhasker, Prentice Hall, ISBN 0-13-096575-8, 1999. (2) Circuit Design with VHDL, Volnei A. Pedroni, MIT Press, ISBN: 0-262-16224-5, 2004.

Laboratory

Laboratory Work:
-- Team-work (maximum 3 students/team) -- Finish the lab work on-time; -- Write good lab reports;
5

Course objectives and outlines

Objectives:
Please visit the course web site for detailed course objectives.
http://www.ece.stevens-tech.edu/~hhe/cpe487f09/class_index.htm

Outlines:
VHDL language elements; Behavioral modeling; Dataflow modeling; Structural modeling; Computer-aided synthesis and implementation; Generics and configuration; Packages and libraries; Design of arithmetic logic unit (ALU); Finite state machines (FSM); Test bench design;
6

History of VHDL
VHDL:
Very High Speed Integrated Circuit (VHSIC) Hardware Description Language

Launched in 1980 by Defense Advanced Research Projects Agency (DARPA) July 1983 Intermetrics, IBM and Texas Instruments were awarded a contract to develop VHDL August 1985 Release of final version of the language under government contract, VHDL Version 7.2 December 1987 IEEE Standard 1076-1987 1988 VHDL became an American National Standards Institute (ANSI ) standard September 1993 IEEE VHDL standard revised 7

Digital System Design Flow

Requirements

Functional Design

Behavioral Simulation

Register Transfer Level Design RTL Simulation Validation Logic Simulation Verification Fault Simulation Timing Simulation Circuit Analysis Design Rule Checking

Logic Design

Circuit Design

Design flows operate at multiple levels of abstraction Need a uniform description to translate between levels Increasing costs of design and fabrication necessitate greater reliance on automation via CAD tools $5M - $100M to design new chips Increasing time to market pressures

Physical Design

Description for Manufacture

Source: Sudhakar Yalamanchili, Georgia Institute of Technology, 2006

The Marketplace

Maximum revenue Revenue loss Revenue

ri se

t ke ar M

M ar

ke t

fa ll

Delay Time

Source: V. K. Madisetti and T. W. Egolf, Virtual Prototyping of Embedded Microcontroller Based DSP Systems, IEEE Micro, pp. 921, 1995.

Role of HDL Y chart

BEHAVIORAL algorithms register transfers Boolean expressions transfer functions

STRUCTURAL

processors registers gates transistors cells modules chips boards PHYSICAL

Description and documentation Simulation Synthesis

Source: (1) D. Gajski and R. H. Kuhn (2) Sudhakar Yalamanchili, VHDL- A starters guide

10

Introduction of development of digital IC technology

The following slides are adapted from Digital Integrated Circuits - A Design Perspective, 2003. J. M. Rabaey, A. Chandrakasan, B. Nikolic

11

ENIAC - The first electronic computer (1946)

10 feet tall; 1,000 square feet of floor- space; 30 tons; More than 70,000 resistors; 10,000 capacitors; 6,000 switches; 18,000 vacuum tubes; Requires 150 kilowatts of power;

12

Transistor Age

1947: Bardeen and Brattain create point-contact transistor

1951: Shockley develops junction transistor which can be manufactured in quantity.

13

Early Integration

Jack Kilby, working at Texas Instruments, invented a monolithic integrated circuit in July 1959. He had constructed the flip-flop shown in the patent drawing above.

14

Planar transistors

In mid 1959, Noyce develops the first true IC using planar transistors,

15

Practice Makes Perfect

1961: TI and Fairchild introduced first logic ICs

1963: Densities and yields improve. This circuit has four flip-flops.

16

Continues development

1967: Fairchild markets the first semi-custom chip. Transistors (organized in columns) can be easily rewired to create different circuits. Circuit has ~150 logic gates.

1968: Noyce and Moore leave Fairchild to form Intel. By 1971 Intel had 500 employees; By 2004, 80,000 employees in 55 countries and $34.2B in sales.

17

Continues development

1970: Intel starts selling a 1k bit RAM.

1971: Ted Hoff at Intel designed the first microprocessor. The 4004 had 4-bit busses and a clock rate of 108 KHz. It had 2300 transistors and was built in a 10 um process.
18

Exponential Growth

1972: 8088 introduced. Had 3,500 transistors supporting a byte-wide data path.

1974: Introduction of the 8080. Had 6,000 transistors in a 6 um process. The clock rate was 2 MHz.
19

Today
Many disciplines have contributed to the current state-of-the-art in VLSI Design:

Solid State Physics Materials Science Lithography and fab Device modeling
To come up with chips like:

Circuit design and layout Architecture design Algorithms CAD tools

20

Pentium 4 0.18 um t

0.18-micron process technology Introduction date: November 20, 2000 (1.5, 1.4 GHz) Level Two cache: 256 KB Advanced Transfer Cache System Bus Speed: 400 MHz SSE2 SIMD Extensions Transistors: 42 Million Typical Use: Desktops and entry-level workstations

21

Pentium 4

0.13-micron

process technology (2.53, 2.2, 2 GHz) Introduction date: January 7, 2002 Level Two cache: 512 KB Advanced Transistors: 55 Million

22

Pentium Pro - multichip module (MCM)

23

Supercomputer for Sony's PlayStation 3

IBM chip has nine

processor cores 192 billion floating-point operations per second (192 G) Typical Use: multimedia

24

Moores Law

In 1965, Gordon Moore noted that the number of

transistors on a chip doubled every 18 to 24 months.

He made a prediction that semiconductor

technology will double its effectiveness every 18 months

25

LOG2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975
Source: Electronics, April 19, 1965.

Moores Law

26

Technology Directions: SIA Roadmap

Year
Feature size (nm) 2 Logic trans/cm Cost/trans (mc) #pads/chip Clock (MHz) 2 Chip size (mm ) Wiring levels Power supply (V) High -perf pow (W)

1999 2002 2005 2008 2011

180 6.2M 1.735 1867 1250 340 6-7 1.8 90 130 18M .580 2553 2100 430 7 1.5 130 100 39M .255 3492 3500 520 7-8 1.2 160

2014

70 50 35 84M 180M 390M .110 .049 .022 4776 6532 8935 6000 10000 16900 620 750 900 8-9 9 10 0.9 0.6 0.5 170 175 183
27

Transistor Counts
1 Billion Transistors
Pentium III Pentium II Pentium Pro Pentium

K 1,000,000 100,000 10,000 1,000 100 10 1 1975

8086 i386 80286 i486

Source: Intel

1980

1985 1990

1995

2000
Projected

2005 2010
28

Courtesy, Intel

Transistors shipped per year

Source: Dataquest/Intel, 8/02

29

Moores law in Microprocessors

1000 100 Transistors (MT) 10 1 0.1 0.01 0.001 1970 8085 8086 8080 8008 4004 1980 1990 Year 2000 2010 386 286 486

2X growth in 1.96 years!

P6 Pentium proc

Transistors on Lead Microprocessors double every 2 years

Courtesy, Intel
30

Frequency
10000 1000 100 486 10 1 0.1 1970 8085 8086 286 386

Frequency (Mhz)

Doubles every 2 years

P6 Pentium proc

8080 8008 4004 1980 1990 Year 2000 2010

Lead Microprocessors frequency doubles every 2 years

31

Courtesy, Intel

Power will be a major problem

100000 10000 Power (Watts) 1000 100

18KW 5KW 1.5KW 500W Pentium proc

286 486 8086 386 10 8085 8080 8008 1 4004 0.1 1971 1974 1978 1985 1992 Year 2000 2004 2008

Power delivery and dissipation will be prohibitive

32

Courtesy, Intel

Productivity Trends
10,000 10,000,000 1,000 1,000,000 100 100,000 10 10,000 1 1,000 0.1 100
xx x xx x x x

Complexity Logic Transistor per Chip (M)

100,000 100,000,000

1,000 1,000,000 58%/Yr. compounded Complexity growth rate 100 100,000 10 10,000 21%/Yr. compound Productivity growth rate 1 1,000 0.1 100 0.01 10

0.01 10 0.001 1

1981

1983

1985

1987

1991

1993

1997

1999

2001

2003

1989

1995

2005

2007

Source: Sematech

Complexity outpaces design productivity

Courtesy, ITRS Roadmap

2009

Productivity (K) Trans./Staff - Mo. 33

Logic Tr./Chip Tr./Staff Month.

10,000 10,000,000

Reference
The lectures notes and pictures are based on the following sources:
[1] J. Bhasker, A VHDL Primer,3rd edition, J. Bhasker, Prentice Hall, ISBN 0-13-096575-8, 1999 [2] S. Tewksbury, VHDL class notes http://stewks.ece.stevens-tech.edu/CpE487-S05/ [2] J. V. Spiegel, VHDL tutorial. http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html [3] J. A. Starzyk, VHDL class lecture notes http://www.ent.ohiou.edu/~starzyk/network/Class/ee515/index.html [4] S. Yalamanchili, Introductory VHDL: From Simulation to Synthesis, Prentice Hall, ISBN 0-13-080982-9, 2001. [5] S. Yalamanchili, VHDL: A Starter's Guide,, Prentice Hall, ISBN: 0-13-145735-7, 2005. [6] V. A. Pedroni, Circuit Design with VHDL,, MIT Press, ISBN: 0-262-16224-5, 2004. [7] K. C. Chang, Digital Design and Modeling with VHDL and Synthesis, , IEEE Computer Society Press, ISBN: 0-8186-7716-3, 1997 [8] J. M. Rabaey, A. Chandrakasan, B. Nikolic, Digital integrated circuits- a design perspective, 2nd edition, prentice hall.
34