Problemas Resueltos de VHDL
Problemas Resueltos de VHDL
Problemas Resueltos de VHDL
Ejemplo#1: MEMORIA RAM GENERICA library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity SRAM is generic( w: d: a: port( Clock: Enable: Read: Write: Read_Addr: Write_Addr: Data_in: Data_out: ); end SRAM;
integer:=4; -- ancho de palabra integer:=4; -- n de palabras integer:=2);-- ancho direccin in std_logic; in std_logic; in std_logic; in std_logic; in std_logic_vector(a-1 downto 0); in std_logic_vector(a-1 downto 0); in std_logic_vector(w-1 downto 0); out std_logic_vector(w-1 downto 0)
architecture behav of SRAM is type ram_type is array (0 to d-1) of std_logic_vector(w-1 downto 0); signal tmp_ram: ram_type; begin -- Lectura process(Clock, Read) begin if (Clock'event and Clock='1') then if Enable='1' then if Read='1' then Data_out <= tmp_ram(std2n(Read_Addr)); else Data_out <= (Data_out'range => 'Z'); -- Todos los bits de Data_out se ponen a 'Z' end if; end if; end if; end process; -- Escritura process(Clock, Write) begin if (Clock'event and Clock='1') then if Enable='1' then if Write='1' then tmp_ram(std2n(Write_Addr)) <= Data_in; end if; end if; end if; end process; end behav;
Ejemplo#3: REGISTRO DE 8 BITS entity biestable is port (clk, reset, C: in bit; D: out bit); end biestable; architecture arch of biestable is begin process(clk, reset) begin if reset=1 then D<=0; elsif (clkevent and clk=1) then D<=C; end if; end process; end arch; entity registro_8 is port (clk, reset: in bit; A: in bit_vector(7 downto 0); B: out bit_vector(7 downto 0)); end registro_8; architecture estructural of registro_8 is component biestable port(clk, reset, c: in bit; d: out bit); end component biestable; signal F: bit_vector(7 downto 0); begin gen: for i in 0 to 7 generate u: biestable port map(clk, reset, A(i),F(i)); end generate gen; B <= F; end estructural;