Introduction

An introduction to VHDL: What is VHDL Basic design methodology Synthesis design flow FPGA architecture Simulation and Synthesis Signal Values

An Introduction to VHDL
What is VHDL?
VHDL is a hardware description language that can be used to model a digital system VHDL is often quoted to be an acronym for Very Hard Description Language or for VHSIC Hardware Description Language VHDL is an IEEE standard as well as an ANSI standard for describing digital systems The standard revised every five years: IEEE Std 1076-1987 IEEE Std 1076-1993 IEEE Std 1164-1993
Note: The material on slides 2-21 can be found in Chapter 4 of the text book

Ali Elkateeb, 2004

Computer Hardware Organization/Design

An Introduction to VHDL
Major Capabilities
It contains elements that can be used to describe the behavior, dataflow, and structure of the digital systems It provides support for modeling the system hierarchically and also supports top-down and bottom-up design methodologies Models written by this language can be verified using a VHDL simulator. The language is not technology-specific It supports both synchronous and asynchronous timing models Test benches can be written using the same language to test other VHDL models
Ali Elkateeb, 2004 Computer Hardware Organization/Design 3

Domains and Levels of Modeling

Structural Functional
high level of abstraction low level of abstraction

Geometric
The source of this slide is The Students Guid to VHDL by P. Ashenden
Ali Elkateeb, 2004

Y-chart due to Gajski & Kahn

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Computer Hardware Organization/Design

Domains and Levels of Modeling

Structural Functional
Algorithm (behavioral) Register-Transfer Language Boolean Equation Differential Equation

Geometric
The source of this slide is The Students Guide to VHDL by P. Ashenden
Ali Elkateeb, 2004

Y-chart due to Gajski & Kahn

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Computer Hardware Organization/Design

Domains and Levels of Modeling

Structural
Processor-Memory Switch Register-Transfer Gate Transistor

Functional

Geometric
The source of this slide is The Students Guide to VHDL by P. Ashenden
Ali Elkateeb, 2004

Y-chart due to Gajski & Kahn

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Computer Hardware Organization/Design

Domains and Levels of Modeling

Structural Functional

Polygons Sticks Standard Cells Floor Plan

Geometric
The source of this slide is The Students Guide to VHDL by P. Ashenden
Ali Elkateeb, 2004

Y-chart due to Gajski & Kahn

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Computer Hardware Organization/Design

Hardware Abstraction
VHDL is used to describe a model for a digital hardware device Each model specifies the external view of the device and one or more internal views Internal view: specifies the functionality or structure of the device External view: specifies the interface of the device through which it communicates with the other models in its environment

Ali Elkateeb, 2004

Computer Hardware Organization/Design

Hardware Abstraction

External view

Digital System

Model

Device

Internal view

Device model

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Computer Hardware Organization/Design

Hardware Abstraction

Entity 1 Device Entity 2 Entity N Actual Hardware

Device model 1

Device model 2

Device model N

VHDL view

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VHDL - Basic Terminology

VHDL is a hardware description language that can be used to model a digital system Entity: A hardware abstraction of a digital system Component: An entity used by another entity Example: when an entity X used in another entity Y, then X become a component for the entity Y. Design units: VHDL provides five different types of primary constructs to describe an entity 1. Entity declaration 2. Architecture body 3. Configuration declaration 4. Package declaration 5. Package body
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VHDL - Basic Terminology

Entity declaration: describes the external view of the entity. Example: input and output signal names Architecture body: contains the internal description of the entity Example: a set of interconnected components that represents the structure of the entity or a set of concurrent or sequential statements that represents the behavior of the entity Each architecture body can be represented by - one style or - mixed style of representation
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VHDL - Basic Terminology

Entity Hardware abstraction of a digital system Model

Entity declaration

Architecture bodies

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VHDL - Basic Terminology

Entity declaration
entity name port names port mode (direction)

entity HALF_ADDER is port ( A, B: in bit; SUM, CARRY:OUT bit); end HALF_ADDER;

reserved words port type

punctuation

SUM

Half-adder circuit
B CARRY

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VHDL - Basic Terminology

Architecture Body - Represents the internal details of an entity - An architecture body can use any of the following modeling styles: 1. Set of interconnected components (structural model) 2. Set of concurrent assignment statements (dataflow model) 3. Set of sequential assignment statements (behavior model) 4. Any combination of the above (mixed model)
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VHDL - Basic Terminology

Structural Model
A SUM

CARRY

architecture HA_STRUCTURE of HALF_ADDER is component XOR2 port (X, Y: in BIT; Z: out BIT); end component; component AND2 port (L, M: in BIT; N: out BIT); end component; begin X1: XOR2 port map (A, B, SUM); A1: AND2 port map (A, B, CARRY); end HA_STRUCTURE;
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VHDL - Basic Terminology

Dataflow Model : expressed by using concurrent signal assignment statements The structure of the entity is not explicitly specified in this modeling It can be implicitly deduced
Architecture HA_concurrent of Half_adder is Begin sum <= A xor B after 8 ns; carry <= A and B after 4 ns; end HA_concurrent; 1. 2. The symbol<= implies an assignment of a value to a signal A concurrent signal assignment statement is executed only when any signal used in the expression on the right-hand side has an event on it (the value for the signal changes)
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Ali Elkateeb, 2004

VHDL - Basic Terminology

Behavioral Model: Specifies the behavior of an entity as a set of statements that are executed sequentially
Sequential statements, within a process statement, do not explicitly specify the structure of the entity but merely its functionality

Signal assigned a value always After a certain Delay This example is not good!!

Architecture dec_sequential of Decoder2x4 is Begin process (A, B, Enable) -- sensitivity list variable Abar, Bbar:Bit; begin Abar := not A; -- variable is always assigned a value Bbar := not B; -- instantaneously (assignment use := compound symbol) If Enable = 1 then Z(3) <= not (A and B); Z(0) <= not (Abar and Bbar); Z(2) <= not (A and Bbar); Z(1) <= not (Abar and B); else Z <= 1111; end if; end process; End dec_sequential; Computer Hardware Organization/Design 18

Ali Elkateeb, 2004

VHDL - Basic Terminology

Behavioral Model: Specifies the behavior of an entity as a set of statements that are executed sequentially
Sequential statements, within a process statement, do not explicitly specify the structure of the entity but merely its functionality
-- 4 to 1 multiplexer design with case construct -SEL: in STD_LOGIC_VECTOR(1 downto 0); -A, B, C, D:in STD_LOGIC; -MUX_OUT: out STD_LOGIC; process (SEL, A, B, C, D) begin case SEL is when "00" => MUX_OUT <= A; when "01" => MUX_OUT <= B; when "10" => MUX_OUT <= C; when "11" => MUX_OUT <= D; when others => MUX_OUT <= 'X'; end case; end process;

Signal assigned a value always After a certain Delay This example is good!

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VHDL - Basic Terminology

Mixed Model Will be discussed after the behavioral model section

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Synthesis Design Flow For FPGAs

Requirements
specification of the design

Functional Design Register Transfer Level Design

- Functional simulation Produced here - Gate level implementation

Preliminary high-level functional design

Initial functional design is refined to produce a more detailed design description

Synthesis Place and Route Timing Extraction

Realistic timing simulation

The material on slides 22 and up can be found in Chapter 1 and 2 of the text book Ali Elkateeb, 2004 Computer Hardware Organization/Design 21

FPGA Architecture

CLB CLB

CLB CLB

CLB CLB

Switch Matrix

Switch Matrix

CLB: Configurable Logic Block PSM: Programmable Switch Matrices

CLB CLB

CLB CLB

CLB CLB

A Generic FPGA Architecture Ali Elkateeb, 2004 Computer Hardware Organization/Design 22

FPGA Architecture
Slew Rate Control Passive Pull-Up, Pull-Down Vcc

CLB

CLB
D Q Output Buffer Pad

Switch Matrix

Input Buffer Q D Delay

CLB

CLB

Programmable Interconnect
C1 C2 C3 C4 H1 DIN S/R EC
S/R Control

I/O Blocks (IOBs)

G4 G3 G2 G1

G Func. Gen. H Func. Gen. F Func. Gen.

DIN F' G' H'

SD D Q

1 G' H' S/R Control

EC RD

F4 F3 F2 F1

DIN F' G' H'

SD D Q

1 H' F'

EC RD

Configurable Logic Blocks (CLBs)

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XC4000E/X Configurable Logic Blocks

2 Four-input function generators (Look Up Tables) - 16x1 RAM or Logic function 2 Registers - Each can be configured as Flip Flop or Latch - Independent clock polarity - Synchronous and asynchronous Set/Reset

C1 C2 C3 C4 H1 DIN S/R EC
S/R Control

G4 G3 G2 G1

G Func. Gen. H Func .Gen. F Func. Gen.

DIN F' G' H'

SD D Q

YQ

1 G' H' S/R Control

EC RD

F4 F3 F2 F1

DIN F' G' H'

SD D Q

XQ

1 H' F'

EC RD

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Look Up Tables

Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Example:

Combinatorial Logic

A B C D 0 0 0 0 0 0 1 1 1 1
G Func. Gen.

Z 0 0 0 1 1 1 0 0 0 1

A B C D Z

Capacity is limited by number of inputs, not complexity Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM WE
G4 G3 G2 G1
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0 0 0 0 1 1 1 1 1 1

0 0 1 1 0 0 0 0 1 1

0 1 0 1 0 1 0 1 0 1

. . .

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XC4000X I/O Block Diagram

Shaded areas are not included in XC4000E family.

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Chip Structure
Programmable Interconnect Points, PIPs (White)

Routed Wires (Blue) Switch Matrix Direct Interconnect (Green)

CLB (Red)

Long Lines (Purple)

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Simulation
Why Simulation: To study the properties of the circuit Discrete Event Simulation: A programming-based methodology for accurately modeling the generation of events in physical systems Timestamp: The time at which an event is to occur Timestep: Simulator clock Simulation state: Frozen the system at a timestep and took a snapshot of the values of all of the signals in the system

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Simulation

SUM

CARRY

A
event

S C
0ns Ali Elkateeb, 2004 5ns 10ns 15ns 20ns 25ns

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Synthesis Synthesis A Process of constructing a physical system from a model VHDL Model
A SU M

CARRY

A Process that operates on three types of information 1. The model of the circuit (e.g. VHDL model) 2. Set of constraints on the resulting circuit, such as speed and area 3. Set of components that are to be used to construct the circuit Synthesis compilers must infer a single hardware implementation from a VHDL description
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Signal Values Signal values are normally associated with the output of gates 0 or 1 values to voltage levels at the output of a device For 5V TTL logic circuit
0 : from 0 to 0.4V 1 : from 2.4 to 5V

For 3.3V logic circuit

0: from 0 to 0.8V 1: from 2 to 3.3V

High-impedance state (Z) Unknown values (X) Initial value of a signal is unknown (U)

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Signal Values Dont care value (-) Signal strength Weak 0 (L) [signal go to 0 slowly] Weak 1 (H) Weak unknown (W) Note: Synthesis of Weak unknown (W) and initialized values (U) do not have meaning for a signal (no physical implementations for W and U) This nine-value system used in IEEE 1164 standard

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