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Generic Component VHDL

The document describes using generics in VHDL to create a reusable PISO (parallel in serial out) component that can be configured for different data widths. A PISO component with a generic width parameter is defined, then instantiated twice in a testbench - once for 8-bits and once for 4-bits - by passing different values to the generic map.

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280 views5 pages

Generic Component VHDL

The document describes using generics in VHDL to create a reusable PISO (parallel in serial out) component that can be configured for different data widths. A PISO component with a generic width parameter is defined, then instantiated twice in a testbench - once for 8-bits and once for 4-bits - by passing different values to the generic map.

Uploaded by

mussadaqhussain8210
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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--The top module has two instantiations- a 8 bit PISO(parallel in serial out) register and a 4 bit PISO.

--Without the use of generics these two components need a seperate .vhd file. --But I have used "generic" keyword to solve this problem. entity piso is generic ( width : integer := 7 ); --default value is 7 port ( clk : in std_logic; load : in std_logic; in1 : in std_logic_vector(width downto 0); out1 : out std_logic ); end piso; architecture Behavioral of piso is signal temp: std_logic_vector (width downto 0) := (others => '0'); -initialize to zero begin process(clk) begin If (load = '0') then -- load the register temp <= in1; elsif (clk'event and clk = '1') then --shift the register elements and output a single bit. out1 <= temp(width); temp(width downto 1) <= temp(width-1 downto 0); end if; end process; end Behavioral; --Now the instantiation of this component in top module is shown below: entity test is ... ... end test; architecture behavior of test is component piso generic ( width : integer := 7 ); port ( clk : in std_logic; load : in std_logic; in1 : in std_logic_vector(width downto 0); out1 : out std_logic ); end component; --signal declarations signal in1 : std_logic_vector(7 downto 0):="10000110"; signal in2 : std_logic_vector(3 downto 0):="1001"; signal load1,load2 : std_logic :='0'; begin --Note down the next two lines. --This is how you pass generic parameters to the instantiated components. piso1 : piso generic map (width => 7) port map(clk,load1,in1,o1); piso2 : piso generic map (width => 3) port map(clk,load2,in2,o2); --change the input signals as you want. end behavior;

Example
component COUNTER port (CLK, RESET: in Std_logic; UpDown: in Std_logic := '0'; -- default value Q: out Std_logic_vector(3 downto 0)); end component; ... -- Positional association... G1: COUNTER port map (Clk32MHz, RST, open, Count); -- Named association (order doesn't matter)... G2: COUNTER port map ( RESET => RST, CLK => Clk32MHz, Q(3) => Q2MHz, Q(2) => open, -- unconnected Q(1 downto 0) => Cnt2, UpDown => open);

Component Declaration Declaration ---- used in ----> Syntax


component component_name generic (generic_list); port (port_list); end component;

Architecture Package

See LRM sections 4.5, 1.1.1.1 and 1.1.1.2


Rules and Examples The port list must define the name, the mode (i.e.direction) and the type of each port on the component.
component HALFADD port(A,B : in bit; SUM, CARRY : out bit); end component;

A component declaration does not define the entity-architecture pair to be bound to each instance, or even the ports on the entity. These are defined by the configuration In an architecture, components must be declared before the begin statement:
architecture STRUCTURAL of FULLADD is -- (local signal declarations here) component ORGATE port (A,B : in bit; Z : out bit); end component; -- (other component declarations)

begin -- the architecture contents end STRUCTURAL;

A component declared in a package is visible in any architecture which uses the package, and need not be declared again. For a component with generics, these must be declared before the ports. They do not have a mode, as by definition they can only pass information into the entity:
component PARITY generic (N : integer); port (A : in std_ulogic_vector (N-1 downto 0); ODD : out std_ulogic); end component;

Synthesis Issues

Component declarations are supported for synthesis, providing the port types are acceptable to the logic synthesis tool. Usually, only generics of type integer are supported. Whether a synthesis tool will "flatten through" a component, treat is as a "black box", or recognise it as a primitive is usually under the user's control.
Whats New in '93

In VHDL-93., an entity-architecture pair can be instantiated directly. In this case a component declaration is not required. This is more compact, but does not allow the flexibility of configuration. In VHDL-93, the component name may be followed by the keyword is, for clarity and consistancy. also the keywords end component may be followed by a repetition of the component name:
component component_name is port (port list); end component component_name;

Component Instantiation Concurrent Statement ---- used in ----> Architecture Syntax


instance_label: component_name generic map (generic_association_list) port map (port_association_list);

See LRM section 9.6


Rules and Examples The instance label is compulsory. The component name must match the relevant component declaration.
architecture STRUCT of INC is signal X,Y,S,C : bit; component HALFADD port(A,B : in bit; SUM, CARRY : out bit); end component; begin U1: HALFADD port map (X,Y,S,C); -- other statements end STRUCT;

The association list defines which local signals connect to which component ports. The association list above ispositional, i.e. the signals are connected up in the order in which the ports were declared. the alternative is named association, where ports are explicitly referenced and order is not important:
ADDER1: HALFADD port map ( B => Y, A => X, SUM => S, CARRY => C);

Ports may be left unconnected using the keyword open:


ADDER2: HALFADD port map (B=>Y,A=>X,SUM=>S,CARRY=>open);

An instance of a component with generics, has a generic map declared before the port map:
U1 : PARITY generic map ( port map ( N => 8) A => DATA_BYTE, ODD => PARITY_BYTE);

Synthesis Issues

Component instantiation is supported for synthesis, although generic map is usually ignored. Whether a logic synthesis tool will "flatten through" a component, treat it as a "black box", or recognise it as a primitive is usually under the user's control.
Whats New in '93

In VHDL-93, an entity-architecture pair may be directly instantiated, i.e. a component need not be declared. This is more compact, but does not allow the flexibility of configuration
DIRECT: entity HA_ENTITY(HA_ARCH) port map (A,B,S,C);

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