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Types of Concurrent Assignment Statements: - Simple Signal Assignments

The document describes different types of concurrent assignment statements in VHDL including simple signal assignments, selected signal assignments, and conditional signal assignments. It provides examples of using each type to assign values to signals and describes their syntax and evaluation order. Additional applications discussed include binary encoders, decoders, gray codes, and 7-segment display control.
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0% found this document useful (0 votes)
54 views8 pages

Types of Concurrent Assignment Statements: - Simple Signal Assignments

The document describes different types of concurrent assignment statements in VHDL including simple signal assignments, selected signal assignments, and conditional signal assignments. It provides examples of using each type to assign values to signals and describes their syntax and evaluation order. Additional applications discussed include binary encoders, decoders, gray codes, and 7-segment display control.
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Types of Concurrent Assignment Statements

Simple Signal Assignments Selected Signal Assignments Conditional Signal Assignment

A A F B 0 0 1 1
ENTITY XOR_Gate IS PORT ( A, B : IN STD_LOGIC ; F : OUT STD_LOGIC ) ; END XOR_Gate ;

B 0 1 0 1

F=AB 0 1 1 0

ARCHITECTURE Simple_Example OF XOR_Gate IS BEGIN

- - Simple Concurrent Assignment

END Simple_Example;

A A F B 0 0 1 1
ENTITY XOR_Gate IS PORT ( A, B : IN STD_LOGIC ; F : OUT STD_LOGIC ) ; END XOR_Gate ;

B 0 1 0 1

F=AB 0 1 1 0

Simple Signal Assignments


ENTITY my_entity IS

PORT (output1 : OUT STD_LOGIC);


END my_entity; ARCHITECTURE my_arch OF my_entity IS
Most Significant Bit Index Least Significant Bit Index

SIGNAL one_signal : STD_LOGIC;

SIGNAL A_bus : STD_LOGIC_VECTOR( 7 DOWNTO 0 );


-- Most Significant Bit: A_bus(____), Least Significant Bit: A_bus(___)

ARCHITECTURE Simpler_Example OF XOR_Gate IS BEGIN


- - Using Available Boolean Function

SIGNAL D_bus : STD_LOGIC_VECTOR( 0 TO 3 ); -- MSBit: D_bus(___), LSBit: D_bus(___) SIGNAL Two_Bit_bus : STD_LOGIC_VECTOR( 3 DOWNTO 1 ); -- MSBit: Two_Bit_bus(___), LSBit: Two_Bit_bus(___)

END Simpler_Example;

ARCHITECTURE my_arch OF my_entity IS

ENTITY my_entity IS

SIGNAL one_signal : STD_LOGIC; SIGNAL A_bus : STD_LOGIC_VECTOR( 7 DOWNTO 0 ); -- Most Significant Bit: A_bus(7), Least Significant Bit: A_bus(0) SIGNAL D_bus : STD_LOGIC_VECTOR( 0 TO 3 ); -- MSBit: D_bus(0), LSBit: D_bus(3) SIGNAL Thr3_Bit_bus : STD_LOGIC_VECTOR( 3 DOWNTO 1 );

PORT (output1 : OUT STD_LOGIC);


END my_entity; ARCHITECTURE my_arch OF my_entity IS

SIGNAL one_signal BEGIN

: STD_LOGIC;

BEGIN -- Examples of Simple Concurrent Signal Assignments:

output1 <= 0 ; one_signal <= output1 ;


-- ERROR: VHDL does not permit Entity OUTputs to be used on the Right -- Side of signal assignments as inputs for determining other signals

one_signal <= 0 ;

--Use single quotes for single-bit explicit assignments

D_bus <= 1010 ; -- Use double quotes for multi-bit assignments


-- D_bus(0) = __, D_bus(1) = ___, D_bus(2) = ___, D_bus(3) = ___

A_bus <= 0000 & D_bus ;


-- A_bus <= 0 0 0 0 1 0 1 0

-- & used for concatenation A_bus(1) = ___, A_bus(3)=___

Thr3_Bit_bus <= A_bus( 5 DOWNTO 3 );


-- Thr3_Bit_bus <= 0 0 1
END arch_name;

-- multiple-bit indexing Thr3_Bit_bus(3) = ___, Thr3_Bit_bus(1)=___

-- OK: VHDL does permit intermediate SIGNALs declared inside the -- ARCHITECTURE to be used on the Either Side of signal assignments

Selected Signal Assignment


Assign one of several possible values to a signal Which value gets assigned depends on the present value of a single selection criterion
Like a case or switch statement in other languages

Selected Signal Assignment


Evaluated by VHDL: Whenever there is a value change in any signals in the select_criterion or in any of the criterionValue(s) Cautions: All choices are evaluated and checked each time Need a WHEN clause _____________________ __________________________ of select_criterion if you omit the OTHERS criterion value
(What if: select_criterion : STD_LOGIC?? Did you specify what to do if select_criterion = Z ??, or - ??, or???)

Syntax:

_________ select_criterion __________ signal <= expression1 WHEN criterionValue1, expression2 WHEN criterionValue2, expression3 WHEN criterionValue3, expression4 WHEN __________;
Defines what to do if NONE of the criterionValues are present.

A F B
ENTITY XOR_Gate IS PORT ( A, B : IN STD_LOGIC ; F : OUT STD_LOGIC ) ; END XOR_Gate ;

A 0 0 1 1

B 0 1 0 1

F=AB 0 1 1 0

A F B
ENTITY XOR_Gate IS PORT ( A, B : IN STD_LOGIC ; F : OUT STD_LOGIC ) ; END XOR_Gate ;

A 0 0 1 1

B 0 1 0 1

F=AB 0 1 1 0

ARCHITECTURE Selected_Example OF XOR_Gate IS BEGIN

ARCHITECTURE Selected_Example OF XOR_Gate IS


SIGNAL A_B : STD_LOGIC_VECTOR (1 DOWNTO 0); BEGIN A_B <= (A & B) ; - - Combine into a 2-bit criterion

WITH (A_B) SELECT

END Selected_Example;

END Selected_Example;

A F B
ENTITY XOR_Gate IS PORT ( A, B : IN STD_LOGIC ; F : OUT STD_LOGIC ) ; END XOR_Gate ;

A 0 0 1 1

B 0 1 0 1

F=AB 0 1 1 0

Example: 4:1 MUX


Sel(1) 0 0
Sel

Sel(0) 0 1 0 1

F D0 D1 D2 D3

ARCHITECTURE Selected_Example OF XOR_Gate IS


SIGNAL A_B : STD_LOGIC_VECTOR (1 DOWNTO 0); BEGIN A_B <= (A & B) ; - - Combine into a 2-bit criterion

1 1

ENTITY MUX_4_to_1 IS

WITH (A_B) SELECT

END Selected_Example;

END MUX_4_to_1;

Sel(1) 0 0 1 Sel 1

Sel(0) 0 1 0 1

F D0 D1 D2 D3

Conditional Signal Assignment


Assign one of several different values to a signal depending on which one of several possible conditions are currently true.
Syntax:

ARCHITECTURE Selected_Mux OF MUX_4_TO_1 IS BEGIN

signal <= expression1 WHEN condition1 ELSE expression2 WHEN condition2 ELSE expression3 WHEN condition3 ELSE
END Selected_Mux;

expression4 ;

Conditional Signal Assignment


NOTES: 1. Each WHEN condition can use
different signals, different values, can be very unique. Must be a Boolean logic expression
Must evaluate to either ______ or ________

Conditional Signal Assignment


NOTES: 2. The conditions are evaluated in the order that they appear in the code.
The __________ condition is acted upon
The rest are ______________

Sequence Matters (!) for the conditions


The Signal Assignment is still concurrent with other signal assignments.

B 0 1 0 1

F=AB 0 1 1 0

Conditional Signal Assignment


NOTES: 3. The final expression (after the final ELSE) handles all the other cases that dont match the conditions specified: signal <= expression1 WHEN condition1 ELSE expression2 WHEN condition2 ELSE expression3 WHEN condition3 ELSE
expression4 ;

A F B
ENTITY XOR_Gate IS PORT ( A, B : IN STD_LOGIC ; F : OUT STD_LOGIC ) ; END XOR_Gate ;

0 0 1 1

ARCHITECTURE Conditional_Example OF XOR_Gate IS BEGIN F <=

END Conditional_Example;

A A F B
ENTITY XOR_Gate IS PORT ( A, B : IN STD_LOGIC ; F : OUT STD_LOGIC ) ; END XOR_Gate ;

B 0 1 0 1

F=AB 0 1 1 0

0 0 1 1

Example: 4:1 MUX With Strobe Enable (Active High)


EN 1
EN

Sel(1) 0 0 1 1 -

Sel(0) 0 1 0 1 -

F D0 D1 D2 D3 0

1
Sel

1 1 0

ARCHITECTURE Conditional_Example OF XOR_Gate IS BEGIN F <=

ENTITY MUX_4_to_1 IS

PORT ( D0, D1, D2, D3, EN: IN STD_LOGIC ; Sel: IN STD_LOGIC_VECTOR( 1 downto 0) ; F : OUT STD_LOGIC ) ; END Conditional_Example; END MUX_4_to_1

EN ENTITY MUX_4_to_1 IS PORT ( D0, D1, D2, D3, EN: IN STD_LOGIC ; Sel: IN STD_LOGIC_VECTOR( 1 downto 0) ; F : OUT STD_LOGIC ) ; END MUX_4_to_1 1 1 1 1 0

Sel(1) 0 0 1 1 -

Sel(0) 0 1 0 1 -

F D0 D1 D2 D3 0

Other Applications of Conditional & Selective Assignments


Binary Encoders / Decoders n Channels 2n binary codes n Channels 2n binary codes Code Converters

ARCHITECTURE Conditional_Mux OF MUX_4_TO_1 IS BEGIN


- - Conditional Concurrent Assignment

F <=
- - Above takes priority Evaluated 1st

Change from one code type to another


Binary Binary-Coded-Decimal (BCD) Gray Codes Parity / Error Detecting / Error Correcting Codes (CDs) Data Modulation Encoding (data storage / communication) Display Control Codes (7-segment display)

WHEN (Sel=00) ELSE WHEN (Sel=01) ELSE WHEN (Sel=10) ELSE WHEN (Sel=11) ELSE 0 ; END Conditional_Mux;

Binary Decoders
Converts an n bit Binary Code (applied to n inputs) to activate 1 of 2n different output lines. (n-to-2n)
All other outputs inactive (0 if active high) May have a strobe enable input
2 to 4 Decoder

Binary Decoders in VHDL


Which VHDL statements for the needed operations? Determining F outputs for the given B inputs?
Simple Signal Assignments??

Selected Signal Assignments??

En B1 B0 1 1 1 1 0 0 1 1 0 1 0 1

F3 0 0 0 1

F2 0 0 1 0

F1 0 1 0 0

F0 1 0 0 0
En

Conditional Assignments??

Binary Encoders
Outputs an n bit Binary Code with the Input Channel Number that is active (of 2n different inputs. (2n-to-n Encoder)
All other inputs inactive (0 if active high)
B3 B2 B1 B0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 F1 0 F0 0

Priority Encoders
Outputs the n bit Binary Code with the Highest Priority Input Channel Number that is active
____________________ can be active ____________ Only the _____________ input gets encoded output Usually has a strobe output to indicate if _____________

B0 B1 B2 B3

0 4to-2 Binary 2 Encoder 3 1 F1 F0

In3 In2 In1 In0 Y1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 1 1 0 0 0

Y0 Str 1 0 1 0 0 1 1 1 1

In0 In1 In2 In3

0 1 Priority 2 Encoder 3 Strobe Y1 Y0 Str

Gray Codes
Main Characteristic: Next code in sequence changes from previous code _______________________ position
Just like minterms/Maxterms for adjacent cells in K-Map

Gray Codes
Creating a Reflective Gray Code:
1. Start with a 1 or 2 bit RGC 2. Make a mirror image below it 3. Add leading 0s to upper half; Add leading 1s to lower half 4. Repeat as needed
3-bit Reflective Gray Code:

00 01 11 10

Unit Distance Code


2-bit Reflective Gray Code:

00 01 11 10

Gray Code Encoders


2-bit Binary-to-RGC Encoder
B1 B0 G1 G0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0
B0 B1 Binary(0) = B0 Binary(1) = B1 0 1
Binary

Gray Code Encoders


Binary Binary Gray Gray

(1)

(0)

(1)

(0)

2-bit Binary-to-RGC Encoder


ENTITY Gray_Encoder_2bit IS PORT ( Binary : IN STD_LOGIC_VECTOR(1 downto 0); Gray : OUT STD_LOGIC_VECTOR(1 downto 0); END Gray_Encoder_2bit ;

0 0 1

0 1 0 1

0 0 1 1

0 1 1 0

Gray Code Encoder 0 1


RGC

G1 G0 Gray(0) = G0 Gray(1) = G1

ARCHITECTURE Select_Gray_Enc OF Gray_Encoder_2bit IS BEGIN

ENTITY Gray_Encoder_2bit IS PORT ( ); END Gray_Encoder_2bit ;


END Select Gray Enc;

Alternate VHDL Mixed CSA Types


Binary Binary Gray Gray

7-Segment Display Control


COMMON-CATHODE Display 1 = Vcc

(1)

(0)

(1)

(0)

ENTITY Gray_Encoder_2bit IS PORT ( Binary : IN STD_LOGIC_VECTOR(1 downto 0); Gray : OUT STD_LOGIC_VECTOR(1 downto 0); END Gray_Encoder_2bit ; 1

0 0 1 1

0 1 0 1

0 0 1 1

0 1 1 0

(Works like you expect)

(1 = LED ON)
COMMON-ANODE Display

ARCHITECTURE Fancy_Gray_Enc OF Gray_Encoder_2bit IS BEGIN Gray(1) <= Binary(1) ; - - Simple Conc. Assign.
- - Conditional Concurrent Assignment

Gray(0) <= Binary(0) WHEN (Binary(1)=0) ELSE NOT( Binary(0) ) ; END Fancy_Gray_Enc;

0 = Gnd

Nexys Board

(___ = LED ON!)

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