Top-Down, Constraint-Driven Design Methodology Based Generation of n-bit Interpolative Current Source D/A Converters

Henry Chang Edward Liu Robert Neff Eric Felt Edoardo Charbon Alberto Sangiovanni-Vincentelli Enrico Malavasi Paul R. Gray

Electronics Research Laboratory Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720, U.S.A.

Abstract
To accelerate the design cycle for analog circuits and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology [1]. In this paper we present a design which demonstrates the two principal advantagesthat this methodology provides a high probability for rst silicon which meets all specications and fast design times. We examine the design of three different 10-bit digital-to-analog (D/A) converters beginning from their performance and functional specications and ending with the testing of the fabricated parts. Critical technology mismatch information gathered from the testing phase is provided.

1 Introduction
As the level of system integration increases, one apparent bottleneck is the design of the analog circuit components. Though these components are often small in area, their design times can be high. To address this problem we have proposed a top-down, constraintdriven design methodology [1], and with it, have provided a variety of design tools such as behavioral level simulators, optimization tools, and physical layout tools. Higher-level tools such as module generators [2] have also been written. To show the effectiveness of this methodology, we have undertaken design examples beginning with industrial-strength specications, and not ending until the designs have been fabricated and tested. This paper presents a complete design ow of an interpolative switched current source D/A converter. As a by-product, a new module generator for this class of 2-stage, n-bit D/A converters has also been developed. This paper is divided into three parts. First, the application of the design style to the synthesis phase is described beginning with the architecture and the performance specications and ending with the layout generation. Compared to some previous works which had also adopted this top-down design style, this design adheres much more rigorously to the methodology. In particular, behavioral level simulators with their ability to dramatically decrease simulation times over circuit simulators were made essential. Using behavioral level simulations at the high-level in conjunction with circuit simulations at the low-level, the integral nonlinearity (INL) and differential nonlinearity (DNL) statistics for the entire D/A converter can be calculated on the order of minutes [3]. Costly full chip circuit simulation is not necessary. By decreasing simulation times, more system-level simulations can be completed, and thus, errors can be caught earlier in the design cycle; and trade-offs at the system level can be better examined. Also more rigorously followed, is the designs adherence to hierarchy to better manage system complexity. Presented in the second part of this paper will be data on the three 10-bit D/A converters that were fabricated. The D/As have varied

architectures and were fabricated on two different 2 :0 m CMOS processes. Two were integrated on the same chip. Each D/A has no more than 2.0 lsb of INL error, 0.5 lsb of DNL error, and can settle for a full scale change at the output to 1 lsb in 20ns. Finally, in the last section, the determination of critical component mismatches and process variations will be presented. Using the measured INL data and the modeling information retained from the behavioral level simulations, the current source mismatches were extracted. Then using this data, the underlying process variations on W , L, and VTH were estimated. By adopting this design scheme, the design time for this type of D/A has been greatly reduced, and a signicant amount of data has been gathered for fault diagnosis. As an example of the design speed-up, the second of the two chips fabricated required only ve days from the time of receiving the design specications to sending it out for fabrication. All three D/As required only one fabrication run each.

2 Design Specications
Mirror 1x 1x Vdd

Iref iout isink

N1

1x

1x

1x

N2

1x

2x Stage 2

N21

Stage 1

Figure 1: D/A Architecture

The converter that has been built is an interpolative switched current source D/A [4] (Figure 1). Given an N -bit digital word (Din ) and a reference current ( Iref ), it returns an output current ( Iout ) which is proportional to Din . The converter has two stages. The rst stage consists of unity or linearly weighted current sources each having a nominal value of 1 Iref . This stage decodes the rst N1 bits of Din . Depending 2N1 on these bits, the currents are either channeled to the output (Iout ), the current mirror, or the current sink ( Isink ). If it is determined that n current sources need to be switched to Iout then the rst n current sources are switched to Iout ; the (n + 1)th current source is switched to the current mirror, and the remaining unused current

sources are switched to Isink . The second stage is made of binary weighted current sources with the smallest current source having 1 a nominal value of 2N Iref . It decodes the remaining (N N1 ) bits (N2 ) of Din . Depending on the remaining bits, these current sources are either switched to Isink or to Iout . The currents are summed at the Iout node producing the analog output current.

Type Architecture Performance Operation Technology Layout

Specications

N1 , N2

Optimization

Max 3 bound on INL, max 3 bound DNL Supply voltages, output voltage (Vout ) range, Iref Design rules, SPICE parameters, process variation ( W , L ), threshold voltage variation ( aVFB ) [5] Input/output terminal locations, non-default cell placement, minimum wire widths for critical signals, use of bonding pads for a stand-alone part, etc. Non-default cost function(s)

Table 1: Design Specications

Table 1 lists the set of design specications for the D/A. They are broken down into different categories; each of which is handled differently as will be described later. The user enters these parameters to the D/A module generator.

3 Synthesis Path
Figure 2 shows the two-level hierarchy used in the synthesis process. The ve partitions or blocks into which the D/A has been divided each contain a set of constraints and a set of parameters to be determined by the generator for that block. The synthesis begins at the top-most block and descends by choosing values for the parameters of that block. These chosen values then become constraints for the next block. This continues until all of the nal low level parameters (e.g. transistor sizes) are chosen. The following sections explain the constraints and parameters applied in this design.
D/A

The rst is the behavioral simulator [3]. Its primary input parameters are the ones listed in Table 2, as well as some of the architectural, operational, and technological information found in Table 1. The simulator returns the statistical INL and DNL characteristics for the D/A converter. It is important to note that the behavioral simulator is implementation independent; the current sources do not have to be the ones shown in Figure 1. The simulations performed are valid for any current source circuit that can be characterized by the parameters in Table 2. A nonlinear optimizer [6] is the other tool that is invoked. This tool requires the performance and optimization information found in Table 1. The performances are used as constraints for the optimization problem. The objective function maximizes the exibility or the chances that the low-level blocks can be implemented. For example, the exibility function implemented is one which estimates how difcult based on basic device mismatch data a certain i is to obtain, and how difcult a certain R is to achieve based on the architecture and operating conditions. For example, the exibility is increased when i is large, since current sources with larger mismatches are easier to build, and likewise, the exibility is decreased when R is large, since current sources with large output resistances are more difcult to build. Figure 3 shows example exibility functions for i and R. It is also important to note that the marginal exibility increase for i decreases as i becomes large. This accounts for the fact that beyond a certain point, the mismatches are so great that almost no design benet is gained from building worse matched current sources from such ill-matched current sources at the start. Similarly, there is a decrease in the absolute value of the slope as R becomes small. A hyperbola and a parabola are used respectively for the exibility functions.
Flexibility Flexibility

0.00 2.00 4.00 6.00 8.00 0.00 200.00 400.00

0.00 1.00 2.00 3.00 4.00 0.00 200.00 400.00

sigma (amps * 106 )

rout (ohms * 10 6)

Figure 3: Example exibility functions for

Linear Array Current Mirror Binary Array Routing

and R.

Figure 2: D/A Hierarchy

Working together, the nonlinear optimizer chooses numerical values for the parameters in the D/A. The performance of the D/A is evaluated using the behavioral simulator, and more values are chosen. This process continues until all of the performance criteria have been met and the exibility function has been maximized.

3.1 High Level Synthesis

The top block in the design as shown in Figure 2 is the D/A. The constraints at this level are the overall D/A performance specications, INL and DNL. The parameters for this block are shown in Table 2. Two tools are applied to select values for these parameters.
Parameter Description Standard deviations of the current sources in the linear, mirror, and binary array respectively. Output resistances of the current sources in the linear, mirror, and binary array respectively. Errors introduced from block level routing.

3.2 Low Level Synthesis

The selected values (denoted by a ) from the high level synthesis above now become constraints for the four blocks in the next level of hierarchy. For example, iL and RL are the constraints for the linear array generator. As long as the linear array generato r produces a current source array with i iL , and an R RL , then based on the behavioral level simulation results, it can be asserted that if all of the low-level blocks meet the constraints on i and R then the D/A performance constraints (i.e. INL and DNL) will be satised. This assertion is checked during the nal extraction and verication phase (Section 3.4) at the end of the design cycle. Given the high-level constraints, the linear, mirror, and binary array generators are invoked to select the widths and lengths of the main and cascode transistors. As before, a simulator and an optimizer are used. SPICE enhanced with a statistical package re-

iL , iM , iB

RL , RM , RB

4INL, 4DNL

Table 2: Parameters for D/A Block

ceives as inputs a set of W s and Ls corresponding to the main and cascode MOS devices along with architectural, operational, and technological information from Table 1, and returns i and R. The optimizer, employing a cutting plane algorithm [7], minimizes the layout area subject to the constraints on i , R, and operating condition constraints from Table 1. Then, as at the high-level, the optimizer chooses values the parameters, in this case the W s and Ls; invokes the circuit simulator to determine whether or not the constraints are satised; and continues until the objective function has been minimized and the constraints have been met. If completed successfully, the selected values, W s and L s, will satisfy the i , R, and operating condition constraints. Therefore, with the previous assertion on the relationship between i s and Rs to INL and DNL, the D/A generated should meet the performance constraints on INL and DNL.

Figure 4: One 10-bit D/A (MOSIS 2.0 m, N-well)

3.3 Physical Layout

The layout generation phase consists of two steps. First, the three arrays based on the results from the low-level synthesis phase are generated. The linear array, the binary array, and the curre nt mirror generators use templates to create subcells, which are tiled to generate the desired blocks. The binary array current sources are tiled together, and the summed currents are passed to a bank of switches. The linear array uses a standard two-dimensional structure [8], with the addition of new decoding circuitry to select the interpolated output. To minimize sensitivity to process gradients, the binary array current sources are connected in a common centroid pattern, and the linear array devices are switched using a symmetrical switching pattern [8]. A standard cell generator was used to synthesize the logic and latches needed for the D/A. With complete schematics from the low-level blocks, INL and DNL constraints, and layout information from the design specications, the three analog blocks along with the digital block, are routed. [3] describes how INL and DNL are calculated.

Figure 5: Two 10-bit D/As (MOSIS 2.0 m, P-well)

falling edge is the clock assertion, and the second edge is the current output fed into a current-to-voltage converter implemented using a 100 MHz operational amplier with a feedback shunt resistor.

3.4 Extraction and Verication

During this nal phase, a full layout extraction including routing parasitics is performed. The results for each block is fed into the circuit simulator which returns iL , iM , iB , RL , RM , and RB . Then this plus INL and DNL is fed into the behavioral simulator which returns the INL and DNL statistics for the D/A generated. Sensitivity analysis at the behavioral level [3] is used to insure that extra parasitics introduced in the routing has not degraded the D/As performance beyond the INL and DNL amount allocated.

5 Mismatch Extraction
In addition to its use during the synthesis phase, the behavioral simulator also provides a vehicle for fault diagnosis once the design has been fabricated, since the behavioral model used captures all of the essential mismatch effects. From the measured INL curves, the mismatch for each component (i.e. current sources) can be derived for all of the experimental chips. Using linear regression, the best estimate can be computed for each mismatch parameter assuming that the mismatch distributions are Gaussian. For example, shown on the left in Figure 8 are the measured
lsb 2.0 0.0 2.0 digital code lsb 2.0 4/6 D/A lsb 2.0 4/6 D/A lsb 2.0 0.0 2.0 digital code 5/5 D/A lsb 2.0 5/5 D/A 6/4 D/A

4 4 4 Experimental Results

We have fabricated three 10-bit D/As. The rst chip (die photo shown in Figure 4) contains a D/A with N1 =5, N2 =5 (5/5) partition. The active area is 1.92mm2 . The second chip (die photo shown in Figure 5) contains two D/As one with N1 =6, N2 =4 (6/4) and the other with N1 =4, N2 =6 (4/6). The active areas are 2.86mm2 and 3.81mm2 , respectively. The areas compare reasonably with previously published D/As [9][10]. The performance specications in all three cases was that there be no more than 2 lsb of INL error and 0.5 lsb of DNL error. Figure 6 depicts the measured INL. The top set of graphs show the data gathered from all of the parts while the bottom set depict only the components which met the performance specications. Although not in the design specications, transient testing on the D/A shows that for a full-scale switch at the output, the D/A can settle to 1 lsb for 10 bits from the start-of-conversion in 20ns. The delay incurred from the falling edge of the clock to the start-ofconversion is 10ns. A plot of this is shown in Figure 7. The rst

lsb 2.0 0.0 2.0

ALL PARTS

digital code

PARTS MEETING SPECIFICATIONS

6/4 D/A

0.0

0.0

0.0

2.0 digital code

2.0 digital code

2.0 digital code

Figure 6: Measured INL for the three D/As

3.6V

Design Phase Behavioral model development High-level optimization Low-level synthesis Incorporation of new unit cell to layout tool Layout generation Extraction/Verication

Time Required 4 hours 10 hours 5 hours 2 days 2 hours 5 hours

100mV /div
EA

trigd

Table 4: Design Times

both the design specications and the gathered technology information from the nished products. The fabricated parts worked the rst time. Table 4 gives an idea of the design times required for each of the design phases. The times shown in Table 4 are estimates on how long it would take to re-do each of these phases given a completely new set of design specications (those found in Table 1). Future work on the D/A design example include adding transient constraints into the design specications and the introduction of new circuits such as ones for higher speed and ones for self-calibration based on the test results. Future work on the design scheme includes building larger systems. It is hoped that the design environment of these systems will also be improved, and that the methodology will be augmented as well, giving it eventually the power necessary to design quickly and effectively the large mixed-signal systems which are so prevalent today.

2.6V -40.8ns Rise error

Fall 2.803 ns

ET 10ns/div Measurements

Compare & References

Proximal 32 %

59.2ns Rem Wfm 2 Avg Main Distal 100 %

Figure 7: Falling Edge for the 10-bit 6/4 D/A

INL results for one of the 5/5 D/As. On the the right is shown its estimated component mismatches. The validity of these results was checked by re-computing the INL based on these estimates and comparing them to the measured INL. The maximum difference between the curves was 0.08 lsb. This component mismatch information can be used for fault diagnosis. For example, Figure 8 shows that most of the mismatches are due to the center s1 (linear array) elements. Future designs can try to improve upon this.
1 0.5

7 Acknowledgements
The authors would like to thank Micro Linear for providing design examples. This research has been partially supported by The National Science Foundation; The Intel Foundation; SRC (93-DC008); and DARPA.

Mismatches (dx/x)

INL (LSB)

0 -0.5 -1 -1.5 -2 0 200 400 600 800 1000 1200

0.01 0.005 0 -0.005 -0.01 -0.015

References
Components

Input Code

Figure 8: Measured INL and Component Mismatches

Component mismatches, in general, are caused by underlying basic statistical process variations. In this design, assumed were underlying process variations [11] [12] such as the at band voltage variations, aVFB , and the standard deviation of the MOS transistor widths and lengths. Using the component mismatch data measured at two reference currents and using a basic mismatch formula [13], the process mismatches can estimated. Table 3 shows the results. The close agreement between the assumption and the extracted results validates the assumptions made during design.

paVFB
W

Constants

units V

Assumed 0.0623 0.05

5/5 D/A 0.0555 0.0437

Table 3: Basic Statistical Process Variations

6 Conclusion
Following the top-down, constraint-driven paradigm, a complete design cycle for a class of D/As has been performed. The cycle was begun with a set of high-level specications and low-level assumptions on the technology, and was completed with the verication of

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s2:16x s2:8x s2:4x s2:2x mirror s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1