RESEARCH PAPERS

DEVELOPMENT OF A CONTROL PATH VHDL CODE

GENERATOR FOR HARDWARE DEVELOPMENT

By
MARCUS LLOYDE GEORGE * BRANDON JOSEPH **
*-** Department of Electrical and Computer Engineering, University of the West Indies, St. Augustine, Trinidad, Tobag.

Date Received: 30/04/2022 Date Revised: 02/05/2022 Date Accepted: 15/05/2022

ABSTRACT
The Very High-Speed Integration Circuit HDL (VHDL) is widely used to implement digital electronic systems. The VHDL
language can be difficult to learn, so it is necessary to simplify and speed up the process of implementing digital
electronic components through a hardware description with a minimal understanding of the VHDL language. This paper
entails the design and development of a Graphical User Interface (GUI) capable of generating VHDL code for
ControlPaths using specified state transition tables and state diagrams. This application was created using the Matrix
Laboratory (MATLAB). Application Builder as the development platform. After development, the system went through unit
testing and integration testing, after which acceptance testing was carried out. The results of the acceptance tests
showed that the software is very effective in quickly generating VHDL code for ControlPaths.
Keywords: Code Generators, VHDL, Hardware Description Language, Hardware Design, Digital Logic Design,
ControlPath, Finite State Machine.

INTRODUCTION Configurable Logic Blocks (CLBs) interconnected by

Very High-Speed Integrated Circuit Hardware Description programmable interconnects. In an FPGA, several
Language (VHDL) is a language used to describe the operations can be performed in parallel so that the
design of digital equipment. It is a standard Hardware algorithms required by control systems can be executed
Description Language (HDL) used in the development of quickly (Amol et al., 2009; Hamdan 2018; Kalage 2009).
digital electronics. VHDL has been adopted by electrical A general-purpose architectural model that describes a
engineers worldwide due to its versatility and feature set. method for designing digital equipment is called a Finite
However, because VHDL is a large and complex State Machine—Data Path (FSM-D) model. The FSM-D
language, learning it in depth can be difficult for some model consists of two main components, such as the
developers (Davis, 2018). The IEEE 1076 standard is a VHDL finite state machine (FSM) and the data path. These
language reference that defines VHDL and its components perform tasks or algorithms programmed
applications. VHDL can be used to map Field for FSM-D. State machines are used in the design of digital
Programmable Gate Arrays (FPGAs) or Complex circuits and are also known as the ControlPath. A state
Programmable Logic Devices (CPLDs) during the design machine is a behavioral model consisting of a finite
phase of digital electronic systems. FPGAs are number of states, state transitions, and actions (Areno,
semiconductor devices that consist of an array of 2007). For the FSM-D architectural model, FSM manages
the execution of tasks and algorithms while the data path
handles numerical calculations, register transfer, and
data manipulation. The ControlPath consists of the states
shown in the state diagram, decision points, inputs, and
outputs.

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When a ControlPath is created, it contains several states method, and the pattern-based method (Franky &
encircled by circles or ovals. Each state contains state Pavlich-Mariscal, 2012). Most code generators are
transition logic, next state logic, and output logic. These implemented using a template method. The template
states are connected using two signals. These signals provides a way to generate code using models that
read and write the current state and the next state in contain inputs. The template describes a method for
memory. The steps for implementing a state machine converting data entered into a program into text files.
include creating an FSM object, declaring a state, Templates provide more flexibility than other methods
creating a transition process to the next state, creating a because templates can be replaced to generate code
next state logic process, and creating an inference logic for alternative architectures and platforms. Template
process. languages tend to have conditional loops and
The skills and knowledge required to use VHDL effectively statements that write parts of text according to logical
make it difficult to learn the language. Thus, it is necessary conditions that are met. Templates also use variables to
to make the process of introducing digital electronics store the input required by the code generator. Finally, the
simpler and more intuitive. The process of creating generated code consists of verbatim text written by the
ControlPaths can become tedious for complex systems developer of the code generator. As system complexity
with many states. This paper entails the development and increases, template maintenance increases. The
implementation of a Graphical User Interface (GUI) debugging process can also become tedious, as code
capable of plotting state charts, appropriate VHDL must be run against the current template and then
ControlPath code, and VHDL testbed code for the debugged until patches for the template are received.
provided state tables. The state diagram is built on a Code generators can be created by replacing regular
graphical interface using a menu, which allows the expressions. This method uses a template that describes a
creation of digital electronic ControlPaths with specified list of character strings (Franky & Pavlich-Mariscal, 2012).
states. The GUI also allows the creation of signals that will Regular expressions consist of certain required
be used to switch between states. characters. They also use a character class construct that
1. Literature Review extracts a list of characters that match a given location.
There are also quantifiers that check for the presence of
There are two main types of code generators used in
certain characters in a string. Regular expressions can
software development. They are active code generators
match strings that follow the specified regular expression
and passive code generators (Sejans & Nikiforova, 2011).
and can replace or transform strings. Replacement strings
The code generator type describes how often the code
contain the text that is replaced with each regular
generated during use is updated. The active code
expression match when performing a search and
generator generates code as it performs actions in the
replacement. If source code for a functional link exists
code generation software. In contrast, a passive code
from a previous project, that source code can be used in
generator generates the code only once, providing the
a code generator program. Then regular expressions and
user with a code template to complete later. The design
source code are used as input. They are used as
goals required that the developed control channel code
parameters, replacing parts of the reference source
generator be primarily a passive code generator. This
code with new code, thus outputting new source code.
means that the code is only generated once after the
user completes the input for the desired design. Loniewski (2010) proposed another code generation
method called the model-driven approach, which uses
There are several methods by which code generators can
the concept of Model-Driven Design (MDE). This type of
be implemented. The main methods are the regular
engineering method aims to bridge the gap between
expression substitution method, the model-based
software and the realm of the problem. MDE achieves this

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by using models that define complex systems at a high Susanti et al. (2011) suggest MathWorks has created a
level of abstraction. A unified modeling language is used hardware description language code generation tool
in MDE to help implement and develop complex models. called HDL Coder. Using MATLAB functions, Simulink
There are also hybrid forms of code generation models, and Stateflow charts, the HDL Coder generates
approaches. Regular expression or pattern-based portable, synthesizable VHDL code (Thompson et al.,
methods can be used when generating MDE code. With a 2008). The HDL Coder allows programming Xilinx,
template-based approach, the code generator injects Microsemi, and Intel application boards in MATLAB.
models and saves them in various formats. The Stateflow charts allow the implementation of Moore and
implementation of regular expression substitution can be Mealy automata and control logic.
done using models. After the implementation of code MathWorks has also developed tools for creating
generation and the design phase, there are methods graphical interfaces. The old version of their software for
used to develop graphical user interfaces. The design creating Graphical User Interface (GUI) applications was
patterns applicable to the code generator user interface called Graphical User Inter face Development
are the Model-View-Controller (MVC), Model-View- Environment (GUIDE). GUIDE has been replaced by the
Presenter (MVP), Model-View-ViewModel (MVVM), and MATLAB Application Builder as it has improved the usability
Model-View-Intent (MVI) methods (Syromiatnikov & and features of GUIDE, making it easier for users to create
Waynes, 2014). GUIs. MathWorks has documented GUIDE migration
Tselepis et al. (2006) developed a graphical user strategies so developers can use App Designer.
interface for the automatic generation of VHDL code 2. Design
describing the topology of systolic arrays. This tool makes
The ControlPath VHDL Code Generator had to be
the hardware implementation of a wide class of software
designed before it could be developed. The design
applications available to both VHDL and non-VHDL
techniques, models, algorithms, and standards
developers. The paper states that the user is only required
employed in the system's development are discussed as
to know the requirements of the software application to
follows,
develop a solution.
2.1 MVC Model
Muhammad (2018) developed and implemented an
All data-related functions that the user interacts with are
FPGA-based VHDL generation tool to implement
represented by the Model component. This can be data
Convolutional Neural Networks (CNNs). The tool was
passed between the View and Controller components, or
created using the Java programming language. It states
any other data related to business logic. For example, a
that their VHDL Generation Tool (VGT) reduced the
customer object will get customer information from a
development time needed to implement CNN efficiently.
database, modify it, and either update or push the data
This has facilitated the process of hardware acceleration
back to the database.
of CNN models through the use of FPGAs through
All of the application's user interface functionality is
parameterization of the implementation of the models.
handled by the View component. For example, the
Another code generation tool can be found in the Xilinx
customer view will include all the user interface
ISE WebPack environment. This tool is called StateCAD
components that the end-user interacts with, such as text
and allows the design of digital blocks based on the
boxes, dropdowns, etc. Controllers serve as the link
description of the state diagram using a graphical input
between the model and view components, handling all
tool. It can be used to generate HDL code using VHDL,
business logic and incoming requests, manipulating the
Abel, or Verilog depending on the state diagram for
data with the model, and interacting with the views to get
synthesis and simulation.
the final result. The client controller, for example, will

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handle all interactions and input from the client view and the goals of the ControlPath VHDL Code Generator GUI in
use the client model to update the database. The client mind. Microsoft Visio was used to help design each user
data will be rendered using the same controller. interface. Microsoft Visio is a CAD (computer-aided
The model should be assigned to controller inputs to design) tool for creating user interfaces and experiences.
make it easier to bind data from the controller to the Figure 2 shows an entity generation window UI design.
model. The model then interprets the user input and The first view developed was the EntityView, as shown in
updates the controller with real-time responses. As input is Figure 2. This view will be presented to the user after
entered, the model updates the corresponding view, executing the ControlPath VHDL Code Generator
providing feedback to the user. Once the update is executable. To start designing a system, first create a state
viewed, it can customize the design using the controller. diagram or state table before using the GUI. The user
Figure 1 shows the architecture of the Model View should then be able to enter the desired object name
Controller diagram. and architecture name using text input fields, as shown in
2.2 User Interface (UI) Design Figures 1 and 2. It must also be able to enter mandatory
port definitions such as clock port name and reset port
Each view and its characteristics have been created with

Controller Model View

DataBinding
EntityGenerationInputs EntityModel Update EntityView
Responses

EntityData

DataBinding
StateMachineSignalAndProcessNamesInputs
Responses

Update ArchitectureView

DataBinding
StateEnumerationInputs ArchitectureModel
Responses

Update StateDiagramView

DataBinding
OutputLogicProcessInputs Responses

ArchitectureData

DataBinding
VHDLTestbenchInputs TestBenchModel Update TestBenchView
Responses

Figure 1. The Architecture of Model View Controller Diagram

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Figure 2. Entity Generation Window UI Design

name. The user can then add other ports to the port table editing program the user wishes to paste it into. The "Zoom
displayed in the lower-left corner of the window. The user In" and "Zoom Out" underneath the "State Diagram"
should be able to enter a port name in the "New Port window remain disabled until the State Enumeration step.
Name" field and then click the "Add Port" button displayed The "View Details" and "View All" toggle should also remain
in the window. This action adds the port to the ports table disabled until the State Enumeration step. Once the user
shown on the Add Port and Remove Last Port buttons. The has clicked on "Finish" for their entity, the "Next" button
user can also click the Delete Last Port button to remove located underneath the "Finish" button becomes
the last port added to the table. enabled. This "Finish" button should also disable the user
The "Finish" button becomes available only when the from adding any more ports to the port table. Once the
user's port table contains at least three inputs, including a "Next" button is clicked, the "Entity Generation" panel seen
sync port and a reset port, and one output. The "Finish" on the left in Figure 3 disappears and the "State Machine,
button creates a text file (.txt) with the name of the entered Process and Signal Name" panel appears. The lamps
object. This text file stores all the ControlPathCode located next to each text input field should switch to the
Generated for this step and future GUI steps. The code colour red whenever the user does any of the following,
stored inside this file must be continuously read and its ·Enters a string that is more than 15 characters long.
contents displayed in the "ControlPath VHDL Code ·Enters any digits.
(Preview)" text box.
·Enter any special characters, including spaces.
The user should be able to click on the "Copy" button
·It leaves the field empty.
located underneath the "ControlPath VHDL Code
·Enters any previously entered or VHDL reserved word
(Preview)" to copy the code inside of the preview to the
Once the user satisfies all the conditions stated for the text
clipboard. This code can then be pasted into any text

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input fields, the lamp turns green, indicating to the user to the criteria that the lamp tests, the Done button
that their desired name is valid. becomes available. When the user clicks the Done
Figure 3 shows the “State Machine, Process and Signal button, the GUI should store the entered names in
Name” window in which the user should be able to do as memory for use in future steps. The GUI should also store
given below, the words into the word bank to ensure that no name is
repeated in the future, avoiding errors in the generated
·Name their state machine using the “State Machine
code.
Name” text input field
Figure 4 shows the “State Enumeration” window that
·Name their present state signal using the “Present
appears once the user navigates on from the “State
State Signal Name” field
Machine, Signal and Process Names” window. The user
·Name their next state signal by using the “Next State
should be able to:
Signal Name” field
·Enter their desired reset state name in the “Reset State
·Name their clocking process by using the “Clocking
Name” text input field
Process Name” field
·Enter their desired idle state name in the “Idle State
·Name their next state logic process using the “Next
Name” text input field
State Logic Process Name” field
·Enter their desired next state name in the “Next State
The lamps in this window act as error indicators, similar to
Name” text input field
the lamps shown in the Entity Generation window. These
·Select whether the state loops internally or not using
indicators change color when non-unique names are
the “Loops Internally?” Dropdown
entered into any of the text fields displayed in this panel.
Once each field has unique and valid entries according ·Select whether the state loops internally using the
“Loops Internally?” Dropdown

Figure 3. State Machine, Signal and Process Names Window UI Design

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Figure 4. State Enumeration Window UI Design

·Select their desired internal loop exit logic using the internal loop exit logic using the "Internal Loop Exit Logic"
“Internal Loop Exit Logic” dropdown dropdown. The user can then click on the "Add State"
·Select their desired secondary exit using the button to add the idle state to the state table. The idle
“Secondary Exit” dropdown state text input field then becomes disabled, and the
"Next State Name" text input field is then enabled. The
·Select their desired secondary exit logic using the
"Secondary Exit" and "Secondary Exit Logic" dropdowns
“Secondary Exit Logic” dropdown
also become enabled.
The user must first enter the information required for the
The user should then be able to enter the next desired
reset state. When entering the reset state name, all other
state using the "Next State Name" text input field. It can
inputs in the "State Enumeration" panel are disabled.
also be specified if,
Once the entered reset state name satisfies the required
text input conditions, the lamp next to the reset state ·The state loops internally
name turns green. When the user clicks on the "Add State" ·The state has internal loop exit logic
button, the reset state name is added to the state table. ·The state has a secondary exit and corresponding
The "Reset State Name" field is then disabled and the "Idle secondary exit logic
State Name" field becomes enabled. The "Loops
If the user has specified the desired parameters for the
Internally?" and "Internal Loop Exit Logic" dropdowns are
state to be added, click the "Add State" button to add the
also enabled. These two dropdowns should allow the user
state to the state table. If the user wishes to remove the last
to decide whether the state they are about to enter into
added state, then click on the "Remove Last State" button.
the state table loops internally and contains exit logic. If
Once the reset state, idle state, and at least one other
the state loops internally, the user then has to specify an
state has been added, the "Finish" button becomes

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enabled. The user should then be able to click on the Once the user has finished the state enumeration, the GUI
"Finish" button, which would lock all the state enumeration will determine, based on the parameters of the final
inputs to prevent further adjustments. This "Finish" button added state, if to draw an arrow looping back to the idle
generates the architecture code corresponding to the state or not. According to Figure 5, the output logic
states, state machine, process, and signal names that the process name should be able to be entered into the
user inputted in steps two and three of the GUI. The code is "Output Logic Process Name" text input field.
saved into the text file created in the entity step. The VHDL The Output Logic Process table should then be populated
code stored in this file is then read from and displayed in with the names of each state from the "State
the "ControlPath VHDL Code (Preview)" textbox. The "State Enumeration" step along with the state number. There
Enumeration" panel should also disappear, and the should be columns for each output port entered into the
"Output Logic Process" window should then appear. port table from the Entity Generation step next to each
Every time the “Add State” or “Remove Last State” buttons state. Inside these columns, there should be checkboxes
are pressed, the “State Diagram” panel of the window that the user can tick to indicate the outputs that go high
updates to reflect the current architecture. Each state for each state. Once the user has specified the high and
added to the architecture is illustrated as a circle on the low outputs for each state, it should be able to click on the
state diagram. The transitions between states should be "Finish" button. This action causes the output logic process
represented by arrows exiting the bottom of each state VHDL code to be generated and saved into the
and entering the top of the next. If any state has internal ControlPath text file. The output labels for each state
exit loop logic, it will be labeled next to the corresponding should also be placed on the state diagram to the right of
transition arrow. Also, if the state loops internally, the each state. Figure 6 shows the design for the "VHDL
internal exit logic for that state will be labeled next to it. Testbench" window, which is the final part of the entire

Figure 5. Output Logic Process Window UI Design

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Figure 6. VHDL Testbench Window UI Design

ControlPath for the VHDL Code Generator GUI. Xilinx Integrated Synthesis Environment (ISE) Design Suite
This window should allow the user to generate a VHDL for further development of the system. When installing a
Testbench which tests the generated ControlPath to system or importing an existing system, ISE Design Suite
ensure that all states are following the user's selected allows including .vhd files. For users who want to view the
outputs and loops as designed. On the "VHDL Testbench resulting code but do not have access to an IDE such as
Panel", the user should be able to generate a Virtual Hard the ISE Design Suite, the .txt format has been used. This
Disk Drive (.vhd) testbench file containing the code to test format is recognized by Notepad, a Text Editor that comes
the designed ControlPath by clicking on the "Generate preinstalled on all Windows computers, making it easy to
Testbench File" button. This button also generates a text check the generated code. Figure 7 shows an Entity
file (.txt) which is read from to populate the "VHDL Relationship Diagram which describes the connections
Testbench Code (Preview)" with the VHDL code that tests between the models for the ControlPath VHDL code
the user's designed ControlPath. Users should also be able generator. This diagram follows the MVC pattern, where
to navigate to previous steps by clicking and moving their models represent the data within the system.
cursor on the menu located at the top of the GUI. The models that were used in this GUI are,
2.3 Data Design ControlPathModel, ArchitectureModel, TestbenchModel,
EntityModel, PortModel, and StateModel. These models
The VHDL code is the main output of the system. The
each represent various aspects of the system and share
generated source code was stored in virtual hard disk
connections. Figure 7, which is an Entity Relationship
(.vhd) files and a text file (.txt). The .vhd file format was
Diagram (ERD), depicts the relationship between the
chosen to store the source code generated in case the
models. This ERD depicts the data structure utilized by the
user wants to import the source code into another
system for storing information, as well as the development
Integrated Development Environment (IDE) such as the

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ControlpathModel

Name
Entity
Architecture
Testbench

TestbenchModel
TestbenchName
EntityModel ArchitectureModel Stimulus
EntityName ArchitectureName
ClockPortName StateMachineName
ResetPortName PresentStateSignalName
Ports NextStateSignalName
ClockingProcessName
NextStateLogicProcessName
ResetStateName
IdleStateName
States
PortModel
NewPortName
Direction
StateModel
ID
NextStateName
InternalLoopCondition
InternalLoopExitLogic
SecondaryExit
SecondaryExitLogic
Outputs

Figure 7. Entity Relationship Diagram of ControlPath VHDL Code Generator

Start
of the ControlPath state diagram and VHDL code.
2.4 Algorithms
The main algorithm involved in the Entity Generation step
of the ControlPath VHDL Code Generator as shown in
Figure 8. In this diagram, the user starts off by determining End

if there are any ports in the entity. For the entity, the reset No
Any Ports in
Entity?
port and clock port must be defined before any other
ports can be added to the port table. Each port name
added to the table must satisfy all input conditions. If there Yes
Generate Entity
are no ports in the entity, the user cannot proceed Code
forward. If there are ports in the entity, each port added For Each
End of List
Port
has to be assigned a direction before being added to the
port table. Once the user has finished adding in all their Out
ports, then it generates the code for the designed entity's
VHDL code. In
Port
Direction?
The Unified Modeling Language (UML) activity diagram
shown in Figure 9 outlines the algorithm for the
architectural generation step of the ControlPath VHDL
Code Generator. In this step, the user must first name the Figure 8. UML Activity Diagram for Entity Generation

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Start

Enter State Machine, Signal and Clocking

Process, Next State Logic Process and Reset
State Names

Does this
Architecture
End No
have any
states?

Yes

For Each
End of List
State

Does this
state loop
Select Outputs For
internally?
Each State

Yes

No
Select Internal Exit
Logic
Generate
Architecture Code

Does this
state have a
Select Secondary Exit Yes secondary
No
loop?

Select Secondary Exit

Logic

Figure 9. UML Activity Diagram for Architecture Generation

state machine, signal, clocking, and next state logic secondary exit logic to proceed.
processes. Then define the reset state and idle state. If the user has completed adding states, then select the
When defining the reset state, the user cannot choose outputs that will go high for each state. The ControlPath
any loop conditions. When defining the idle state, the user operates by continuously looping through the list of states
can choose internal loop conditions but no secondary until it reaches a state with an internal loop without internal
exit conditions. Once done, the user must determine exit logic or if the state machine has been reset. Once the
whether or not the architecture has other states. If the user has defined the outputs for the created states, then it
architecture contains other states, the user must select generates the ControlPath's VHDL architecture code. At
whether the state contains an internal loop. If so, the state this step, the ControlPath code file is created with all of the
can be assigned internal loop exit logic. The user can also code required for the ControlPath to function. The
indicate if this state has a secondary exit by selecting one generated ControlPath .vhd code file can be imported
of the previous states on the secondary exit dropdown. into Xilinx Integrated Synthesis Environment (ISE) for
Once a secondary exit is specified, the user must select verification. This ControlPath can then be tested using the

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corresponding testbench code, which the GUI also validation.

provides for the user. 3. Implementation
The algorithm also duplicates by storing any data that the The implementation phase of this ControlPath VHDL code
user enters into the port or state tables. The algorithm then generator consists of several steps, which will be entailed
checks any string entered in the edit text boxes against as follows,
the VHDL reserved words and stored data. Once the
3.1 Software Platform and Programming Tools
program determines that the entered row satisfies all input
This project required MATLAB to be a development
criteria, it is allowed access to add to the appropriate
platform. Thus, the MATLAB App Designer interface was
table. A similar duplication avoidance algorithm is also
used to develop the graphical user interface. MATLAB App
applied to the state enumeration drop-down lists, through
Designer contains ready-made front-end elements such
which the user specifies the internal exit logic and the
as buttons, radio buttons, axes, windows, and panels.
secondary exit logic. The dropdown algorithm removes
There is also comprehensive information about the
any exit logic used for previous states.
properties of each element provided by the developers
2.5 Standard Compliance
of MATLAB, known as MathWorks. App Designer allows
To ensure that user input in the user interface is valid and developers to focus more on the business logic of the GUI,
conforms to the VHDL reference guide standard, several rather than wasting time on redundant tasks of coding,
functions were created to perform user interface property design, and layout of front-end elements. Pre-MATLAB App
validation each time an action or event is triggered on Designer is an upgraded version of the legacy MATLAB
that particular element in the GUI. MATLAB functions have GUIDE system. This development environment helps
been used as part of the validation functions because the developers write code to run their user interfaces. It also
test strings meet the required criteria for input into allows quick testing of the developed GUI, aiding in the
memory. The text input validation functions ensured that process of error detection and debugging. Table 2 shows
the generated ControlPath contained no errors. Once some development tools.
there were no errors in the system, the user could continue
3.2 Hardware Specifications
designing the ControlPath. Whenever the user violated
The hardware specifications of the computer that the
the text input requirements, the add button was disabled.
ControlPath VHDL Code Generator GUI was developed
Errors are reported to the user by lamp indicators located
and tested are shown in Table 3. This combination of
next to each text entry field in the GUI. The indicator lamp
components improved the development process of the
turns red for invalid entries and green for valid entries.
ControlPath VHDL Code Generator by providing MATLAB
Each time the user adds text data to a table in the GUI, the
with adequate computing resources.
data is stored in the reserved word bank. This word bank
3.3 Software Development Life Cycle and Version Control
contains predefined VHDL reserved words as well as
previously entered data. This is used to prevent duplicate The program has to be planned and built-in to meet the
or invalid entries in the system. Table 1 shows the input project's goals. The investigation and selection of a

Condition Input Output Description

stringLength string bool Checks the length of the input being typed in the text input field to see if it exceeds 15 characters in length. This ensures that
labels do not exceed the size of state circles, allowing the state diagram to be clearer to the user.
isLetter string bool Checks each character in the string being entered for alphabetic characters, preventing the user from inputting any spaces,
digits, or special characters.
isEmpty string bool Checks the text input field to see if there are any characters.
alreadyExists string bool Compares the string with a predefined list of strings that contain specified reserved words according to the VHDL language
reference manual

Table 1. Text Input Validation Checks

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Tool Description

MATLAB MATLAB was installed on the computer being used for development and was used as the console for debugging the GUI
MATLAB App Designer The App Designer feature of MATLAB was the tool mainly utilized for the development of the GUI. This tool offered two developmental views.
These views were the Code View and the Design View.
Google Cloud Online cloud services such as Gmail and Google Drive were utilized for backing up versions of the software as well as for logging progress.
Xilinx ISE 14.7 This is a VHDL developmental environment which was used to synthesize the ControlPath VHDL code produced by the GUI
Xilinx ISE Simulator (ISIM) This is a hardware descriptive language simulator integrated within Xilinx ISE. This tool was used in conjunction with the testbench VHDL
code generated by the GUI, to simulate the waveforms produced by the designed ControlPaths
Microsoft Visio This tool was used to draw the test cases in the form of state diagrams and entities used for testing the ControlPath GUI.

Table 2. Developmental Tools

version of the modified waterfall model, known as the V-

Component Specification
model software development life cycle, is shown in Figure
Operating System 64-bit Windows 10 Pro
Graphics Card Nvidia GeForce GTX 1060 6GB 10 (Uttar, 2021).
Central Processing Unit (CPU) AMD Ryzen 5 1600 @ 3.6 GHz
Memory (RAM) 16.0GB
The software development lifecycle model that was used
is the "V" model, which is shown in Figure 10. This model
Table 3. Hardware Specifications of Developmental Computer was suitable for implementing this VHDL ControlPath
software development life cycle were part of the software Code Generator because the process was iterative. The
development process. The administration, flow, and code generator often required changes in the middle of
version control of software development are all aided by implementing modules, resulting in periodic regression to
a software development life cycle. Three software life earlier stages of development. Microsoft Visio was then
cycle models were investigated, with the best one used to display various GUI views. After that, the MATLAB
chosen for this paper. The three models chosen are Pure
Waterfall, Modified Waterfall (V Model), and Evolutionary
Prototyping models. Table 4 compares the three software
development life cycles.
After comparing the three software development life
cycles, the Modified Waterfall (V Model) was selected as it
seemed the most appropriate for this proposed system.
The model allows for highly reliable systems to be created
because of its simultaneous design and testing style. This
approach helps mitigate risks when developing software,
as bugs are often detected earlier in development,
allowing developers to fix them more quickly than in other Figure 10. Modified Waterfall (V-Model)
Software Development Life Cycle
software models, such as the Pure Waterfall model. A

Software Development Life Cycle Advantages Disadvantages

Pure Waterfall Model The pure waterfall model produces highly reliable and scalable systems. This model cannot work well with poorly understood
This model can work with a predefined schedule and provides requirements and architecture.
management with progress visibility.
Modified Waterfall Model This model works well with poorly understood requirements and This model can require more time on average
(V Model) architecture. It can be used to mitigate risks as well as be than other models
used in time-restricted scenarios.
Evolutionary Prototyping This model works very well with poorly understood requirements. This model does not work well with predefined
The software can be changed at any point in the cycle schedules and has low progress visibility

Table 4. Comparison of Software Development Life Cycles

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Application Designer was used to create the front-end disabled, the element's default values, and the visibility of
GUI. The frontend consisted of a user interface for Entity the element. The user can also right-click on any element
Generation, State Machine, Signal and Process Names, to access the context menu. Through this context menu,
State Enumeration Frontend, State Diagram Frontend, the designer can cut, copy, paste, duplicate, or delete
Output Logic Process Frontend, VHDL Test-bench elements. Using this context menu, the developer can
Generation Frontend. After the main elements of the front also add callbacks, which are functions associated with
end were placed or built, the back end was built. The an element event such as a button click.
server part was responsible for processing all the data that Figure 12 shows the MATLAB App Designer Code View
the user entered into the graphical interface. This includes several interfaces that have helped in GUI
included storing object data, architecture data, and development. The Code View consisted of a "Code
state-chart coordinate data. Browser", a "Component Browser", an "Application
3.4 Development Tools and Interfaces Layout", and a code editing space. The Code Browser
MATLAB provides a console that displays error messages also differed in the organization of callbacks, functions,
when developing software. Graphical user interfaces can and properties. Callbacks are functions or blocks of code
also be designed and programmed using App Designer. that are fired by an event or action on a front-end GUI.
The App Designer consists of two different developmental Examples of events that can trigger a callback are,
views, called Design View and Code View. The design opening a drop-down list, clicking a button, typing, or
view, shown in Figure 11, is used to lay out front-end clicking a mouse.
elements such as windows, panels, menus, buttons, axes, Functions were methods of a GUI class. The Code Explorer
input fields, and labels. In this Design view, the user can helps to break down the code into modules so it can
also edit component properties. These properties include quickly find bugs in the software. This feature also helped
the color of the lamps, whether the edit box is enabled or transform large, complex functions into smaller, simpler

Figure 11. MATLAB App Designer Design View

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Figure 12. MATLAB App Designer Code View

ones. Properties consisted of global variables, i.e. information that populates it. Using MVC, this concept was
variables that could be accessed and used between used to establish communication between the controller
different callbacks. These properties were used to store and different GUI views. The inputs were associated with
specific object data, architecture data, file names, signal events such as clicking buttons, entering text in a text field,
names, process names, VHDL reserved words, font size switching, opening a drop-down menu, and selecting a
data, and input validation flag data. drop-down list. For the ControlPath code generator, the
The design view of MATLAB App Designer consists of the data binding is implemented in the.mlapp file. All
"Component Library," the "Component Browser," and the generated VHDL ControlPath code was bound to a text file
design workspace. This view allowed the placement of named after the user object. The test bench code was
interactive and non-interactive front-end elements. This linked to another text file, named after the entity but with
view also allows the user to scale components, add the text "_testbench" appended to the file name.
callbacks for use in Code View, and edit the values and Figures (14) and (15) show the code behind the data
properties of hosted components. binding used in this GUI. The "fopen" function opens a text
Figure 13 shows the generated ControlPath VHDL code file and names it according to the entity name entered by
within the Xilinx ISE environment. The generated ControlPath the user. The "sprintf" function is used to replace instances
code can be verified in this step prior to being simulated of "%s" in the predefined quoted text. This function was
within the simulation step using the ISE Simulator (Isim). used to tie the input string variables from the user to text
like the filename and code. The "fprintf" function then
3.5 Data Binding
writes the data that was stored in the ControlPath's
Data binding is the process of connecting a display
memory into the text (.txt) and virtual hard disk (.vhd) files
element, such as a user interface control, with the
accordingly.

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Figure 13. Xilinx ISE Verification of Generated ControlPath VHDL Code

Figure 14. Data Binding to ControlPath Text File from Entity View

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Figure 15. Data Binding to Testbench Text File and Virtual Hard Disk File from TestbenchView

3.6 Software Workflow architecture and state diagram by enumerating their

The user is guided through five steps when designing their states and naming their state machines and architectural
desired ControlPath. The first step is ControlPath Creation, processes. In the final step, the user can generate their
which includes the creation of a text file named after the testbench code to test their designed ControlPath. Users
entity which will store all the generated code. Next, there is can import the generated code into Xilinx ISE for design
Entity Creation where the user enumerates their input and verification. Figure 16 shows the workflow of ControlPath
output ports. Afterward, the user generates their VHDL Code Generator.

State Transition Next State Logic Output Logic

State Machine
Process Process Process
Generation
Generation Generation Generation

Controlpath Architecture Testbench

Entity Creation
Creation Creation Creation

Controlpath Code
Entity Code and State Testbench Code
Generation Diagram Generation
Generation

Figure 16. Software Workflow of ControlPath VHDL Code Generator

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4. Testing system is "CarParkSystem". Figure 18 depicts a state

The ControlPath VHDL Code Generator has undergone diagram of the parking system's transitions, outputs, and
unit and integration testing during development, using states, as well as secondary output logic. This system is
ten unique test cases in the form of state diagrams and
state transition tables. Integration testing was done
reset = 1
between each view, model, and controller to identify requestFee = 0
validateFeePaid = 0
bugs in the software. After that, system and acceptance resetState openGate = 0
print = 0
testing were carried out to ensure that the system meets done = 0

the requirements, offering users an effective user

requestFee = 0
interface and user experience. This testing method validateFeePaid = 0
idle start = 0 openGate = 0
helped mitigate the risks associated with developing this print = 0
done = 0
GUI. Xilinx ISE, an integrated development environment
start = 1
used in digital electronics development, was used to
requestFee = 1
verify that the VHDL code generated by the system validateFeePaid = 0
startFee openGate = 0
matches the VHDL reference manual. The test cases print = 0
done = 0
consisted of state diagrams and state transition tables. It is
created using a graphical user interface and the resulting requestFee = 0
validateFeePaid = 0
files are imported into the Xilinx synthesis software. waitOne feePaid = 0 openGate = 0
print = 0
Synthesis transforms the abstract code of the desired done = 0
feePaid = 1
control path into a design implementation consisting of
requestFee = 0
logic gates. The Xilinx Design Suite and this process ensure validateFeePaid = 1
validateFee openGate = 0
that the syntax of the generated VHDL code matches the print = 0
done = 0
VHDL reference manual.
Figure 17 shows the entity of a car park system used to requestFee = 0
validateFeePaid = 0
collect payments from drivers who park their cars in a waitTwo feeValid = 0 openGate = 0
print = 0
parking lot. The system first asks the user to pay the done = 0

commission and then checks the paid commission. After feeValid = 1

requestFee = 0
paying the fee, the system prints out a ticket allowing the validateFeePaid = 0
printTicket openGate = 0
driver to park in the parking lot. Once the driver takes the print = 1
done = 0
ticket, the gate opens and waits until the entry time expires
before closing again. The object name for this car parking requestFee = 0
validateFeePaid = 0
ticketError = 1 waitThree ticketTaken = 0 openGate = 0
print = 0
clk
done = 0

RESET reset requestFee ticketTaken = 1

start requestFee = 0
validateFeePaid
feePaid validateFeePaid = 0
liftGate timeExpired = 0 openGate = 1
feeValid CarParkSystem openGate print = 0
done = 0
timeExpired
print timeExpired = 1
ticketTaken
requestFee = 0
ticketError validateFeePaid = 0
done
doneState openGate = 0
print = 0
done = 1

Figure 17. Test Case 1 Car Park System Entity Diagram Figure 18. Test Case 1 State Diagram

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used because it tests the project's maximum ten-state has reached in their ControlPath generation process.
requirement. The data from the state chart will be entered Figure 20 shows the entity code that was generated when
into the VHDL ControlPath Code Generator to verify that it the "Finish" button in the Entity Generation panel was
meets the requirements of the system. clicked. This button only becomes enabled when,
Figure 19 shows the object generation window of the VHDL ·There were valid entity and architecture names in the
ControlPath code generator. This "Entity Generation" edit fields
controller panel, which the user must interact with, is
visible in the leftmost panel of the program's main
window. Only alphabetic text can be entered in the "Entity
Name", "Architecture Name", "Clock Port Name", "Reset
Port Name" and "New Port Name" fields. The user must first
enter valid inputs for the clock port name and reset port
name fields. Valid inputs are indicated by the adjacent
light, which lights up green. Invalid entries are indicated by
a red lamp next to the field in which text is being entered.
The direction drop-down list is used to specify the direction
of each port in or out. The user can then interact with the
destination dropdown, add a port, and remove the last
port buttons. To generate the code for the designed
object, the user needs to click the "Finish button." The
panel displayed at the left-most section of this window
changes depending on the generation step that the user Figure 20. Example of Generated Entity Code

Figure 19. Entity Generation Window for Test Case 1

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·There were at least three inputs inclusive of the reset Within this window, the user inputs alphabetic text within
and clock ports the provided text fields to name their state machine and
·There was at least one output port. the corresponding signal and process names for the
ControlPath. Afterward, users can input the desired state
Figure 21 shows the state machine, signal, and process
names, along with state loops and transition logic. The
naming windows through which the data required for the
state diagram displays each state using a circle. It also
architecture to be generated as input. Before the "Finish"
displays transition points by using arrows pointing to other
button could be enabled, each text edit field had to only
states. Inside each circle, there are state labels. On the
contain unique and non-VHDL reserved words. Figure 22
right side of each state, output labels indicating which
shows the architecture generation window.

Figure 21. State Machine, Signal and Process Names Window (First Architecture Generation Step)

Figure 22. State Enumeration Window (Second Architecture Generation Step)

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outputs are high and low for each state are stated. These table. Once the finish button was clicked, the ControlPath
labels are only visible when the toggle switch is in the View .vhd file was generated. The ControlPath .txt file is also
Details mode. Once the user has entered a state's updated with the new data. The generated .vhd file was
required information, then click on the "Add State" button then imported directly into Xilinx ISE, where the ControlPath
to add the state to the state table or remove the last state was synthesized. The copy button also worked by copying
added from the table. Figure 22 shows the generated the code directly from the "Generated VHDL Code
state diagram when the toggle is switched into the View All (Preview)". This provides developers with multiple options
mode. This toggle allows the user to zoom out to see all of for exporting the code into an IDE where the user can work
the states in the designed ControlPath at the trade-off of on it further or simulate it.
state details. All labels are replaced with state numbers Figure 24 shows the generated architecture code for the
from the state table to give the user a quick idea of which test case. The architecture code begins on line 22 and
state the user looking at. To regain all of the state details on then continues down. Line 24 shows the state names
the diagram, the user must click on the view toggle being listed within the brackets of the "defaultFsm" state
located at the bottom right of the state diagram window. machine. Line 26 shows the definition of the present state
All of the entered state data for test case one was stored in signal named "pstate" and the next state signal named
the state table seen on the left of the "State Enumeration" "nstate". These signal names were the default names
window. provided by the GUI to the user. Lines 31-38 are the
Figure 23 shows the output logic process generation step clocking process, and the next state logic process begins
of the Architectural Generation. In this step, the name of on line 40 and continues further on. The inputs that the user
the desired output logic process was entered. Outputs entered into the GUI are all stated within the brackets of
that were required to go high were ticked in the state line 40. The GUI was able to generate the code with

Figure 23. Final Step in Architectural Generation (Output Logic Process)

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Figure 24. Test Case 1 Generated ControlPath Code Showing Clocking and Next State Logic Processes (Architecture Begins)

indentations and spacing to improve the readability of logic are high simultaneously, the next state will be the
the code for the end-user. The lines of code with two internal exit logic's next state and not the secondary exit's
consecutive dashed lines followed by text were VHDL state.
comments. These comments are not functional, so the Figure 26 shows the code generated from the output
user only serves to inform the developer of what the block logic process step after clicking the finish button. At this
of code underneath may be doing. This code represents step, the text file containing all the ControlPath code
the beginning of the architectural generation process. generated up until this point should be updated. The text
Figure 25 shows lines 77-86 show how the internal exit (.txt) file is named after the entity inputted at the first step of
logic "ticketTaken" and secondary exit logic "ticketError" of the ControlPath generation process, with ".txt" appended
the "waitThree" state were accounted for using "if" and to it. The ControlPath virtual hard disk (.vhd) file is similar but
"elseif" statements. These statements checked the with "_ControlPath.vhd" appended to it. Figure 27 and
respective exit logic and assigned the next state Figure 28 show the case statements of the output logic
according to the following, process. High outputs are assigned the std_logic value of
·If internal exit logic and secondary exit logic are both '1' and low outputs are assigned the value of '0'.
'0', the next state signal is the present state value. Figure 29 shows the "VHDL Testbench" window for Test
·If internal exit logic is '0' and secondary exit logic is '1', Case 1. It shows the generated VHDL testbench code in
the next state signal is the second exit state value. the "VHDL Testbench Code (Preview)" text area. This code
can be copied to the clipboard by clicking on the "Copy"
·If internal exit logic is '1' and secondary exit logic is '0',
button located directly under the text area. The code can
the next state signal is the next state in the table.
also be obtained from the generated testbench text file
·Else next state is the next state in the table.
named after the entity with "_testbench.txt" appended to
Note that if both the internal exit logic and secondary exit

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Figure 25. Test Case 1 Generated Next State Logic Code

Figure 26. Test Case 1 Generated Output Logic Process Begins Figure 27. Test Case 1 Output Logic Process

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developers to check to see if they entered the correct

information in the previous steps prior to generating their
final ControlPath and testbench files. Users are not able to
edit any of the information entered into the GUI at this
point as the code has already been generated. The
generated VHDL testbench can then be placed on Xilinx
ISE and used for simulation using ISim.
Figure 30 shows the waveforms produced by the
ControlPath VHDL Code Generator's testbench file when it
is simulated within ISim. All input ports, output ports, and
states are shown on this diagram. The clock period
"clk_period" of 10 ns is also shown here. From Figure 30, it
can be seen that when reset goes high, the ControlPath is
initiated as the present state signal "pstate" switches to
Figure 28. End of Generated Architecture Code (Architecture Ends)
"resetstate". The ControlPath then enters the "idle" state as
it. Alternatively, the generated testbench .vhd file can be seen by the pstate becoming "idle" at 215 ns. The next
directly imported into Xilinx ISE. The VHDL Testbench code state signal "nstate" is assigned the state "startfee" at 230
generated in this step can be seen in Figures (30) to (33). ns when "start" is set to '1'. When the next rising edge of the
This GUI allows users to navigate back to the previous steps clock "clk" occurs at 235 ns, "pstate" is assigned the value
of the ControlPath creation process via the "Previous" that "nstate" has, which in this case is "startfee".
button or the main menu located at the top. This allows When "pstate" is assigned the value of "startfee",

Figure 29. Test Case 1 VHDL - Testbench Window

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Figure 30. ISim simulation of the Generated VHDL Testbench of Test Case 1 (First Section)

"requestfee" goes to '1' as that was the output logic go to '1' at 275 ns. "printticket" has no internal loop,
process contained. Since the "startfee" state does not therefore "nstate" is immediately assigned the value of
have internal looping, "nstate" is assigned to "waitone" "waitthree" once this state is entered. On the next rising
immediately upon the ControlPath entering the "startfee" edge of the clock at 285 ns, "print" goes to '0' as "pstate" is
state. The "waitone" state has internal looping; therefore, assigned the next state value of "waitthree".
"nstate" remains as "waitone" until the internal exit logic Figure 25 shows that the "waitthree" state contains an
"feepaid" goes to "1" at 250 ns. Since "feepaid" became internal loop and a secondary exit. The ControlPath VHDL
'1', "nstate" is instantly assigned the next state value of Code Generator is programmed to toggle the secondary
"validatefee". The "pstate" value then changes to exit logic of a state before the internal exit logic to ensure
"validatefee" at the next rising edge of the clock at 255 ns. that all exits are tested. In Figure 31, at 290 ns, the
Once the ControlPath is in the "validatefee" state, "ticketerror" input goes to '1', causing "nstate" to be
"validatefeepaid" goes to '1'. "nstate" is immediately assigned the "waitthree" state's secondary exit of
given the value of "waittwo" as "validatefee" does not loop "validatefee". On the next rising edge of the clock at 295
internally. Since the clock period is 10 ns, the ControlPath ns, "pstate" is assigned the next state value of
only stays in the "validatefee" state for 10 ns before "validatefee", causing the "validatefeepaid" output to go
switching to "waittwo" at 26.5 ns. to "1" for 10 ns. At 305 ns, the next rising edge occurs,
According to Figure 25, once the ControlPath is in the causing the state to switch to "waittwo" again.
"waittwo" state, all outputs are set to "0", hence there is no According to Figure 32, since all inputs that have been
output. According to the car park system's state diagram, toggled to "1" stay as '1' in this testbench, no internal
the "waittwo" state loops internally. As such, "nstate" looping occurs for "waittwo" or any of the previous states
remains as "waittwo" until the "waittwo" state's internal exit checked. This results in "nstate" being immediately
logic "feevalid" goes to "1", as seen at 270 ns in Figure 31. assigned the value of "printticket". On the next rising edge
When "feevalid" goes to '1', "nstate" is given the value of of the clock at 315 ns, "pstate" is given the "nstate" value of
"printticket". On the next rising edge of the clock, "pstate" is "printticket", causing the "print" output to go to '1' for 10 ns.
given the value of "printticket", making the "print" output At 325 ns, "pstate" is assigned the value of "waitthree",

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Figure 31. ISim simulation of the Generated VHDL Testbench of Test Case 1 (Second Section)

Figure 32. ISim simulation of the Generated VHDL Testbench of Test Case 1 (Third Section)

whose secondary exit has just been tested. This time, at "timeexpired" goes to '1'. This occurs at 340 ns, causing
330 ns, the "tickettaken" input is set to '1', changing the "state" to be assigned the "donestate" state value. On the
"nstate" value to "liftgate". next rising edge of the clock at 345 ns, "pstate" is assigned
On the next rising edge of the clock at 335 ns, the present the "nstate" value of "donestate". This causes the "done"
state becomes "liftgate", causing the "opengate" output output to go to "1" for 10 ns. Since the end of the
to go to "1". The "liftgate" state internally loops, therefore ControlPath has been reached, at 355 ns, the
"nstate" remains as "liftgate" until the internal exit logic ControlPathloops to the "idle" state at the beginning of the
ControlPath, continuously cycling through all states as all

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internal exit logic have been set to '1'. developed GUI. Ten of these students filled out the GUI
Figure 33 shows the continuous cycling through the ten Beta Testing Questionnaire. The survey aimed to gather
states of the car park system since all of the internal exit data on students' understanding of VHDL and their skill
logic has been set to '1'. This is indicated by the "pstate" level with respect to ControlPath VHDL implementation. Of
and "nstate" values changing every 10 ns. the total sample size of 13 students, 15% were fourth-year
students, 23% were second-year students, and 62% were
5. Discussion
third-year students. Prior to the students' testing the
The latest version of the ControlPath VHDL Code
software, each was given a questionnaire to fill out. The
Generator consists of four major views split up among five
questionnaire mainly sought to gather data about the
different UI panels. These views were the EntityView,
effectiveness of the GUI with regard to the system
A r c h i t e c t u r e V i e w, S t a t e D i a g r a m V i e w, and
requirements. The students were provided with a
TestbenchView. The EntityView consisted of the Entity
standalone executable of the ControlPath VHDL Code
Generation panel. The ArchitectureView consisted of the
Generator. This removed the need for students to have
"State Machine, Signal, and Process Names" panel, the
MATLAB installed on a system to run the software.
"State Enumeration" panel, and the "Output Logic
Some students that attempted to beta test the graphical
Process" panel. The StateDiagramView was also split
user interface indicated that the standalone executable
among the Entity window, StateEnumeration window, and
required MATLAB runtime files to be installed prior. These
OutputLogicProcess window. The TestbenchView only
students were provided an installer executable that
consisted of the fifth panel in the GUI, which was the "VHDL
installed the MATLAB necessary runtime files and the
Testbench" panel.
ControlPath VHDL Code Generator standalone desktop
This version of the GUI was used to conduct system and
executable.
acceptance testing using students under the
The ControlPath VHDL Code Generator functions in
Department of Electrical and Computer Engineering at
accordance with the system requirements, where it
the University of the West Indies, St. Augustine Campus. The
successfully generates the ControlPath VHDL code for test
students who were previously contacted for the data-
case 1, designed using the GUI. The state diagram was
gathering survey were invited back to beta test the

Figure 33. ISim simulation of the Generated VHDL Testbench of Test Case 1 (Fourth Section)

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also generated with the design of the ControlPath. The "EntityGenerationInputs", "StateMachineSignalAnd
ControlPath VHDL Code Generator can also create a ProcessNamesInputs", "StateEnumerationInputs",
ControlPath consisting of more than 10 states, surpassing "OutputLogicProcessInputs" and "VHDLTestbenchInputs".
the max state requirement of the system. The GUI After the data was bound by the controller, it was then
successfully created ControlPath VHDL code for the passed to the model, which interpreted the data and
designed system. This code included the successful updated the State Diagram and VHDL Code Previews or
generation of the Entity, Architecture, State Diagram, Views accordingly. This is seen in Figure 6, where the
State Declaration, State Transition Process, Next State model consists of the "EntityModel", "ArchitectureModel",
Logic Process, and Output Logic Process. and "TestbenchModel" and interacts with the Controller
The designed ControlPath VHDL Code Generator was built via "DataBinding" and "Responses". Within the MVC, there
primarily as a passive code generator using MATLAB App were more detailed interactions between
Designer. This template allowed users to export the subcomponents of the models. This can be seen in the
generated code for further work in an IDE such as Xilinx ISE. Entity Relationship Diagram in Figure 7. The MVC aided in
The passive code generator design helped mitigate risks the successful creation of the ControlPath VHDL Code
when developing the GUI because active code Generator.
generators require an active link to be maintained with Conclusion
the code file, whereas passive code generators do not. The development of a ControlPath VHDL Code Generator
The Model View Controller architectural pattern and the V- for digital electronic units resulted in the design and
model software development life cycle were utilized to implementation of a graphical user interface capable of
ensure that the developed software was reliable. VHDL code generation. The graphical user interface was
Extensive unit, integration, system, and acceptance constructed as a standalone desktop executable using
testing were all done to ensure that the developed the MVC pattern, where the V-model software
solution satisfied the system requirements. For the unit and development life cycle model was used. A
integration testing, 10 test cases were input into the developmental survey was conducted, and the results
developed GUI, and the output was observed for errors. show that most students possess a moderate
For the system and acceptance testing, several students understanding of VHDL and find it slightly challenging to
tested the GUI and provided feedback via the implement. This gap between understanding and
questionnaires that were distributed. This development implementation shows the need for a tool such as the
and testing method as shown in Figure 10 ensured that ControlPath VHDL Code Generator. This tool aids students
the developed user interface and user experience were in the process of designing digital logic systems with a
satisfactory, allowing users to intuitively use the software minimal understanding of VHDL. The results show that after
without much prior knowledge of VHDL or ControlPaths. students used the ControlPath VHDL Code Generator to
The developed ControlPath VHDL Code Generator design a system using a ControlPath diagram, the results
followed the Model View Controller architectural pattern show that there was a decrease in the difficulty of the
(Figure 6). This segmented the development of the GUI ControlPath generation process.
into three main components called the Model, View, and There were several limitations in the development of the
Controller. The views of this GUI were the "EntityView", ControlPath VHDL Code Generator. First, the completion
"ArchitectureView", "StateDiagramView", and the of the system resulted in limited space being available for
"TestBenchView". These views consisted of the front-end UI the viewing of diagrams. A compromise had to be made
that users were presented with and had to interact with. between viewing full details of all states versus seeing an
The data that was entered on each view was then overview of the entire state diagram with simplified
handled by the controller. The Controller consisted of the details. The result was a "View Details" and "View All" toggle

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 RESEARCH PAPERS

which allows the user to see the full details of some states Previous project data can be reloaded if a system is
at a time when on "View Details". The user can also pan finished but adjustments are needed. This loading
around the diagram to view other states. When on "View capability is implemented into the system where the state
All", the panning is disabled and all of the state names, diagram, port table data, state table data, and VHDL
transitions, loops, and secondary exit text are removed, code are regenerated based on the saved data. The user
being replaced by the state number, which is situated in data can be saved in a text (.txt) file format and read into
the centre of each state circle. This allows users to the GUI using a load algorithm. The data can also be
reference the state numbers in the state table encrypted to prevent the ControlPath from being
corresponding to the states on the state diagram. There is tampered with or corrupted by an external editor.
also no maximum limit to the number of input ports, References
output ports, and states that the user may add to their
[1]. Areno, M. C. (2007). Automated Constraint-Based
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Hardware Architecture Generation For Reconfigurable
prevent generated ControlPaths from not being
Computing Systems. Utah State University.
functional. The second limitation was that the
[2]. Davis, B. (2018). Is VHDL easy to learn? Retrieved from
implemented system was only designed for desktops and
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laptops using Windows as the operating system. This
[3]. Franky, M. C., & Pavlich-Mariscal, J. A. (2012,
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method to save the generated state diagram as a picture Dabhade, R. G. (2009). Modeling and simulation of FPGA
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before allowing a user to add the string data to memory. Languages and Systems (pp. 213-227). Springer, Berlin,
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still adhering to the VHDL Reference Manual. Third, future Experiments with Code Generation from the UML Class
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ABOUT THE AUTHORS

Marcus Lloyde George received the P.hD, MPhil, and B.Sc degrees in Electrical and Computer Engineering from the University
of the West Indies, St. Augustine Campus, in the years 2019, 2011, and 2007 respectively. He is the author of several academic
books. Some of his technical and scientific interests are Business Administration, Strategic Planning and Management,
Engineering Education, Formal Specifications, Modeling and Verification, Field-Programmable Architectures, Intelligent
Electronic Devices, and Biomedical Engineering.

Brandon Joseph received his B.Sc degree in Electrical and Computer Engineering from the University of the West Indies, St.
Augustine in 2022 and is a former research student of Marcus Lloyde George.

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prohibited without permission.