Sata Interface White Paper 091605
Sata Interface White Paper 091605
Sata Interface White Paper 091605
Serial ATA has emerged as the industry standard internal storage interface designed to solve the bandwidth constraints of Parallel ATA, as well as well as the dependence on 5V signaling lines that are incompatible with silicon processes used in a wide variety of microprocessors. Serial ATA overcomes these issues by employing a 250mV differential signaling method. Differential signaling rejects induced noise. The 250mV differential signal level is compatible with future microelectronic fabrication processes. Forecasts indicate ATA dominance ATA is the dominant HDD interface in the industry. The ATA interface market is expected to be approximately 190 million units in 2003, accounting for about 90% of all HDDs shipped, according to International Data Corporations (IDC) 2002/03 forecasts. By 2006, IDC projects ATA unit shipments will increase to beyond 310 million and continue to account for 90% of all HDDs shipments. It is clear that the market will demand ATA-class HDDs for the foreseeable future. Serial ATA standards activities The Serial ATA Working Group published the Serial ATA 1.0a specication in 2003, which was in turn adopted by the ANSI T13 public standards committee as the ATA/ ATAPI-7 V3 specication. In 2004, the Serial ATA Working Group evolved into a formal organization called the Serial ATA International Organization (SATA-IO), dedicated to sustain the specication and create further SATA-based interface solutions. The pioneering work instigated by the
Serial ATA Topology
Operating System
Application 1
Application 1
Application 2
Application 2
Driver
Application 3
Disk
Disk
Application 3
Disk
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Link layer The Link layer is responsible for sending and receiving frames, control signal primitives and performing ow control. The Link layer contains a primitive character encoder/ decoder, 8B/10B encoder/decoder, 32-bit CRC calculator, data scrambler/descrambler and a layer controller. Transport layer The Transport layer handles the packing and unpacking of ATA and ATAPI information into Frame Information Structures. The Transport layer also manages the FIFO or buffer memory for controlling data ow.
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