IEEE SOLID-STATE CIRCUITS SOCIETY

NEW THIS YEAR:

2012 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE

FEBRUARY 19, 20, 21, 22, 23

CONFERENCE THEME:

ADVANCE PROGRAM

SILICON SYSTEMS FOR SUSTAINABILITY

9 TUTORIALS on RF mixers, Flash-memory, mobile GHz processors, wideband delta-sigma, jitter,

SAN FRANCISCO MARRIOTT MARQUIS HOTEL

5-DAY PROGRAM

DEMOS EXTENDED TO AN ACADEMIC DEMONSTRATION SESSION (ADS)

SUNDAY ALL-DAY

2 FORUMS on RF beamforming, and green circuit design

THURSDAY ALL-DAY
4 FORUMS on data communications, computational imaging,
biolectronics, and many-core SoC optmization

integrated voltage regulators, digital calibration for RF, offset and flicker noise, and MEMS

2 EVENING EVENTS on graduate student research in progress, and smarter robotics

A SHORT-COURSE on low-power analog signal processing

ISSCC VISION STATEMENT

The International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts.

CONFERENCE TECHNICAL HIGHLIGHTS

On Sunday, February 19th, the day before the official opening of the Conference, ISSCC 2012 offers: A choice of up to 4 of a total of 9 Tutorials A choice of 1 of 2 Advanced-Circuit-Design Forums The 90-minute tutorials offer background information and a review of the basics in specific circuit-design topics. In the all-day Advanced-Circuit-Design Forums, leading experts present state-of-the-art design strategies in a workshop-like format. The Forums are targeted at designers experienced in the technical field. On Sunday evening, there are two events: A Special-Topic Session entitled, Whats Next in Robots?..... will be offered starting at 8:00pm. In addition, the Student Research Preview, featuring short presentations followed by a poster session from selected graduate-student researchers from around the world will begin at 7:30 pm. A distinguished circuit designer, Professor Willy Sansen will provide introductory remarks at the Preview. On Monday, February 20th, ISSCC 2012 offers four plenary papers on the theme: Silicon Systems for Sustainability. On Monday at 12:15 pm, there will be a Womens Networking Event, a luncheon. On Monday afternoon, there will be five parallel technical sessions, followed by a Social Hour open to all ISSCC attendees. The Social Hour held in conjunction with the Book Display will also include the Academic Demonstration Session (ADS), featuring posters and live demonstrations for selected papers from universities. Monday evening features a panel discussion on Is RF Doomed to Digitization?.., as well as two SpecialTopic Sessions on Technologies that Could Change the World.., and Optical PCB Interconnects... On Tuesday, February 21st, there are five parallel morning and afternoon technical sessions. A Social Hour open to all ISSCC attendees will follow. The Social Hour held in conjunction with the Book Display will include the Industrial Demonstration Session (IDS), featuring posters and live demonstrations for selected papers from industry. Tuesday evening sessions include two evening panels on Little-Known Features of Well-Known Creatures, and What is the Next RF Frontier?, as well as one Special-Topic Session on Vision for Future Television. On Wednesday, February 22nd, there will be five parallel sessions morning and afternoon. On Thursday, February 23rd, ISSCC offers a choice of five events: A Short Course on Low-Power Analog Signal Processing Four Advanced-Circuit-Design Forums on high-speed data communications, computational imaging, bioelectronics, and many-core SoC optimization Registration for educational events will be filled on a first-come, first-served basis. Use of the ISSCC Web-Registration Site (http://www.isscc.org) is strongly encouraged. Registrants will be provided with immediate confirmation on registration for Tutorials, Advanced-CircuitDesign Forums, and the Short Course.

Need Additional Information?

Go to: www.isscc.org
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TABLE OF CONTENTS
Tutorials .........................................................................................4-6 F1 F2 ES1 ES2 FORUMS Beamforming Techniques and RF Transceiver Design..........................................7 Robust VLSI Circuit Design and Systems for Sustainable Society .......................8 EVENING SESSIONS Student Research Preview ...................................................................................9 Whats Next in Robots? ~ Sensing, Processing, Networking Toward Human Brain and Body .................10 PAPER SESSIONS Plenary Session............................................................................................11-14 High-Bandwidth DRAM & PRAM .......................................................................15 Processors.........................................................................................................16 RF Techniques....................................................................................................17 Audio and Power Converters .............................................................................18 Medical, Displays and Imagers ..........................................................................19

1 2 3 4 5 6

Acadamic Demonstration Session................................................................................20 ES3 ES4 EP1 EVENING SESSIONS Technologies that Could Change the World You Decide!..................................21 Optical PCB Interconnects, Niche or Mainstream?.............................................22 Is RF Doomed to Digitization? What Shall RF Circuit Designers Do? ...............................................................22 PAPER SESSIONS Multi Gb/s Receiver and Parallel I/O Techniques ................................................23 Delta-Sigma Converters .....................................................................................24 Wireless Transceiver Techniques .......................................................................25 High-Performance Digital...................................................................................26 Sensors & MEMs ...............................................................................................27 Multimedia & Communications SoCs ................................................................28 High-Performance Embedded SRAM.................................................................29 Digital Clocking & PLLs .....................................................................................30 mm-Wave & THz Techniques .............................................................................31

7 8 9 10 11 12 13 14 15

Conference Timetable ......................................................................32-33 16 17 Switching Power Control Techniques.................................................................34 Diagnostic & Therapeutic Technologies for Health.............................................35

Industry Demonstration Session ..................................................................................36 ES5 EP2 EP3 18 19 20 21 22 23 24 25 26 27 28 EVENING SESSIONS Vision for Future Television................................................................................37 Little-Known Features of Well-Known Creatures ................................................38 What is the Next RF Frontier? ............................................................................38 PAPER SESSIONS Innovative Circuits in Emerging Technologies....................................................39 20+Gb/s Wireline Transceivers & Injection-Locked Clocking .............................40 RF Frequency Generation ...................................................................................41 Analog Techniques .............................................................................................42 Image Sensors...................................................................................................43 Advances in Heterogeneous Integration.............................................................44 10GBASE-T & Optical Frontends........................................................................45 Non-Volatile Memory Solutions .........................................................................46 Short-Range Wireless Transceivers ...................................................................47 Data Converter Techniques ................................................................................48 Adaptive & Low-Power Circuits .........................................................................49 SHORT COURSE Low-Power Analog Signal Processing ..........................................................50-51 F3 F4 F5 F6 FORUMS 10-40 Gb/s I/O Design for Data Communications ..............................................52 Computational Imaging......................................................................................53 Bioelectronics for Sustainable Healthcare ..........................................................54 Power/Performance Optimization of Many-Core Processor SoCs......................55

Committees..............................................................................................................56-60 Conference Information...........................................................................................61-63

TUTORIALS
T1: RF Mixers: Analysis and Design Trade-offs

Sunday February 19th

Mixers are essential building blocks of every RF transceiver, often compromising the noise and linearity performance of the entire receive or transmit chain. Specifically, the switching action involved in mixing typically dictates the choice of the radio architecture and proper frequency planning to avoid the receiver desensitization. In this tutorial various mixer architectures such as passive and active, current-mode and voltage-mode, and their properties are analyzed and discussed. Of special importance is the noise response of mixers, which is not very well understood due to the nonlinear and time varying nature of the block, and the fact that conventional linear noise analysis applicable to amplifiers often does not hold. We will focus on intuitive and qualitative ways of analyzing the noise of both passive and active mixers as well. Instructor: Hooman Darabi Hooman Darabi received the BS and MS degrees both in Electrical Engineering from Sharif University of Technology, Tehran, Iran, in 1994, and 1996, respectively. He received the Ph.D. degree in electrical engineering from the University of California, Los Angeles, in 1999. He is currently a Sr. Technical Director and a Fellow with Broadcom Corporation, Irvine, CA, as a part of the mobile and wireless group. His interests include analog and RF IC design for wireless communications. Dr. Darabi holds over 170 issued or pending patents with Broadcom, and has published over 50 peer-reviewed journal and conference papers.

T2: Flash-Memory Based Circuit, System, and Platform Design

Applications using flash memory are rapidly increasing in number. Different applications of flash memory demand various Circuit, System, Software and Platform Co-Design to optimize usage. Even for a given application these tradeoffs should be considered. Unlike tutorials on flash memory in the past that mostly focus on circuit design, this tutorial will consider System, Software, and Platform Design from the application perspective. The tutorial will also be of interest to the broader audience with interests beyond memory field. Instructor: Mark Bauer Mark Bauer is a Fellow at Micron working in the NAND Solutions Group where he is responsible for the vertical integration of Non Volatile Memory and memory systems. He joined Micron in 2010 as part of the Numonyx aqusition. Prior to Micron he spent three years at Numonyx on advanced Phase Change Memory designs in technology. From 1985 to 2008 he worked at Intel developing EPROM, NOR Flash, NAND Flash and Phase Change Memory designs. He holds more than 30 US Patents, has published numerous technical papers in the field of Non Volitile Memory, has been an invited speaker at technical conferences, served on the ISSCC Memory Technical Program Committee for 11 years and is currently on the VLSI Symposium Technical Program Committee. He recieved the BSEE from the University of California in 1985.

T3: Mobile GHz Processor Design Techniques

Mobile computing devices such as smart-phones and smart-pads open up new challenges in mobile processor designs in terms of their speed and power targets. Mobile processors are getting more powerful in order to run increasingly complex software. Therefore, the design of high-speed low-power mobile processors is becoming the major challenge. In this tutorial, design techniques for high-speed mobile CPU and GPU are discussed at several design levels. The talk will go through the architecture, circuit, device level optimization and also consider chip-wise power management techniques. Special considerations for cost-effective microarchitectures, high-speed logic, low-power arithmetic, and DVFS will be highlighted. Instructor: Byeong-Gyu Nam Byeong-Gyu Nam received his Ph.D. degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2007. His Ph.D. work focused on low-power GPU design for mobile devices. From 2007 to 2010, he was with Samsung Electronics, Giheung, Korea, where he worked on the worlds first low-power 1-GHz ARM microprocessor design. Dr. Nam is currently with Chungnam National University, Daejeon, Korea, as an assistant professor. His current interests include mobile GPU, embedded CPU, lowpower SoC, and their associated SW platforms. He is serving as a program committee member of the IEEE ISSCC, A-SSCC, COOL Chips, and VLSI-DAT.

TUTORIALS
T4: Wideband Delta-Sigma Modulators

Sunday February 19th

The application space of delta-sigma analog-to-digital converters has been greatly extended during the last few decades with applications ranging from traditional applications such as audio and hearing aids that require only a few (tens of) kHz bandwidth to a multitude of cellular standards that need up to 40MHz bandwidth. To enable this bandwidth range of four orders of magnitude, new innovative wideband delta-sigma architectures and circuits have been developed that operate at GHz rate sampling frequencies. This tutorial gives an introduction to the system design and implementation of wideband delta-sigma modulators. A review of wideband delta-sigma architectures, loop stability, filter implementations and circuit designs is presented. Some case studies illustrate wideband delta-sigma modulators that have bandwidths in the range from several tens of MHz to beyond 100MHz. Instructor: Lucien Breems Lucien Breems received the M.Sc. degree and the Ph.D. degree in Electrical Engineering from the Delft University of Technology, The Netherlands, in 1996 and 2001, respectively. From 2000 to 2007 he was with Philips Research, Eindhoven the Netherlands and in 2007 he joined NXP Semiconductors where he currently leads a team working on delta-sigma A/D converters. Since 2008, he has been a lecturer at the Delft University of Technology on the topic of deltasigma modulation and since 2011 he is a part-time Professor at the Eindhoven University of Technology. His research interests are in the field of mixed-signal circuit design. In 2001, he received the ISSCC Van Vessem Outstanding Paper Award.

T5: Jitter: Basic and Advanced Concepts, Statistics, and Applications

Jitter and phase noise are key factors that deeply impact the performance of circuits in modern communication applications. Within the industry, many types of jitter must be and are considered, including cycle-to-cycle, accumulated, deterministic, random, total, absolute, integrated, TIE, and more. Understanding the implications of each of these jitter types demands clear jitter term definitions as well as a common understanding of their practical meaning. In response to this need, this tutorial will presents basic and advanced concepts of jitter. The first part of the tutorial will focus on jitter definitions, statistics, and the relationship of jitter to phase noise. The second part of the tutorial will explore the impact of jitter on a variety of applications, drawing on examples from wireline as well as other technical areas. The overall goal of the tutorial is to provide a solid understanding of what jitter is, how to correctly specify it, and to enhance understanding of jitter specifications for different applications. Instructor: Nicola Da Dalt Nicola Da Dalt received the Master degree from University of Padova, Italy, in 1994 and the PhD degree from RWTH Aachen, Germany, in 2007, both in Electronic Engineering. From 1996 to 1998 he was with Telecom Italia, Italy, as concept engineer for architectures and synchronization of data transmission networks and satellite communications. Since 1998 he has been with Infineon Technologies, Austria, as an IC design and concept engineer for clock systems in applications ranging from wireline, to memory and wireless. Since March 2005 he leads the Clocking and Interface Systems group. He received the 2010 IEEE Guillemin-Cauer Best Paper Award. He holds four granted patents and is the author of several publications in conferences and journals.

T6: Power Management Using Integrated Voltage Regulators

Aggressive technology scaling has enabled very high levels of transistor integration. Managing total power consumption has emerged as the most challenging task in todays highly complex microprocessor systems. In this tutorial, we will review power management techniques implemented in recent designs. Independent per-core dynamic voltage scaling is proven to be an effective way to minimize power consumption. Due to the size and routing planes, the number of independent platform rails is limited to a very small number. Near-load voltage regulators provide a practical solution. This tutorial includes a survey of recent innovations in near-load voltage regulators. Instructor: Tanay Karnik Tanay Karnik is Principal Engineer and Program Director in Intel Labs Academic Research Office. He received his Ph.D. in Computer Engineering from University of Illinois at UrbanaChampaign in 1995. His research interests are in the areas of variation tolerance, power delivery, soft errors and physical design. He has published 50 technical papers, has 44 issued and 33 pending patents. He received an Intel Achievement Award for the pioneering work on integrated power delivery. Tanay was the General Chair of ASQED10, ISQED09, ISQED08 and ICICDT08. Tanay is IEEE Senior Member, Associate Editor for TVLSI and Guest Editor for JSSC.

TUTORIALS
T7: Digital Calibration for RF Transceivers

Sunday February 19th

Designing high-precision RF transceivers in deep submicron technologies is increasingly challenging due to reduced supply headroom, non-linearities of transistors, and large process parameter spread. By taking advantage of the cheaper and faster digital computing power, digital calibration is becoming an increasingly common practice to overcome such challenges and enhance transceiver performance. Calibration techniques covered include I/Q mismatch calibration, DC offset and LO leakage removal, closed-loop power control and envelope tracking, analog filter response calibration, digital pre-distortion for PAs, and antenna tuning. The tutorial will also cover DSP methods and algorithms and provide specific examples of digitally calibrated transceivers. Instructor: Albert Jerng Albert Jerng received his BSEE, MSEE from Stanford University, and his PhD EE from MIT in 1994, 1996, and 2006, respectively. While at MIT, he conducted research on CMOS VCO design and digital TX architectures for Gb/s OFDM systems. Since 2007, he has been with Ralink Technologies as Sr. Director for Advanced Circuits and Systems working on Bluetooth and WiFi products, and is now employed as Deputy Director at Mediatek, responsible for the WiFi RF transceiver division, after their merger with Ralink. He is also serving as General Chair for the IEEE RFIC Symposium in 2012.

T8: Managing Offset and Flicker Noise

A large number of circuits require DC accuracy and low noise at low frequencies. Sensor interfaces are a good example, but comparators, ADCs, and many other blocks need it too. This tutorial will provide a review of techniques to achieve low offset and flicker noise. Techniques such as chopper stabilization, correlated double sampling, auto-zero, digital startup calibration, and digital background calibration will be reviewed. Implementation examples will be shown and noise and aliasing and other artifacts will be analyzed. Techniques to master these artifacts will be discussed. The ideas will then be taken into the mixed signal domain. Instructor: Axel Thomsen Axel Thomsen received his PhD from the Georgia Institute of Technology in 1992. He has held positions at the University of Alabama in Huntsville, University of Texas, and Cirrus Logic. Currently he is a Distinguished Engineer at Silicon Laboratories in Austin, TX. He has worked on chips for industrial measurement, timing, isolation and power applications. He has a strong interest in precision measurement. Currently he is working in the Embedded Mixed Signal Division on data converters and amplifiers. He holds more than 40 patents.

T9: Getting In Touch with MEMS: The Electromechanical Interface

MEMS systems include mechanical structures and electronic sense and drive circuits. Between these is an electromechanical interface, which can be capacitive, piezoresistive, piezoelectric, ferroelectric, electromagnetic, thermal, optical or can take some other form. The selection of this interface is the single most critical decision in the system definition, and it determines the eventual capabilities and limits of the device. The interface fundamentally sets the devices sensitivity, accuracy, drift, ageing, temperature behavior, and environmental capabilities. The interface determines the MEMS production technology and hence the fab selection, the cost structure, and the time to market. This tutorial examines and compares the available options and application drivers. Which interface technologies can be used? Why is one more suitable for a particular application than another? How do they scale? What is on the horizon? The goal is to expand the attendees potential role from circuit designer to system designer. From Here is the MEMS device, design the interface circuit. into Here is the problem, define an optimal solution. Instructor: Aaron Partridge Aaron Partridge received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from Stanford University, Stanford, CA, in 1996, 1999, and 2003, respectively. In 2004 he cofounded SiTime Corp. where he is Chief Science Officer. SiTime is the leading supplier of MEMS oscillators, resonators, and timing devices. From 2001 through 2004 he was Project Manager at Robert Bosch Research and Technology Center, Palo Alto, CA, where he coordinated the MEMS resonator research. He serves on the IEEE International Solid-State Circuits Conference IMMD subcommittee and is the Editorial Chair of the IEEE International Frequency Control Symposium.

FORUM
Organizers: Committee:

Sunday February 19th, 8:00 AM

F1: Beamforming Techniques and RF Transceiver Design
Eric Klumperink, University of Twente, Enschede, The Netherlands Domine Leenaerts, NXP Semiconductors, Eindhoven, The Netherlands Albert Jerng, Ralink, Jhubei, Taiwan Yorgos Palaskas, Intel, Hillsboro, OR Didier Belot, ST Microelectronics, Crolles, France

Phased arrays exploit electronic beamforming to create an electronically steerable beam pattern. This reinforces antenna gain in certain directions and reduces gain in others, i.e. spatial filtering. Until recently, phased-array systems exploited dedicated RF technologies leading to relatively costly systems, e.g. for nautical systems, airplane radar systems, and satellite communication. More recently, low-cost highly integrated beamforming concepts received considerable interest in academia but also industry, enabling consumer applications e.g. in base stations for macro- and femto-cells, car radar and 60GHz wideband radio links. (Bi-)CMOS beamforming techniques are at the heart of such systems. This forum reviews beamforming techniques suitable for IC integration, and discusses related (Bi-)CMOS transceiver designs. Several techniques will be discussed, e.g. RF phase shifting, LO phase shifting, I/Q vector modulation and digital processing. Also the relation between key radar and communication system requirements and transceiver IC requirements will be considered. Finally, trends and challenges will be discussed in a panel. Forum Agenda Time 08:00 08:30 09:00 09:30 10:00 10:30 11:15 11:45 1:00 1:45 2:15 2:45 Topic Breakfast Introductory Overview of Beamforming Gabriel Rebeiz, UC San Diego, LaJolla, CA S-Band Phased-Array Radar with 2-D Digital Beamforming Wim de Heij, THALES Nederland BV, Hengelo, The Netherlands SiGe BiCMOS Single-Chip Receiver for S-Band Phased-Array Radars Frank van Vliet, TNO, The Hague, The Netherlands Break Silicon RF Phased-Arrays at X-, Q-, W-Band and Beyond Kwang-Jin Koh, Virginia Tech, Blacksburg, VA Butler Matrix Beamforming Phased Arrays and CMOS Implementation Sheng-Fuh Chang, Chung Cheng University, Chiaya, Taiwan Lunch Silicon-Based Integrated Beamforming and On-Chip Radiators Ali Hajimiri, California Institute of Technology, Pasadena, CA Vector Modulation Techniques and Interference Nulling Jeyanandh Paramesh, Carnegie Mellon University, Pittsburgh, PA Break RF Beamforming and 60GHz BiCMOS Chipsets Scott Reynolds, IBM T.J. Watson Research Center, Yorktown Heights, NY Panel Discussion: Challenges for the future? Closing Remarks (Chair)

3:30 4:00

FORUM
Organizer/Chair: Co-Chair: Committee:

Sunday February 19th, 8:00 AM

Ken Takeuchi, University of Tokyo, Tokyo, Japan Jan Crols, AnSem, Heverlee, Belgium Ken Takeuchi, University of Tokyo, Tokyo, Japan Jan Crols, AnSem, Heverlee, Belgium Kevin Zhang, Intel, Hillsboro, OR Mike Clinton, Texas Instruments, Dallas, TX Tadaaki Yamauchi, Renesas Electronics, Itami, Japan

F2: Robust VLSI Circuit Design and Systems for Sustainable Society

Technology scaling brings new challenges to the design of reliable and robust VLSI circuits and systems challenges that arise at the system, circuit and device levels. This Forum provides an overview of such challenges, as well as overviews recent advances in the domain of reliable and robust VLSI systems. Topics covered include the fault-tolerance requirements for microcontrollers in automotive applications, recent trends in CMOS variability, design techniques for robust non-volatile and volatile memories, as well as directions for improving the robustness of analog, communications, and voltage regulator circuits and systems. Forum Agenda Topic Time 8:00 8:20 8:30 Breakfast Introduction Ken Takeuchi, University of Tokyo, Tokyo, Japan Future Development of Robustness and Fault Tolerance Requirements for Microcontrollers in Safety Relevant Automotive Applications Bernd Mller, Robert Bosch GmbH, Stuttgart, Germany Understanding CMOS Variability and Soft errors for Robust Circuit Design Hidetoshi Onodera, Kyoto University, Kyoto, Japan Break Robust SRAM Design in Nano-Scale CMOS: Circuit and Technology Yih Wang, Intel, Portland, OR Embedded Non-Volatile Memory Design for Highly Reliable Applications Takashi Kono, Renesas Electronics, Itami, Japan Lunch Dependable SSD Design Hiroshi Sukegawa, Toshiba, Yokohama, Japan Robust System Design: Overcoming Complexity and Reliability Challenges Subhasish Mitra, Stanford University, Stanford, CA Break Reliability Considerations in Deep Submicron Analog Circuit Design Terry Mayhugh, Texas Instruments, Richardson, TX Channel Coding in Wireless Martin Bossert, Ulm University, Ulm, Germany Voltage Regulator Circuits and System Energy Management Dave Freeman, Texas Instruments, Dallas, TX Conclusion

9:20 10:10 10:25 11:15 12:05 1:00 1:50 2:40 2:55 3:45 4:35 5:25

EVENING SESSIONS

Sunday February 19th, 7:30 PM

ES1: STUDENT RESEARCH PREVIEW (SRP)

The Student Research Preview (SRP) will highlight selected student research projects in progress. The SRP consists of 23 one-minute presentations followed by a Poster Session, by graduate students (Masters and PhDs) from around the world, which have been selected on the basis of a short submission concerning their on-going research. Selection is based on the technical quality and innovation of the work. This year, the SRP will be presented in three sessions: Analog, Mixed-Signal and RF Circuits; High-Performance Systems and Imagers; Techniques for Ultra-Low-Power Sensors. The Student Research Preview will begin with a brief talk by the distinguished circuit designer, Professor Willy Sansen, K.U. Leuven. His talk on careers in solid-state circuits is scheduled for Sunday,February 19th, starting at 7:30pm, and is open to all ISSCC registrants.

Chair: Co-Chair: Co-Chair:

Jan Van der Spiegel University of Pennsylvania Makoto Ikeda University of Tokyo, Japan Eugenio Cantatore Technical University Eindhoven, The Netherlands Secretary: SeongHwan Cho KAIST, Korea Advisor: Kenneth C. Smith University of Toronto, Canada Media/Publications: Laura Fujino University of Toronto, Canada A/V: John Trnka Rochester, MN

COMMITTEE MEMBERS
Bryan Ackland Bharadwaj Amrutur Bevan Baas Andrea Baschirotto Bill Bowhill Eugenio Cantatore SeongHwan Cho Denis Daly Vasantha Erraguntla Vincent Gaudet Makoto Ikeda Adreas Kaiser Takayuki Kawahara Shen-Iuan Liu Ko Makinwa Akira Matsuzawa Dejan Markovic' Shahriar Mirabbasi Boris Murmann Bing Sheu Sameer Sonkusale Jan Van der Spiegel Marian Verhelst Zhihua Wang Stevens Institute of Technology, USA IISC, India University of California, Davis, USA University of Milan-Bicocca, Italy Intel, USA Tech University Eindhoven, The Netherlands KAIST, Korea Cambridge Analog Technologies Intel, India University of Waterloo, Canada University. of Tokyo, Japan ISEN, France Hitachi, Japan National Taiwan University, Taiwan Tech. University Delft, The Netherlands Tokyo Inst. Tech., Japan UCLA, USA University of British Columbia, Canada Stanford University, USA TSMC, Taiwan Tufts University, USA University of Pennsylvania, USA Kath. University of Leuven, Belgium Tsinghua University, P.R. China

EVENING SESSIONS
ES2:

Sunday February 19th, 8:00 PM

Whats Next in Robots? ~ Sensing, Processing, Networking Toward Human Brain and Body
Kazutami Arimoto, Renesas Electronics, Itami, Hyogo, Japan Sam Kavusi, Bosch Research, Palo Alto, CA Kenneth Salisbury, Stanford University, Stanford, CA

Organizer: Organizer: Chair:

Most of us dreamt about robots in our childhood interacting and assisting us in our daily life. They are way beyond fiction and have emerged to become unavoidable in minimally-invasive surgery and industrial automation. There is also an explosion in research areas around autonomous cars, humanoid/android, and personal assistance robots. Such advances are largely due to the advances in semiconductor technologies driven by consumer and automotive electronics. Increasingly robotic platforms are also benefiting from the wirelessly connected infrastructure and the cloud. This session provides an overview of the major areas and their challenges that may be addressed by semiconductor technologies.

Time 8:00

Topic Robot Society with Teleoperated Robots and Androids Hiroshi Ishiguro, Osaka University and ATR, Osaka and Kyoto, Japan Robotics for Minimally-Invasive Surgery and Therapy Simon DiMaio, Intuitive Surgical, Sunnyvale, CA Advancing Personal Robotics Gnter Niemeyer, Willow Garage, Menlo Park, CA Humanoid Robotics for Services Bruno Maisonnier, ALDEBARAN Robotics, Paris, France

8:25 8:50 9:15

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SESSION 1

Monday February 20th, 8:30 AM

PLENARY SESSION INVITED PAPERS

Chair: Anantha Chandrakasan, Massachusetts Institute of Technology, Cambridge, MA ISSCC Conference Chair Associate Chair: Hideto Hidaka, Renesas Electronics, Itami, Japan ISSCC Program Committee Chair

FORMAL OPENING OF THE CONFERENCE 1.1 FlashMemory The Great Disruptor! Eli Harari, Co-Founder, Former CEO, and Chairman (retired), SanDisk , Milpitas, CA

8:30AM 8:45AM

Since its commercial introduction in 1988 Flash-memory chip density has advanced through 19 technology nodes, doubling the number of bits per chip with each successive node, with sub 20nm 128Gb Flash chips entering volume production in 2012. This incredible pace has been made possible by the use of the industry-workhorse floating-gate Fowler-Nordheim tunneling cell, first employed in EEPROM, then in NOR and NAND Flash EEPROM. The convergence of NAND Flash with System-Flash and Multi Level Cells (MLC) in the past decade transformed Flash from primarily a code-store memory to a highly-reliable low-cost data-store medium, bringing enormous price reductions and capacity growth to consumers. Flash became an enabling technology to, as well as a prime beneficiary from, the digital consumer electronics revolution, the rise of the Internet, and the proliferation of wireless mobile devices (most recently, smartphones and tablets), fueling the rapid growth of Flash storage into a $25 billion industry today. Over the past decade, Flash storage profoundly disrupted analog film, floppy disks, magnetic tapes, micro-drives, and optical CDs. Price elasticity drove rapid growth in consumer demand for Flash units and megabytes. Fierce competition among Flash suppliers ensured an ample supply, and created Flash-card format standards developed by Industry Associations, thereby open to all. Billions of units of SD, micro-SD, USB Flash-drive, and embedded Flash are sold by the industry each year, working seamlessly in literally tens of thousands of different host devices that are used in a broad spectrum of industries and applications. I have been fortunate to have been involved with the semiconductor Non-Volatile-Memory industry over its 40-year history, first as a device physicist, then as an entrepreneur and businessman. In this presentation, I will provide my personal recollections of some of the past milestones of this industry, and commentary on the profound impact that Flash has had on Consumer Electronics and Mobile Computing. Looking forward, I will briefly discuss the substantial opportunities, as well as the considerable challenges for NAND Flash and post-NAND 3D Flash in the sub-20nm era ahead. I foresee that technology and manufacturing challenges will be overcome through device and architectural innovations, and that in the coming decade NAND and post-NAND 3D Flash will grow to eclipse all other storage media, whether semiconductor, magnetic, or optical, thereby completing a breathtaking odyssey spanning 50 years!

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SESSION 1
1.2

Monday February 20th, 9:20 AM

9:20AM

The Role of Semiconductors in the Energy Landscape Carmelo Papa, Senior Executive VP/GM, STMicroelectronics, Geneva, Switzerland

The exponential increase of world energy demand, with a forecasted rise in electricity consumption of 45% between 2010 and 2030, makes energy management one of the most urgent topics of this century, and a key driver of the evolution semiconductors and electronics components. Furthermore, the Kyoto Protocol on Climate Change targets a limitation of global temperature increase to 2C maximum, within 2030, through two primary interventions: by increasing electricity production from renewable and bio-fuel sources, and by increasing energy efficiency, using a wider adoption of microelectronics. Energy efficiency can contribute up to 54% of the required CO2 reduction. From the application point of view, electricity consumption comes from 3 major areas of use: Power Supply (24%), Lighting (21%), and Motor Control (55%). Semiconductors will play an essential role in this scenario, thanks to a continuous improvement in silicon technologies, innovative IC topologies, and system design methodologies. For example, for the past 10 years, appliances have seen a progressive replacement of universal motors with brushless motors using powerful and cost-efficient microcontrollers with embedded advanced software algorithms, such as the ultimate Field-Oriented Controls. Thanks to this development, the market welcomes new Class-A+ Home Appliances with average energy efficiency increase by 30% or more, that provide a saving of up to 50TWh by 2020, todays equivalent electricity consumption of Portugal and Latvia. Cost-effective IC solutions make todays CFL (Compact Fluorescent Lamp) and LED lighting technology adoption more affordable, with corresponding power-consumption reduction. For instance, the replacement of incandescent lamps with CFL in Europe will allow a saving of 11.5TWh by 2025, that is, one third of Denmarks current electricity consumption. More Moore and More than Moore technologies will play an important role in the energy revolution involving aspects of the Smart Grid, particularly in Power-Conversion and Connectivity Systems. The first, with the adoption of finer lithography geometries, will allow miniaturization and integration at the component level, while the latter with heterogeneous system integration will allow the introduction of more functions like micro-batteries, smart sensors, plastic electronics, energy harvesting, and so on. What we see is a kind of revolution, with an enormous impact on sustainability, quality of life, and societal change!

ISSCC, SSCS, IEEE AWARD PRESENTATIONS BREAK

9:55AM 10:20AM

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SESSION 1
1.3

Monday February 20th, 10:35 AM

10:35AM

Take the Expressway to Go Greener Yoichi Yano, Executive VP, Renesas Electronics, Tokyo, Japan

Society is going green! Increasingly, people commit to choosing equipment with lower energy demands. Historically, the growth of green has been repeatedly motivated by various economic shocks, such as the 1973 oil crisis. More recently, the Lehman Brothers crisis in 2008 inspired green initiatives in various industry sectors: surges in solar-power generation, eco-friendly white-goods products, consumer electronics, and green hybrid cars. Most recently, the 3.11 earthquake and tsunami in Japan triggered another wave in energy-saving life style motivated by the shortage of electric power. Now, the world is demanding greener products for a greener society on a scale never seen before. How can we reduce power consumption? Over time, microelectronics has evolved to save power. Semiconductor technology has been in the lead in the reduction of power consumption, by enabling monitoring, controlling, and managing of energy consumption. The key product in this advance has been a lesscommonly-known semiconductor device called the microcontrollers. Microcomputers were introduced to the market in the early 1970s, firstly for electronic calculators, then in electro-mechanical controllers such as in cash registers, white goods, and consumer electronics. Then, microcomputers evolved along two different paths one, called Microprocessors (MPU), for Personal Computers and Servers, and another called Microcontrollers (MCUs) for embedded controls. Beginning in 1987, market research firms began to track world-wide shipment data for these two categories. Thus, we know that in 2010, 500 million MPUs and 13 billion MCUs were shipped the latter being 20x expansion since 1987. Currently, about 400 MCUs are shipped EVERY SECOND! Now, that MCUs are everywhere you imagine, we see more than one hundred such devices in every modern home in white goods, consumer electronics, remote controllers, metering, and so on. We find approximately one hundred MCUs in a modern car in engine control, transmission control, body electronics, HVAC, window control, mirror control, Hybrid and all Electric Vehicle, and so on. Wide acceptance of MCUs in various embedded applications results from their ease of use, the availability of a wide range of products, and their self containment everything needed is integrated on a tiny piece of silicon. In short, MCUs are low-power, small in foot print, adequate in performance, and low-cost. Technology-wise, the strength of an MCU comes from its programmability via on-board Flash-memory technology. While the introduction of Flash-based MCUs goes back to the early 1990s, its widespread use in low-end microcontrollers was delayed to the early 2000s. Flash-based MCUs changed the world because of their programmability within a very small foot print and at low power. Thus, the huge current market! Most recently an MCU has been developed that can operate from one lemon as a battery source. Such MCUs can save tremendous amounts of power through their vast use in a myriad of applications. They are truly the core technology for everything going greener! Yet, MCUs will evolve further to save power, in wide spread applications including the energy harvesting environment. On the other hand, the automotive industry requires higher real-time performance with a much higher level of functional safety in addition to lower power. Such requirements will drive the development of next generation Flash MCUs on the expressway to going green!

13

SESSION 1
1.4

Monday February 20th, 11:10 AM

11:10AM

Sustainability in Silicon and Systems Development David Perlmutter, Executive VP, Intel, Santa Clara, CA

It has been predicted that Moores Law will continue to double transistor-integration capacity every two years, providing the abundance of transistors needed to realize novel architectures for future platforms. These platforms will enable more more-intelligent electronic gadgets and devices to enrich our lives. Harnessing Moores Law and sustaining this growth over the last four decades has not been easy. The task has been challenging; overcoming design-productivity limitations in the 80s; power dissipation in the 90s; and leakage power in the last decade. However, we have persevered! But now, the major challenge we will face in the coming decade is not just power, but energy efficiency. Imagine a 100 gigaoperations-per-second mobile device, a product that we would expect by the end of the decade, consuming hundreds of watts of power! Likewise, with present techniques, a high-end exascale supercomputer would be expected to consume in excess of 1 gigawatts of power; not a practical solution. While Moores Law continues to provide more transistors, power budgets limit our ability to use them. However, there are several technologies on the horizon which provide relief, and that we must exploit. Advances in transistor structures such as 3D tri-gate transistors in 22nm, 3D die stacking, and future heterogeneous technologies, will provide higher performance at lower energy and leakage. Circuit technologies such as near-threshold-voltage logic can boost energy efficiency by an order of magnitude. Novel architectures can implement fine-grain power and energy management. System software can be smarter and self-aware to manage the entire platform with an order-of-magnitude improvement in energy efficiency. Clearly, in the expansion of the compute continuum, the energy-efficiency challenge is best served with the co-design spirit; from top to bottom and from applications to process technology, all in harmony. Energy efficiency of the compute sector will become increasingly important, with exponential growth, and we must make smart choices about resource consumption that can help save the environment. Intel recognizes the importance of caring for the planet by developing technological solutions to reducing the environmental impact of computing. This talk will addresses energy efficiency, and outlines challenges, solutions, and opportunities in the next decade for the compute continuum.

PRESENTATION TO PLENARY SPEAKERS CONCLUSION

11:45AM 11:55AM

14

SESSION 2
Session Chair: Associate Chair: 2.1

Monday February 20th, 1:30 PM

HIGH-BANDWIDTH DRAM & PRAM
Joo Sun Choi, Samsung Electronics, Hwasung, Korea Daisaburo Takashima, Toshiba, Yokohama, Japan

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with 1:30 PM Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, H. Jeoung, K-W. Lee, J. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D-H. Jung, J. Choi, B. Moon, J-H. Choi, B. Kim, S-J. Jang, J. Choi, K. Oh Samsung Electronics, Hwasung, Korea 2.2 A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with Bank Group 2:00 PM and 4 Half-Page Architecture K. Koo, S. Ok, Y. Kang, S. Kim, C. Song, H. Lee, H. Kim, Y. Kim, J. Lee, S. Oak, Y. Lee, J. Lee, J. Lee, H. Lee, J. Jang, J. Jung, B. Choi, Y. Kim, Y. Hur, Y. Kim, B. Chung, Y. Kim Hynix Semiconductor, Icheon, Korea 2.3 2:30 PM A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with Local-Bitline Sense Amplifier, Hybrid LIO Sense Amplifier and Dummy-Less Array Architecture K-N. Lim, W-J. Jang, H-S. Won, K-Y. Lee, H. Kim, D-W. Kim, M-H. Cho, S-L. Kim, J-H. Kang, K-W. Park, B-T. Jeong Hynix Semiconductor, Icheon, Korea Break 3:00 PM 2.4 A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with Input 3:15 PM Skew Calibration and Enhanced Control Scheme Y-C. Bae, J-Y. Park, S. Rhee, S. Ko, Y. Jeong, K-S. Noh, Y. Son, J. Youn, Y. Chu, H. Cho, M. Kim, D. Yim, H-C. Kim, S-H. Jung, H-I. Choi, S. Yim, J-B. Lee, J. Choi, K. Oh Samsung Electronics, Hwasung, Korea 2.5 A 20nm 1.8V 8Gb PRAM with 40MB/s Program Bandwidth 3:45 PM Y. Choi, I. Song, M-H. Park, H. Chung, S. Chang, B. Cho, J. Kim, Y. Oh, D. Kwon, J. Sunwoo, J. Shin, Y. Rho, C. Lee, M. Kang, J. Lee, Y. Kwon, S. Kim, J. Kim, Y-J. Lee, Q. Wang, S. Cha, S. Ahn, H. Horii, J. Lee, K. Kim, H. Joo, K. Lee, Y-T. Lee, J. Yoo, G. Jeong Samsung Electronics, Hwasung, Korea A 283.2W 800Mb/s/pin DLL-Based Data Self-Aligner for 4:15 PM Through-Silicon Via (TSV) Interface H-W. Lee1,2, S-B. Lim1, J. Song1, J-B. Koo1, D-H. Kwon2, J-H. Kang2, Y. Kim2, Y-J. Choi2, K. Park2, B-T. Chung2, C. Kim1 1 Korea University, Seoul, Korea 2Hynix Semiconductor, Icheon, Korea An 8Gb/s/pin 4pJ/b/pin Single-T-Line Dual (Base+RF) Band 4:30 PM Simultaneous Bidirectional Mobile Memory I/O Interface with Inter-Channel Interference Suppression Y. Kim1, G-S. Byun2, A. Tang1, C-P. Jou3, H-H. Hsieh3, G. Reinman1, J. Cong1, M-C. Chang1 1 University of California, Los Angeles, Los Angeles, CA 2 West Virginia University, Morgantown, WV 3 TSMC, Hsinchu, Taiwan 2.8 A 7Gb/s/Link Non-Contact Memory Module for Multi-Drop Bus System Using Energy-Equipartitioned Coupled Transmission Line W-J. Yun, S. Nakano, W. Mizuhara, A. Kosuge, N. Miura, H. Ishikuro, T. Kuroda Keio University, Yokohama, Japan Conclusion 4:45 PM 2.7 2.6

5:00 PM

15

SESSION 3
Session Chair: Associate Chair:

Monday February 20th, 1:30 PM

PROCESSORS
Joshua Friedrich, IBM, Austin, TX Luke Shin, Oracle, Santa Clara, CA

3.1 A 22nm IA Multi-CPU and GPU System-on-Chip S. Damaraju1, V. George1, S. Jahagirdar1, T. Khondker1, R. Milstrey1, S. Sarkar1, S. Siers1, I. Stolero2, A. Subbiah1 1 Intel, Folsom, CA 2 Intel, Haifa, Israel 3.2

IDS

1:30 PM

A 32-Core RISC Microprocessor with Network Accelerators, 2:00 PM Power Management and Testability Features B. Miller, D. Brasili, T. Kiszely, R. Kuhn, R. Mehrotra, M. Salvi, M. Kulkarni, A. Varadharajan, S-H. Yin, W. Lin, A. Hughes, B. Stysiack, V. Kandadi, I. Pragaspathi, D. Hartman, D. Carlson, V. Yalala, T. Xanthopoulos, S. Meninger, E. Crain, M. Spaeth, A. Aina, S. Balasubramanian, J. Vulih, P. Tiwary, D. Lin, R. Kessler, B. Fishbein, A. Jain Cavium, Marlboro, MA 3.3 The Next-Generation 64b SPARC Core in a T4 SoC Processor 2:30 PM J. Shin, H. Park, H. Li, A. Smith, Y. Choi, H. Sathianathan, S. Dash, S. Turullols, S. Kim, R. Masleid, G. Konstadinidis, R. Golla, M. Doherty, G. Grohoski, C. McAllister Oracle, Santa Clara, CA Break 3:00 PM

32nm x86 OS-Compliant PC On-Chip with Dual-Core Atom 3:15 PM Processor and RF WiFi Transceiver H. Lakdawala1, M. Schaecher2, C-T. Fu1, R. Limaye3, J. Duster1, Y. Tan1, A. Balankutty1, E. Alpman1, C. Lee1, S. Suzuki1, B. Carlton1, H. Kim1, M. Verhelst1, S. Pellerano1, T. Kim2, D. Srivastava1, S. Venkatesan3, H-J. Lee1, P. Vandervoorn1, J. Rizk1, C-H. Jan1, K. Soumyanath1, S. Ramamurthy1 1 Intel, Hillsboro, OR; 2Intel, Chandler, AZ; 3Intel, Santa Clara, CA 3.5 An 800MHz 320mW 16-Core Processor with Message-Passing and Shared-Memory Inter-Core Communication Mechanisms Z. Yu, K. You, R. Xiao, H. Quan, P. Ou, Y. Ying, H. Yang, M. Jing, X. Zeng Fudan University, Shanghai, China 3.6 3:45 PM

3.4

A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor IDS 4:15 PM in 32nm CMOS S. Jain1, S. Khare1, S. Yada1, A. V1, P. Salihundam1, S. Ramani1, S. Muthukumar1, S. M1, A. Kumar1, S. Gb1, R. Ramanarayanan1, V. Erraguntla1, J. Howard2, S. Vangal2, S. Dighe2, G. Ruhl2, P. Aseron2, H. Wilson2, N. Borkar2, V. De2, S. Borkar2 1 Intel, Bangalore, India; 2Intel, Hillsboro, OR Resonant Clock Design for a Power-Efficient High-Volume x86-64 Microprocessor V. Sathe1, S. Arekapudi2, A. Ishii3, C. Ouyang2, M. Papaefthymiou3,4, S. Naffziger1 1 AMD, Fort Collins, CO 2AMD, Sunnyvale, CA 3 Cyclos Semiconductor, Berkeley, CA; 4University of Michigan, Ann Arbor, MI 3.8 A Reconfigurable Distributed All-Digital Clock Generator Core with SSC and Skew Correction in 22nm High-k Tri-Gate LP CMOS Y. Li1, C. Ornelas2, H. Kim1, H. Lakdawala1, A. Ravi1, K. Soumyanath1 1 Intel, Hillsboro, OR; 2Intel, Guadalajara, Mexico Conclusion 3.7 4:45 PM

5:00 PM

5:15 PM

16

SESSION 4

Monday February 20th, 1:30 PM

RF TECHNIQUES

Session Chair: Associate Chair: 4.1

Masoud Zargari, Qualcomm, Irvine, CA Songcheol Hong, KAIST, Daejeon, Korea

A Blocker-Tolerant Wideband Noise-Cancelling Receiver 1:30 PM with a 2dB Noise Figure D. Murphy1,2, A. Hafez1,2, A. Mirzaei2, M. Mikhemar2, H. Darabi2, M-C. Chang1, A. Abidi1 1 University of California, Los Angeles, Los Angeles, CA 2 Broadcom, Irvine, CA 4.2 8-Path Tunable RF Notch Filters for Blocker Suppression A. Ghaffari, E. Klumperink, B. Nauta University of Twente, Enschede, The Netherlands 4.3 A Wideband IM3 Cancellation Technique for CMOS Attenuators W. Cheng, M. Oude Alink, A. Annema, G. Wienk, B. Nauta University of Twente, Enschede, The Netherlands A 1-to-2.5GHz Phased-Array IC Based on gm-RC All-Pass Time-Delay Cells S. Garakoui, E. Klumperink, B. Nauta, F. Van Vliet University of Twente, Enschede, The Netherlands Break 4.5 A Fully Integrated Dual-Mode CMOS Power Amplifier for WCDMA Applications B. Koo1, T. Joo1, Y. Na2, S. Hong1 1 KAIST, Daejeon, Korea 2 Samsung Electro-Mechanics, Suwon, Korea 4.6 A 28.3mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a +27.1dBm WCDMA CMOS Power Amplifier S. Kousai, K. Onizuka, T. Yamaguchi, Y. Kuriyama, M. Nagaoka Toshiba, Kawasaki, Japan 4.7 4.4 2:00 PM

2:30 PM

2:45 PM

3:00 PM 3:15 PM

3:45 PM

A Fully Integrated Triple-Band CMOS Power Amplifier 4:15 PM for WCDMA Mobile Handsets K. Kanda1, Y. Kawano2, T. Sasaki2, N. Shirai2, T. Tamura2, S. Kawai2, M. Kudo2, T. Murakami2, H. Nakamoto1, N. Hasegawa2, H. Kano2, N. Shimazui2, A. Mineyama3, K. Oishi1, M. Shima4, N. Tamura4, T. Suzuki3, T. Mori1, K. Niratsuka2, S. Yamaura2 1 Fujitsu Laboratories, Kawasaki, Japan 2 Fujitsu Semiconductor, Yokohama, Japan 3 Fujitsu Laboratories, Atsugi, Japan 4 Fujitsu Semiconductor, Mie, Japan 4.8 A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp Differential Swing 4:45 PM

I. Sarkas, A. Balteanu, E. Dacquay, A. Tomkins, S. Voinigescu University of Toronto, Toronto, ON, Canada Conclusion 5:15 PM

17

SESSION 5

Monday February 20th, 1:30 PM

AUDIO AND POWER CONVERTERS

Session Chair: Associate Chair: 5.1

Wing-Hung Ki, HKUST, Hong Kong, China Jed Hurwitz, Consultant, Edinburgh, United Kingdom

An 8 2.5W 1%-THD 104dB(A)-Dynamic-Range Class-D Audio Amplifier with an Ultra-Low EMI System and Current Sensing for Speaker Protection A. Nagari, E. Allier, F. Amiard, V. Binet, C. Fraisse ST-Ericsson, Grenoble, France 5.2

IDS

1:30 PM

A 1.5W 10V-Output Class-D Amplifier Using a Boosted Supply From a Single 3.3V Input in Standard 1.8V/3.3V 0.18m CMOS B. Serneels, E. Geukens, B. De Muer, T. Piessens ICsense, Leuven, Belgium 5.3

2:00 PM

A 0.028% THD+N, 91% Power-Efficiency, 3-Level PWM 2:30 PM Class-D Amplifier with a True Differential Front-End S. Kwon1, I. Kim2, S. Yi1, S. Kang1, S. Lee1, T. Hwang1, B. Moon1, Y. Choi1, H. Sung1, J. Koh1 1 Dongbu Hitek, Seoul, Korea 2 Samsung Electronics, Kyunggi-Do, Korea 5.4 A 41-Phase Switched-Capacitor Power Converter with 2:45 PM 3.8mV Output Ripple and 81% Efficiency in Baseline 90nm CMOS G. Villar Piqu NXP Semiconductors, Eindhoven, The Netherlands Break 3:00 PM 3:15 PM

A High-Voltage CMOS IC and Embedded System for Distributed Photovoltaic Energy Optimization with Over 99% Effective Conversion Efficiency and Insertion Loss Below 0.1% J. Stauth1,2, M. Seeman2, K. Kesarwani2 1 Dartmouth College, Hanover, NH 2 Solar Semiconductor, Sunnyvale, CA A Maximum Power-Point Tracker without Digital Signal Processing in 0.35m CMOS for Automotive Applications R. Enne, M. Nikolic, H. Zimmermann Vienna University of Technology, Vienna, Austria 5.7 5.6

5.5

3:45 PM

A 40mV Transformer-Reuse Self-Startup Boost Converter 4:15 PM with MPPT Control for Thermoelectric Energy Harvesting J-P. Im1, S-W. Wang1, K-H. Lee1, Y-J. Woo2, Y-S. Yuk1, T-H. Kong1, S-W. Hong1, S-T. Ryu1, G-H. Cho1 1 KAIST, Daejeon, Korea 2 Siliconworks, Daejeon, Korea A 330nA Energy-Harvesting Charger with Battery IDS 4:45 PM Management for Solar and Thermoelectric Energy Harvesting K. Kadirvel1, Y. Ramadass2, U. Lyles1, J. Carpenter1, A. Chandrakasan3, B. Lum-Shue-Chan1 1 Texas Instruments, Melbourne, FL 2 Texas Instruments, Dallas, TX 3 Massachusetts Institute of Technology, Cambridge, MA Conclusion 5:15 PM 5.8

18

SESSION 6

Monday February 20th, 1:30 PM

MEDICAL, DISPLAYS AND IMAGERS

Session Chair: Associate Chair: 6.1

Yusuke Oike, Sony, Atsugi, Japan Maysam Ghovanloo, Georgia Institute of Technology, Atlanta, GA

A Sampling-Based 128128 Direct Photon-Counting X-Ray Image 1:30 PM Sensor with 3 Energy Bins and Spatial Resolution of 60m/pixel H-S. Kim1, S-W. Han2, J-H. Yang1, S. Kim2, Y. Kim2, S. Kim2, D-K. Yoon2, J-S. Lee2, J-C. Park2, Y. Sung2, S-D. Lee2, S-T. Ryu1, G-H. Cho1 1 KAIST, Daejeon, Korea; 2Samsung Advanced Institute of Technology, Yongin, Korea 6.2 A 1.36W Adaptive CMOS Image Sensor with Reconfigurable Modes of Operation From Available Energy/Illumination for Distributed Wireless Sensor Network J. Choi, S. Park, J. Cho, E. Yoon; University of Michigan, Ann Arbor, MI 6.3 A 0.5V 4.95W 11.8fps PWM CMOS Imager with 82dB Dynamic Range and 0.055% Fixed-Pattern-Noise M-T. Chung, C-C. Hsieh; National Tsing Hua University, Hsinchu, Taiwan 6.4 2:00 PM

2:30 PM

A Capacitive Touch Controller Robust to Display Noise 2:45 PM for Ultrathin Touch Screen Displays K-D. Kim, S-H. Byun, Y-K. Choi, J-H. Baek, H-H. Cho, J-K. Park, H-Y. Ahn, C-J. Lee, M-S. Cho, J-H. Lee, S-W. Kim, H-D. Kwon, Y-Y. Choi, H. Na, J. Park, Y-J. Shin, K. Jang, G. Hwang, M. Lee Samsung Electronics, Yongin, Korea Break 3:00 PM A 160A Biopotential Acquisition ASIC with Fully 3:15 PM IDS Integrated IA and Motion-Artifact Suppression N. Van Helleputte1, S. Kim1, H. Kim1, J. Kim2, C. Van Hoof1,3, R. Yazicioglu1 1 imec, Heverlee, Belgium; 2Samsung Advanced Institute of Technology, Yongin, Korea 3 KU Leuven, Leuven, Belgium 6.5 6.6 CMOS Capacitive Biosensor with Enhanced Sensitivity for Label-Free DNA Detection K-H. Lee, S. Choi, J. Lee, J-B. Yoon, G-H. Cho; KAIST, Daejeon, Korea 3:45 PM

A 100Mphoton/s Time-Resolved Mini-Silicon Photomultiplier with On-Chip Fluorescence Lifetime Estimation in 0.13m CMOS Imaging Technology D. Tyndall1, B. Rae2, D. Li3, J. Richardson4, J. Arlt1, R. Henderson1 1 University of Edinburgh, Edinburgh, United Kingdom 2 STMicroelectronics, Edinburgh, United Kingdom 3 University of Sussex, Brighton, United Kingdom 4 Dialog Semiconductor, Edinburgh, United Kingdom 6.8

6.7

4:00 PM

A Wireless Magnetoresistive Sensing System for ADS 4:15 PM an Intra-Oral Tongue-Computer Interface H. Park1, B. Gosselin2, M. Kiani1, H-M. Lee1, J. Kim1, X. Huo1, M. Ghovanloo1 1 Georgia Institute of Technology, Atlanta, GA; 2Laval University, Quebec, QC, Canada 6.9 A CMOS 10kpixel Baseline-Free Magnetic Bead Detector with Column-Parallel Readout for Miniaturized Immunoassays S. Gambini, K. Skucha, P. Liu, J. Kim, R. Krigel, R. Mathies, B. Boser University of California at Berkeley, Berkeley, CA Conclusion 4:45 PM

5:15 PM

19

ACADEMIC DEMONSTRATION SESSION (ADS)*

ISSCC 2012 is expanding the industrial demonstration event introduced last year to include the Academic Demonstration Session (ADS), to be held on Monday February 20th, from 4 to 7 pm, Golden Gate Hall. ADS will feature live demonstrations of selected ICs presented by academics in regular paper sessions. ADS is intended to demonstrate real-life applications made possible by new ICs presented this year. In the Advance Program, papers for which demonstrations are available will be notated by the symbol ADS, ADS

Monday, February 20th

6.8 A Wireless Magnetoresistive Sensing System for an Intra-Oral Tongue-Computer Interface 4:15 PM

Tuesday, February 21st

10.6 3D-MAPS: 3D Massively Parallel Processor with Stacked Memory 10.7 Centip3De: A 3930DMIPS/W Configurable Near-Threshold 3D Stacked System with 64 ARM Cortex-M3 Cores 11.5 A 0.4C (3) -70 to 200C Time-Domain Temperature Sensor Based on Heat Diffusion in Si and SiO2 12.4 A 320mW 342GOPS Real-Time Moving Object Recognition Processor for HD 720p Video Streams 15.1 A 1kPixel CMOS Camera Chip for 25fps Real-Time Terahertz Imaging Applications 16.8 Voltage-Boosting Wireless Power Delivery System with Fast Load Tracker by -Modulated Sub-Harmonic Resonant Switching 17.2 A 259.6W Nonlinear HRV-EEG Chaos Processor with Body Channel Communication Interface for Mental Health Monitoring 17.3 A Sub-10nA DC-Balanced Adaptive Stimulator IC with Multimodal Sensor for Compact Electro-Acupuncture System 10:45 AM 11:15 AM

10:15 AM

3:15 PM

1:30 PM

5:00 PM

2:00 PM 2:30 PM

Wednesday, February 22nd

22.2 A Global-Shutter CMOS Image Sensor with Readout Speed of 1Tpixel/s Burst and 780Mpixel/s Continuous 25.2 Over-10-Extended-Lifetime 76%-Reduced-Error Solid-State Drives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme 26.4 An Interference-Aware 5.8GHz Wake-Up Radio for ETCS 28.4 A 200mV 32b Subthreshold Processor with Adaptive Supply Voltage Control 9:00 AM

2:00 PM

3:15 PM 2:45 PM

*ADS may include additional demonstrations of work reported at the Student Research Preview.

20

EVENING SESSIONS
ES3:

Monday February 20th, 8:00 PM

Technologies that Could Change the World You Decide!

Organizer: Jed Hurwitz, Broadcom, Edinburgh, United Kingdom Chair: Jafar Savoj, Xilinx, San Jose, CA

Often a new technology comes along that is just plain different than incumbent solutions or approaches. This session looks at a number of recent ideas that are asking us to re-assess the way things are done today. It should be an entertaining evening, providing an overview of the new technologies, their key benefits (and weaknesses) and an update on where they now sit, and which barriers and markets they may conquer. There will be an opportunity for the audience to question the speakers, as there will undoubtedly be interesting alternative viewpoints!

Time 8:00 8:25

Topic MEMS-Based Resonators and Oscillators are Now Replacing Quartz Aaron Partridge, SiTime, Sunnyvale, CA Thermal Diffusivity Sensors: Temperature Sensors that Scale! Kofi Makinwa, Delft University of Technology, Delft, The Netherlands VCO-Based Quantizers: Has Their Time Arrived? Michael H. Perrott, Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates Continuous Time DSPs Yannis Tsividis, Columbia University, New York, NY Analog Syntheses: Computer-Aided Design to Secure Analog Design Quality and Productivity Georges Gielen, Katholik University of Leuven, Leuven, Belgium

8:50

9:15 9:40

21

EVENING SESSION
ES4:
Organizer: Organizer: Organizer: Chair:

Monday February 20th, 8:00 PM

Optical PCB Interconnects, Niche or Mainstream?

Ichiro Fujimori, Broadcom, Irvine, CA SeongHwan Cho, KAIST, Daejon, Korea Joshua Friedrich, IBM, Austin, TX John Stonick, Synopsis, Hillsboro, OR

Efforts in the area of optical backplane technology have been underway for several years, generating significant interest. Recently, these efforts have led to discussions regarding the role of embedded optics for chip-to-chip communication on printed circuit boards. A consensus appears to be emerging that PCB interconnects for mainframes and high-end servers will leverage optical technologies, but will these approaches ever go mainstream? In this evening session, we will review the latest in optical interconnect-related circuit design, the prospects for optics use in mainstream I/O applications, and to provide comparison to copper-based solutions and associated roadmaps. Time 8:00 8:30 Topic Optical Interconnects Why We Will Have To Use Them David Miller Stanford University, Stanford, CA Optical PCB Interconnects For Computing Applications: From Niche to Mainstream Bert Offrein IBM Research, Zurich, Switzerland Integrated Silicon Photonics and Applications In and Around PC/Servers Mario Paniccia, Intel, Santa Clara, CA The Final Push to Mainstream; Can Integrated Optics Learn From Integrated Magnetics? Keishi Ohashi, NEC, Tsukuba, Japan

9:00

9:30

EP1:
Organizer:

Is RF Doomed to Digitization? What Shall RF Circuit Designers Do?

R. Bogdan Staszewski, Delft University of Technology, Delft, The Netherlands Jacques Rudell, University of Washington, Seattle, WA

Moderator:

The most recent trend in RF design is toward more and more digital content. This is very intriguing but, at the same time, it could be quite challenging to traditionally-minded designers as well as new entrants who have been educated using contemporary textbooks that are yet to be updated. What is the ultimate destiny of RF architectural and circuit design? Will RF share the same digitization fate as, for example, the audio on cellular phones? Are there any alternatives or safe havens far from the digital encroachment? Seven leading experts from industry and academia will debate this controversial topic. Panelists: Borivoje Nikolic, UC Berkeley, Berkeley, CA Oren Eliezer, Xtendwave, Plano, TX Ken Hansen, Freescale, Austin, TX Rik Jos, NXP, Nijmegen, The Netherlands Andreas Kaiser, IEMN-ISEN, Lille, France Lawrence Loh, Mediatek, Hsinchu, Taiwan Akira Matsuzawa, Tokyo Institute of Technology, Tokyo, Japan

22

SESSION 7

Tuesday February 21st, 8:30 AM

MULTI GB/s RECEIVER AND PARALLEL I/O TECHNIQUES

Session Chair: Associate Chair: 7.1 Bob Payne, Texas Instruments, Dallas, TX Tatsuya Saito, Hitachi, Kawasaki, Kanagawa, Japan

An 18.6Gb/s Double-Sampling Receiver in 65nm CMOS 8:30 AM for Ultra-Low-Power Optical Communication M. Honarvar Nazari, A. Emami-Neyestanak California Institute of Technology, Pasadena, CA 7.2 A 0.4mW/Gb/s 16Gb/s Near-Ground Receiver Front-End 9:00 AM with Replica Transconductance Termination Calibration K. Kaviani, A. Amirkhany, C. Huang, P. Le, C. Madden, K. Saito, K. Sano, V. Murugan, W. Beyene, K. Chang, C. Yuan Rambus, Sunnyvale, CA 7.3 A 19Gb/s Serial Link Receiver with Both 4-Tap FFE and 5-Tap DFE Functions in 45nm SOI CMOS A. Agrawal, J. Bulzacchelli, T. Dickson, Y. Liu, J. Tierno, D. Friedman IBM T. J. Watson, Yorktown Heights, NY Break 7.4 9:30 AM

10:00 AM

An 8GB/s Quad-Skew-Cancelling Parallel Transceiver 10:15 AM in 90nm CMOS for High-Speed DRAM Interface Y-S. Kim1, S-K. Lee1, S-J. Bae2, Y-S. Sohn2, J-B. Lee2, J. Choi2, H-J. Park1, J-Y. Sim1 1 Pohang University of Science and Technology, Pohang, Korea 2 Samsung Electronics, Hwasung, Korea A 4.1pJ/b 16Gb/s Coded Differential Bidirectional 10:45 AM IDS Parallel Electrical Link A. Amirkhany1, K. Kaviani1, A. Abbasfar1, F. Shuaeb2, W. Beyene1, C. Hoshino3, C. Madden1, K. Chang1, C. Yuan1 1 Rambus, Sunnyvale, CA 2 Rambus, Bangalore, India 3 Rambus, Tokyo, Japan 7.5 7.6 A 5Gb/s Single-Ended Parallel Receiver with Adaptive FEXT Cancellation S-K. Lee, H. Ha, H-J. Park, J-Y. Sim Pohang University of Science and Technology, Pohang, Korea 7.7 A Compact Low-Power 3D I/O in 45nm CMOS Y. Liu, W. Luk, D. Friedman IBM T. J. Watson, Yorktown Heights, NY Conclusion 11:15 AM

11:45 AM

12:15 PM

23

SESSION 8

Tuesday February 21st, 8:30 AM

DELTA-SIGMA CONVERTERS

Session Chair: Associate Chair: 8.1

Brian Brandt, Maxim Integrated Products, North Chelmsford, MA Gerhard Mitteregger, Intel Mobile, Villach, Austria 8:30 AM

An LC Bandpass ADC with 70dB SNDR Over 20MHz Bandwidth Using CMOS DACs J. Harrison1, M. Nesselroth1, R. Mamuad1, A. Behzad2, A. Adams1, S. Avery1 1 Broadcom, Sydney, Australia 2 Broadcom, San Diego, CA A 12mW Low-Power Continuous-Time Bandpass Modulator with 58dB SNDR and 24MHz Bandwidth at 200MHz IF H. Chae1,2, J. Jeong1, G. Manganaro2, M. Flynn1 1 University of Michigan, Ann Arbor, MI 2 Analog Devices, Wilmington, MA 8.2 8.3

9:00 AM

A DC-to-1GHz Tunable RF ADC Achieving DR = 74dB 9:30 AM and BW = 150MHz at f0 = 450MHz Using 550mW H. Shibata1, R. Schreier1, W. Yang2, A. Shaikh2,3, D. Paterson2, T. Caldwell1, D. Alldred1, P. Lai2 1 Analog Devices, Toronto, ON, Canada 2 Analog Devices, Wilmington, MA 3 now independent consultant, Lahore, Pakistan Break 10:00 AM A 16mW 78dB-SNDR 10MHz-BW CT- ADC Using Residue-Cancelling VCO-Based Quantizer K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, P. Hanumolu Oregon State University, Corvallis, OR A 72dB-DR CT Modulator Using Digitally Estimated Auxiliary DAC Linearization Achieving 88fJ/conv in a 25MHz BW P. Witte1, J. Kauffman1, J. Becker1, Y. Manoli2, M. Ortmanns1 1 Ulm University, Ulm, Germany 2 University of Freiburg - IMTEK, Freiburg, Germany 8.5 A 15mW 3.6GS/s CT- ADC with 36MHz Bandwidth and 83dB DR in 90nm CMOS P. Shettigar, S. Pavan IIT Madras, Chennai, India 8.7 8.6 8.4 10:15 AM

10:45 AM

11:15 AM

11:45 AM A 20mW 61dB SNDR (60MHz BW) 1b 3rd-Order Continuous-Time Delta-Sigma Modulator Clocked at 6GHz in 45nm CMOS V. Srinivasan, V. Wang, P. Satarzadeh, B. Haroun, M. Corsi Texas Instruments, Dallas, TX Conclusion 12:15 PM

24

SESSION 9

Tuesday February 21st, 8:30 AM

WIRELESS TRANSCEIVER TECHNIQUES

Session Chair: Associate Chair: 9.1

Sven Mattisson, Ericsson, Lund, Sweden Shouhei Kousai, Toshiba, Kawasaki, Japan

A 40MHz-to-1GHz Fully Integrated Multistandard Silicon 8:30 AM Tuner in 80nm CMOS J. Greenberg1, F. De Bernardinis2, C. Tinella2, A. Milani2, J. Pan1, P. Uggetti2, M. Sosio3, S. Dai1, S. Tang1, G. Cesura2, G. Gandolfi2, V. Colonna2, R. Castello2,3 1 Marvell, Santa Clara, CA 2 Marvell, Pavia, Italy 3 University of Pavia, Pavia, Italy 9.2 A Multiband Multimode Transmitter without Driver Amplifier 9:00 AM O. Oliaei, M. Kirschenmann, D. Newman, K. Hausmann, H. Xie, P. Rakers, M. Rahman, M. Gomez, C. Yu, B. Gilsdorf, K. Sakamoto Fujitsu Semiconductor Wireless, Tempe, AZ Active Feedback Receiver with Integrated Tunable RF Channel Selectivity, Distortion Cancelling, 48dB Stopband Rejection and >+12dBm Wideband IIP3, Occupying <0.06mm2 in 65nm CMOS S. Youssef, R. Van der Zee, B. Nauta University of Twente, Enschede, The Netherlands Break 9.4 9.3 9:30 AM

10:00 AM

A 20dBm 2.4GHz Digital Outphasing Transmitter for WLAN 10:15 AM Application in 32nm CMOS P. Madoglio1, A. Ravi1, H. Xu1, K. Chandrashekar1, M. Verhelst1, S. Pellerano1, L. Cuellar2, M. Aguirre2, M. Sajadieh3, O. Degani4, H. Lakdawala1, Y. Palaskas1 1 Intel, Hillsboro, OR 2 Intel, Guadalajara, Mexico 3 Intel, Santa Clara, CA 4 Intel, Haifa, Israel 9.5 A 60GHz Outphasing Transmitter in 40nm CMOS with 15.6dBm Output Power D. Zhao, S. Kulkarni, P. Reynaert KU Leuven, Leuven, Belgium 9.6 10:30 AM

A 4-in-1 (WiFi/BT/FM/GPS) Connectivity SoC with Enhanced 10:45 AM Co-Existence Performance in 65nm CMOS Y-H. Chung1, M. Chen1, W-K. Hong1, J-W. Lai1, S-J. Wong2, C-W. Kuan1, H-L. Chu1, C. Lee1, C-F. Liao1, H-Y. Liu1, H-K. Hsu1, L-C. Ko1, K-H. Chen1, C-H. Lu1, T-M. Chen1, Y. Hsueh1, C. Chang1, Y-H. Cho1, C-H. Shen1, Y. Sun2, E-C. Low2, X. Jiang2, D. Hu2, W. Shu2, J-R. Chen1, J-L. Hsu1, C-J. Hsu1, J-H. Zhan1, O. ShanaA2, G-K. Dehng1, G. Chien3 1 MediaTek, Hsinchu, Taiwan 2 MediaTek, Singapore 3 MediaTek, San Jose, CA 9.7 A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive Switched-Capacitor Beamforming Receiver Front-End in 65nm CMOS M. Soer1, E. Klumperink1, B. Nauta1, F. Van Vliet1,2 1 University of Twente, Enschede, The Netherlands 2 TNO Science and Industry, The Hague, The Netherlands Conclusion 11:15 AM

11:30 AM

25

SESSION 10

Tuesday February 21st, 8:30 AM

HIGH-PERFORMANCE DIGITAL

Session Chair: Associate Chair:

Lew Chua-Eoan, Qualcomm, San Diego, CA Se-Hyun Yang, Samsung Electronics, Yongin, Korea 8:30 AM

10.1 A 280mV-to-1.1V 256b Reconfigurable SIMD Vector Permutation Engine with 2-Dimensional Shuffle in 22nm CMOS S. Hsu, A. Agarwal, M. Anders, S. Mathew, H. Kaul, F. Sheikh, R. Krishnamurthy Intel, Hillsboro, OR

10.2 A Source-Synchronous 90Gb/s Capacitively Driven Serial 9:00 AM On-Chip Link Over 6mm in 65nm CMOS D. Walter, S. Hppner, H. Eisenreich, G. Ellguth, S. Henker, S. Hnzsche, R. Schffny, M. Winter, G. Fettweis Technical University Dresden, Dresden, Germany 10.3 A 1.45GHz 52-to-162GFLOPS/W Variable-Precision 9:30 AM IDS Floating-Point Fused Multiply-Add Unit with Certainty Tracking in 32nm CMOS H. Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, F. Sheikh, R. Krishnamurthy, S. Borkar Intel, Hillsboro, OR 10.4 A 2.05GVertices/s 151mW Lighting Accelerator 9:45 AM for 3D Graphics Vertex and Pixel Shading in 32nm CMOS F. Sheikh, S. Mathew, M. Anders, H. Kaul, S. Hsu, A. Agarwal, R. Krishnamurthy, S. Borkar Intel, Hillsboro, OR Break 10:00 AM 10.5 A 3D System Prototype of an eDRAM Cache Stacked Over Processor-Like Logic Using Through-Silicon Vias M. Wordeman1, J. Silberman1, G. Maier2, M. Scheuermann1 1 IBM T. J. Watson, Yorktown Heights, NY 2 IBM Systems and Technology Group, Fishkill, NY 10:15 AM

ADS 10:45 AM 10.6 3D-MAPS: 3D Massively Parallel Processor with Stacked Memory D. Kim1, K. Athikulwongse1, M. Healy1, M. Hossain1, M. Jung1, I. Khorosh1, G. Kumar1, Y-J. Lee1, D. Lewis1, T-W. Lin1, C. Liu1, S. Panth1, M. Pathak1, M. Ren1, G. Shen1, T. Song1, D. Woo1, X. Zhao1, J. Kim2, H. Choi3, G. Loh1, H-H. Lee1, S. Lim1 1 Georgia Institute of Technology, Atlanta, GA 2 KAIST, Daejeon, Korea 3 Amkor Technology, Seoul, Korea ADS 11:15 AM 10.7 Centip3De: A 3930DMIPS/W Configurable Near-Threshold 3D Stacked System with 64 ARM Cortex-M3 Cores D. Fick, R. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Sylvester, D. Blaauw University of Michigan, Ann Arbor, MI
10.8 K Computer: 8.162 PetaFLOPS Massively Parallel Scalar 11:45 AM Supercomputer Built with Over 548k Cores H. Miyazaki1, Y. Kusano1, H. Okano1, T. Nakada1, K. Seki1, T. Shimizu1, N. Shinjo1, F. Shoji2, A. Uno2, M. Kurokawa2 1 Fujitsu, Kanagawa, Japan 2 RIKEN, Hyogo, Japan Conclusion 12:15 PM

26

SESSION 11
Session Chair: Associate Chair:

Tuesday February 21st, 8:30 AM

SENSORS & MEMs
Christoph Hagleitner, IBM Research, Ruschlikon, Switzerland Maurits Ortmanns, University of Ulm, Ulm, Germany 8:30 AM

11.1 A Interface for MEMS Accelerometers Using Electrostatic Spring-Constant Modulation for Cancellation of Bondwire Capacitance Drift P. Lajevardi1, V. Petkov2, B. Murmann1 1 Stanford University, Stanford, CA 2 Robert Bosch, Palo Alto, CA 11.2 A Capacitance-to-Digital Converter for Displacement Sensing with 17b Resolution and 20s Conversion Time S. Xia, K. Makinwa, S. Nihtianov Delft University of Technology, Delft, The Netherlands 11.3 A 50W Biasing Feedback Loop with 6ms Settling Time for a MEMS Microphone with Digital Output J. Van den Boom NXP Semiconductors, Nijmegen, The Netherlands 11.4 ASIC for a Resonant Wireless Pressure-Sensing System for Harsh Environments Achieving 2% Error Between -40 and 150C Using Q-Based Temperature Compensation M. Rocznik1, F. Henrici2, R. Has2 1 Robert Bosch, Palo Alto, CA 2 Robert Bosch, Stuttgart, Germany Break 11.5 A 0.4C (3) -70 to 200C Time-Domain Temperature Sensor Based on Heat Diffusion in Si and SiO2 C. Van Vroonhoven1, D. DAquino2, K. Makinwa1 1 Delft University of Technology, Delft, The Netherlands 2 National Semiconductor, Santa Clara, CA

9:00 AM

9:15 AM

9:30 AM

10:00 AM 10:15 AM

ADS

11.6 A Temperature-to-Digital Converter for a MEMS-Based IDS 10:45 AM Programmable Oscillator with Better Than 0.5ppm Frequency Stability M. Perrott1, J. Salvia2, F. Lee3, A. Partridge2, S. Mukherjee2, C. Arft2, J-T. Kim2, N. Arumugam2, P. Gupta2, S. Tabatabaei2, S. Pamarti4, H. Lee2, F. Assaderaghi2 1 Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates 2 SiTime, Sunnyvale, CA 3 Fairchild Semiconductor, San Jose, CA 4 University of California, Los Angeles, Los Angeles, CA 11.7 A CMOS Temperature Sensor with a Voltage-Calibrated Inaccuracy of 0.15C (3) From -55 to 125C K. Souri, Y. Chae, K. Makinwa Delft University of Technology, Delft, The Netherlands 11.8 Ratiometric BJT-Based Thermal Sensor in 32nm and 22nm Technologies J. Shor, K. Luria, D. Zilberman Intel, Yakum, Israel Conclusion 11:15 AM

11:45 AM

12:15 PM

27

SESSION 12

Tuesday February 21st, 1:30 PM

MULTIMEDIA & COMMUNICATIONS SOCs

Session Chair: Associate Chair: Byeong-Gyu Nam, Chungnam National University, Daejeon, Korea Shannon Morton, Nvidia, Bristol, United Kingdom

12.1 A 32nm High-k Metal Gate Application Processor 1:30 PM IDS with GHz Multi-Core CPU S-H. Yang, S. Lee, J. Lee, J. Cho, H-J. Lee, D. Cho, J. Heo, S. Cho, Y. Shin, S. Yun, E. Kim, U. Cho, J. Son, C. Kim, J. Youn, Y. Chung, S. Park, S. Hwang Samsung Electronics, Yongin, Korea 12.2 A 335Mb/s 3.9mm2 65nm CMOS Flexible MIMO 2:00 PM Detection-Decoding Engine Achieving 4G Wireless Data Rates M. Winter1, S. Kunze1, E. Perez Adeva1, B. Mennenga1, E. Mats1, G. Fettweis1, H. Eisenreich1, G. Ellguth1, S. Hppner1, S. Scholze1, R. Schffny1, T. Kobori2 1 Technical University Dresden, Dresden, Germany 2 NEC, Tokyo, Japan 12.3 A Full 4-Channel 6.3Gb/s 60GHz Direct-Conversion 2:30 PM Transceiver with Low-Power Analog and Digital Baseband Circuitry K. Okada1, K. Kondou2, M. Miyahara1, M. Shinagawa2, H. Asada1, R. Minami1, T. Yamaguchi1, A. Musa1, Y. Tsukui1, Y. Asakura2, S. Tamonoki2, H. Yamagishi2, Y. Hino2, T. Sato1, H. Sakaguchi1, N. Shimasaki1, T. Ito1, Y. Takeuchi1, N. Li1, Q. Bu1, R. Murakami1, K. Bunsen1, K. Matsushita1, M. Noda2, A. Matsuzawa1 1 Tokyo Institute of Technology, Tokyo, Japan 2 Sony, Tokyo, Japan Break 12.4 A 320mW 342GOPS Real-Time Moving Object Recognition Processor for HD 720p Video Streams J. Oh, G. Kim, J. Park, I. Hong, S. Lee, H-J. Yoo KAIST, Daejeon, Korea 3:00 PM 3:15 PM

ADS

12.5 A 464GOPS 620GOPS/W Heterogeneous Multi-Core IDS SoC for Image-Recognition Applications Y. Tanabe, M. Sumiyoshi, M. Nishiyama, I. Yamazaki, S. Fujii, K. Kimura, T. Aoyama, M. Banno, H. Hayashi, T. Miyamori Toshiba, Kawasaki, Japan 12.6 A 2Gpixel/s H.264/AVC HP/MVC Video Decoder Chip for Super Hi-Vision and 3DTV/FTV Applications D. Zhou1, J. Zhou1, J. Zhu2, P. Liu2, S. Goto1 1 Waseda University, Kitakyushu, Japan 2 Shanghai Jiao Tong University, Shanghai, China 12.7 A True Multistandard, Programmable, Low-Power, IDS Full HD Video-Codec Engine for Smartphone SoC M. Mehendale1, S. Das1, M. Sharma1, M. Mody1, R. Reddy1, J. Meehan2, H. Tamama3, B. Carlson3, M. Polley3 1 Texas Instruments, Bangalore, India 2 Texas Instruments, Nice, France 3 Texas Instruments, Dallas, TX Conclusion

3:45 PM

4:15 PM

4:45 PM

5:15 PM

28

SESSION 13

Tuesday February 21st, 1:30 PM

HIGH-PERFORMANCE EMBEDDED SRAM

Session Chair: Associate Chair:

Leland Chang, IBM T.J. Watson, Yorktown Heights, NY Michael Clinton, Texas Instruments, Dallas, TX

13.1 A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology 1:30 PM with Integrated Active VMIN-Enhancing Assist Circuitry E. Karl, Y. Wang, Y-G. Ng, Z. Guo, F. Hamzaoglu, U. Bhattacharya, K. Zhang, K. Mistry, M. Bohr Intel, Hillsboro, OR 13.2 A 6T SRAM with a Carrier-Injection Scheme to Pinpoint and Repair Fails That Achieves 57% Faster Read and 31% Lower Read Energy K. Miyaji1, T. Suzuki2, S. Miyano2, K. Takeuchi1 1 University of Tokyo, Tokyo, Japan 2 Semiconductor Technology Academic Research Center, Yokohama, Japan 13.3 Capacitive-Coupling Wordline Boosting with Self-Induced VCC Collapse for Write VMIN Reduction in 22-nm 8T SRAM J. Kulkarni, B. Geuskens, T. Karnik, M. Khellah, J. Tschanz, V. De Intel, Hillsboro, OR 2:00 PM

2:30 PM

13.4 A 28nm 360ps-Access-Time Two-Port SRAM with a Time-Sharing 2:45 PM Scheme to Circumvent Read Disturbs Y. Ishii1, Y. Tsukamoto1, K. Nii1, H. Fujiwara1, M. Yabuuchi1, K. Tanaka2, S. Tanaka1, Y. Shimazaki1 1 Renesas Electronics, Kodaira, Tokyo, Japan 2 Renesas Electronics, Itami, Hyogo, Japan Break 3:00 PM

29

SESSION 14

Tuesday February 21st, 3:15 PM

DIGITAL CLOCKING & PLLs

Session Chair: Associate Chair:

Anthony Hill, Texas Instruments, Dallas, TX Hiroo Hayashi, Toshiba Semiconductor, Kawasaki, Japan 3:15 PM

14.1 A 0.004mm2 250W TDC with Time-Difference Accumulator and a 0.012mm2 2.5mW Bang-Bang Digital PLL Using PRNG for Low-Power SoC Applications J-P. Hong, S-J. Kim, J. Liu, N. Xing, T-K. Jang, J. Park, J. Kim, T. Kim, H. Park Samsung Electronics, Yongin, Korea 14.2 A 1.5GHz 890W Digital MDLL with 400fsrms Integrated Jitter, -55.6dBc Reference Spur and 20fs/mV Supply-Noise Sensitivity Using 1b TDC A. Elshazly, R. Inti, B. Young, P. Hanumolu Oregon State University, Corvallis, OR 14.3 A 6.7MHz-to-1.24GHz 0.0318mm2 Fast-Locking All-Digital DLL in 90nm CMOS M-H. Hsieh, L-H. Chen, S-I. Liu, C-P. Chen National Taiwan University, Taipei, Taiwan 14.4 A TDC-Less ADPLL with 200-to-3200MHz Range and 3mW Power Dissipation for Mobile SoC Clocking in 22nm CMOS N. August, H-J. Lee, M. Vandepas, R. Parker Intel, Portland, OR 14.5 A Digitally Stabilized Type-III PLL Using Ring VCO with 1.01psrms Integrated Jitter in 65nm CMOS A. Sai, Y. Kobayashi, S. Saigusa, O. Watanabe, T. Itakura Toshiba, Kawasaki, Japan Conclusion

3:45 PM

4:15 PM

4:30 PM

4:45 PM

5:15 PM

30

SESSION 15
Session Chair: Associate Chair:

Tuesday February 21st, 1:30 PM

mm-WAVE & THz TECHNIQUES
Ehsan Afshari, Cornell University, Ithaca, NY Yorgos Palaskas, Intel, Hillsboro, OR

ADS 1:30 PM 15.1 A 1kPixel CMOS Camera Chip for 25fps Real-Time Terahertz Imaging Applications H. Sherry1,2,3, J. Grzyb2, Y. Zhao2, R. Al Hadi2, A. Cathelin1, A. Kaiser3, U. Pfeiffer2 1 STMicroelectronics, Crolles, France; 2University of Wuppertal, Wuppertal, Germany 3 IEMN / ISEN, Lille, France
15.2 280GHz and 860GHz Image Sensors Using Schottky-Barrier Diodes in 0.13m Digital CMOS R. Han1,2, Y. Zhang3, Y. Kim3, D. Kim3, H. Shichijo3, E. Afshari2, K. O3 1 University of Florida, Gainesville, FL; 2Cornell University, Ithaca, NY 3 University of Texas at Dallas, Richardson, TX 15.3 A 0.28THz 44 Power-Generation and Beam-Steering Array K. Sengupta, A. Hajimiri; California Institute of Technology, Pasadena, CA 15.4 A 283-to-296GHz VCO with 0.76mW Peak Output Power in 65nm CMOS Y. M. Tousi, O. Momeni, E. Afshari; Cornell University, Ithaca, NY Break 15.5 A 1V 19.3dBm 79GHz Power Amplifier in 65nm CMOS K-Y. Wang, T-Y. Chang, C-K. Wang National Taiwan University, Taipei, Taiwan 2:00 PM

2:30 PM

2:45 PM

3:00 PM 3:15 PM

15.6 A 9% Power Efficiency 121-to-137GHz Phase-Controlled 3:30 PM Push-Push Frequency Quadrupler in 0.13m SiGe BiCMOS Y. Wang1,2, W. Goh1, Y-Z. Xiong2,3 1 Nanyang Technological University, Singapore; 2Institute of Microelectronics, Singapore 3 MicroArray Technologies, Chengdu, China 15.7 A 144GHz 0.76cm-Resolution Sub-Carrier SAR Phase Radar 3:45 PM for 3D Imaging in 65nm CMOS A. Tang1, G. Virbila1, D. Murphy1, F. Hsiao1, Y. Wang1, Q. Gu2, Z. Xu3, Y. Wu4, M. Zhu1, M-C. Chang1 1 University of California, Los Angeles, Los Angeles, CA; 2University of Florida, Gainsville, FL 3 HRL, Malibu, CA; 4Northrop Grumman Aerospace Systems, Los Angeles, CA 15.8 A 2Gb/s-Throughput CMOS Transceiver Chipset with In-Package 4:15 PM Antenna for 60GHz Short-Range Wireless Communication T. Mitomo, Y. Tsutsumi, H. Hoshino, M. Hosoya, T. Wang, Y. Tsubouchi, R. Tachibana, A. Sai, Y. Kobayashi, D. Kurose, T. Ito, K. Ban, T. Tandai, T. Tomizawa Toshiba, Kawasaki, Japan 15.9 A Low-Power 57-to-66GHz Transceiver in 40nm LP CMOS 4:45 PM with -17dB EVM at 7Gb/s V. Vidojkovic1, G. Mangraviti1,2, K. Khalaf1,2, V. Szortyka1,2, K. Vaesen1, W. Van Thillo1, B. Parvais1, M. Libois1, S. Thijs1, J. Long3, C. Soens1, P. Wambacq1,2 1 imec, Heverlee, Belgium; 2Vrije Universiteit Brussel, Brussel, Belgium 3 Delft University of Technology, Delft, The Netherlands 15.10 A 4-Path 42.8-to-49.5GHz LO Generation with Automatic Phase Tuning for 60GHz Phased-Array Receivers L. Wu, A. Li, H. Luong Hong Kong University of Science and Technology, Hong Kong, China Conclusion 5:00 PM

5:15 PM

31

TIMETABLE OF ISSC
Sunday, February 19th
8:00AM 10:00AM 12:30PM 2:30PM T1: RF Mixers: Analysis & Design Trade-offs T3: Mobile GHz Processor Design Techniques T6: Power Management Using Integrated Voltage Regulators T8: Managing Offset & Flicker Noise

ISSCC
T2: Flash-Memory

T4: W

T7: Dig

T9: Getting In Touch

ISSCC
8:00AM F1: Beamforming Techniques & RF Transceiver Design

ISSCC 2012
7:30 PM ES1: Student Research Review: Poster Session with Short Presentations

What's Ne Session

Monday, February 20th

8:30AM 1:30PM 5:15PM Session 2: High Bandwidth DRAM & PRAM Session 3: Processors

ISSCC 2012

Session 4: RF Technique

Academic Demo Session (4-7), Author Interviews, Book Display, Social Hour

ISSCC 2
8:00PM ES3: Technologies that Could Change the World - You Decide!

ES4: Optical PCB Int

Tuesday, February 21st

8:30AM Session 7: Multi-Gb/s Receiver & Parallel I/O Techniques Session 12: Multimedia & Communications SoCs Session 8: Delta-Sigma Converters

ISSCC 2012

Session 9: Wireless Transceiver T

1:30PM

Session 13: High-Performance Embedded SRAM Session 14: Digital Clocking and PLLs

5:15PM

Industrial Demo Session (4-7), Author Interviews, Book Display, Social Hour

ISSCC 2012
8:00PM ES5: Vision for Future Television

EP2: Little-Known F

Wednesday, February 22nd

8:30AM Session 18: Innovated Circuits in Emerging Technologies Session 23: Advances in Heterogeneous Integration 1:30PM Session 24: 10G BaseT & Optical Frontends 5:15 PM Author Interviews

ISSCC 2012

Session 19: 20+Gb/s Wireline Tran Injection-Locked Cl

Session 25: Non-Volatile Memory

Thursday, February 23rd

8:00 AM

ISSCC 201

SC1: Low-Powe

ISSCC
8:00AM F3: 10-40 Gb/s I/O Design for Data Communications

F4: Computational Imaging

32

CC 2012 SESSIONS
Based Circuits, System, and Platform Design T5: Jitter: Basic & Advanced Concepts, Statistics, & Applications

2012 TUTORIALS

Wideband Delta-Sigma Modulators ital Calibration for RF Transceivers

h With MEMS: The Electromechanical Interface

2012 FORUMS
F2: Robust VLSI Circuit Design & System for a Sustainable Society

EVENING SESSIONS

8:00 PM ES2: ext in Robots? - Sensing, Processing, Networking Toward Human Brain & Body 1: Plenary Session Session 5: Audio & Power Converters Session 6: Medical, Displays & Imagers

2 PAPER SESSIONS

es

2012 SESSIONS
erconnects, Niche or Mainstream? EP1: Is RF Doomed to Digitization? - What Shall RF Circuit Designers Do?

2 PAPER SESSIONS
Session 10: High-Performance Digital Session 15: mm-Wave and THz Techniques Session 11: Sensors and MEMs Session 16: Switching Power Control Techniques Session 17: Diagnostic & Therapeutic Techologies for Health

Techniques

EVENING SESSIONS
EP3: What is the Next RF Frontier?

Features of Well-Known Creatures

2 PAPER SESSIONS
Session 20: RF Frequency Generation Session 26: Short-Range Wireless Transceivers Session 21: Analog Techniques Session 22: Image Sensors

: sceivers & locking

: Solutions

Session 27: Data Converter Techniques

Session 28: Adaptive & Low-Power Circuits

12 SHORT COURSE

er Analog Signal Processing

C 2012 FORUMS
F5: Bioelectronics for Sustainable Healthcare F6: Power/Performance Optimization of Many-Core Processor SoCs

33

SESSION 16

Tuesday February 21st, 1:30 PM

SWITCHING POWER CONTROL TECHNIQUES

Session Chair: Associate Chair: Baher Haroun, Texas Instruments, Dallas, TX Gyu-Hyeong Cho, KAIST, Daejeon, Korea 1:30 PM

16.1 Near Independently Regulated 5-Output Single-Inductor DC-DC Buck Converter Delivering 1.2W/mm2 in 65 nm CMOS C-W. Kuan, H-C. Lin MediaTek, Hsinchu, Taiwan 16.2 A High-Stability Emulated Absolute Current Hysteretic Control Single-Inductor 5-Output Switching DC-DC Converter with Energy Sharing and Balancing S-W. Wang1, G-H. Cho2, G-H. Cho1 1 KAIST, Daejeon, Korea 2 JDA, Daejeon, Korea 16.3 Off-the-Line Primary-Side Regulation LED Lamp Driver with Single-Stage PFC and TRIAC Dimming Using LED Forward Voltage and Duty Variation Tracking Control J. Hwang, M. Jung, D. Kim, J. Lee, M. Jung, J. Shin Anaperior Technology, Seoul, Korea Break 16.4 A 0.18m CMOS 91%-Efficiency 0.1-to-2A Scalable Buck-Boost DC-DC Converter for LED Drivers P. Malcovati1, M. Belloni1, F. Gozzini2, C. Bazzani2, A. Baschirotto3 1 University of Pavia, Pavia, Italy 2 Mindspeed, Newport Beach, CA 3 University of Milano-Bicocca, Milano, Italy 16.5 A 92% Efficiency Wide-Input Voltage Range Switched-Capacitor DC-DC Converter V. Ng, S. Sanders University of California at Berkeley, Berkeley, CA 16.6 An Optimized Driver for SiC JFET-Based Switches Delivering More Than 99% Efficiency K. Norling, C. Lindholm, D. Draxelmayr Infineon Technologies, Villach, Austria 16.7 An Adaptive Reconfigurable Active Voltage Doubler/Rectifier for Extended-Range Inductive Power Transmission H-M. Lee, M. Ghovanloo Georgia Institute of Technology, Atlanta, GA 16.8 Voltage-Boosting Wireless Power Delivery System with Fast Load Tracker by -Modulated Sub-Harmonic Resonant Switching R. Shinoda, K. Tomita, Y. Hasegawa, H. Ishikuro Keio University, Yokohama, Japan

2:00 PM

2:30 PM

3:00 PM 3:15 PM

3:45 PM

4:15 PM

4:45 PM

ADS

5:00 PM

Conclusion

5:15 PM

34

SESSION 17

Tuesday February 21st, 1:30 PM

DIAGNOSTIC & THERAPEUTIC TECHNOLOGIES FOR HEALTH

Session Chair: Associate Chair: Alison Burdett, Toumaz Technology, Abingdon, United Kingdom Fu-Lung Hsueh, TSMC, Hsinchu, Taiwan

17.1 An 8-Channel Scalable EEG Acquisition SoC with Fully Integrated 1:30 PM Patient-Specific Seizure Classification and Recording Processor J. Yoo1, L. Yan2, D. El-Damak3, M. Bin Altaf1, A. Shoeb4, H-J. Yoo5, A. Chandrakasan3 1 Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates 2 imec, Leuven, Belgium 3 Massachusetts Institute of Technology, Cambridge, MA 4 Massachusetts General Hospital, Harvard Medical School, Cambridge, MA 5 KAIST, Daejeon, Korea 17.2 A 259.6W Nonlinear HRV-EEG Chaos Processor with Body Channel Communication Interface for Mental Health Monitoring T. Roh, S. Hong, H. Cho, H-J. Yoo KAIST, Daejeon, Korea 17.3 A Sub-10nA DC-Balanced Adaptive Stimulator IC with Multimodal Sensor for Compact Electro-Acupuncture System K. Song, H. Lee, S. Hong, H. Cho, H-J. Yoo KAIST, Daejeon, Korea

ADS

2:00 PM

ADS

2:30 PM

Break

3:00 PM

17.4 A Batteryless 19W MICS/ISM-Band Energy Harvesting 3:15 PM Body Area Sensor Node SoC F. Zhang1, Y. Zhang2, J. Silver1, Y. Shakhsheer2, M. Nagaraju1, A. Klinefelter2, J. Pandey1, J. Boley2, E. Carlson1, A. Shrivastava2, B. Otis1, B. Calhoun2 1 University of Washington, Seattle, WA 2 University of Virginia, Charlottesville, VA 17.5 A 1V 5mA Multimode IEEE 802.15.6/Bluetooth Low-Energy WBAN Transceiver for Biotelemetry Applications A. Wong, M. Dawkins, G. Devita, N. Kasparidis, A. Katsiamis, O. King, F. Lauria, J. Schiff, A. Burdett Toumaz, Abingdon, United Kingdom 17.6 A mm-Sized Wirelessly Powered and Remotely Controlled Locomotive Implantable Device A. Yakovlev, D. Pivonka, T. Meng, A. Poon Stanford University, Stanford, CA 17.7 A CMOS Impedance Cytometer for 3D Flowing Single-Cell Real-Time Analysis with Error Correction K-H. Lee1, J. Nam2, S. Choi1, H. Lim2, S. Shin2, G-H. Cho1 1 KAIST, Daejeon, Korea 2 Korea University, Seoul, Korea Conclusion 3:45 PM

4:15 PM

4:45 PM

5:15 PM

35

INDUSTRY DEMONSTRATION SESSION (IDS)

ISSCC 2012 continues this year with the Industry Demonstration Session (IDS), to be held on Tuesday February 21st, from 4 to 7 pm, Golden Gate Hall. IDS will feature live demonstrations of selected ICs presented by industry in regular paper sessions. IDS is intended to demonstrate real-life applications made possible by new ICs presented this year. In the Advance Program, papers for which demonstrations are available will be notated by the symbol IDS. IDS

Monday, February 20th

3.1 3.6 A 22nm IA Multi-CPU and GPU System-on-Chip A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor in 32nm CMOS An 8 2.5W 1%-THD 104dB(A)-Dynamic-Range Class-D Audio Amplifier with an Ultra-Low EMI System and Current Sensing for Speaker Protection A 330nA Energy-Harvesting Charger with Battery Management for Solar and Thermoelectric Energy Harvesting A 160A Biopotential Acquisition ASIC with Fully Integrated IA and Motion-Artifact Suppression 1:30 PM 4:15 PM

5.1

1:30 PM

5.8

4:45 PM

6.5

3:15 PM

Tuesday, February 21st

7.5 A 4.1pJ/b 16Gb/s Coded Differential Bidirectional Parallel Electrical Link 10:45 AM

10.3 A 1.45GHz 52-to-162GFLOPS/W Variable-Precision Floating-Point Fused Multiply-Add Unit with Certainty Tracking in 32nm CMOS 11.6 A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator with Better Than 0.5ppm Frequency Stability 12.1 A 32nm High-k Metal Gate Application Processor with GHz Multi-Core CPU 12.5 A 464GOPS 620GOPS/W Heterogeneous Multi-Core SoC for Image-Recognition Applications 12.7 A True Multistandard, Programmable, Low-Power, Full HD Video-Codec Engine for Smartphone SoC

9:30 AM

10:45 AM

1:30 PM

3:45 PM

4:45 PM

Wednesday, February 22nd

19.3 A 40nm CMOS Single-Chip 50Gb/s DP-QPSK/BPSK Transceiver with Electronic Dispersion Compensation for Coherent Optical Channels 22.9 A 19201080 3.65m-Pixel 2D/3D Image Sensor with Split and Binning Pixel Structure in 0.11m Standard CMOS 26.6 A Meter-Range UWB Transceiver Chipset for Around-the-Head Audio Streaming 26.8 A 915MHz 120W-RX/900W-TX Envelope-Detection Transceiver with 20dB In-Band Interference Tolerance 9:30 AM

12:00 PM

4:15 PM

5:00 PM

36

EVENING SESSIONS
ES5:
Organizer:

Tuesday February 21st, 8:00 PM

Vision for Future Television

Atsuki Inoue, Fujitsu Laboratories, Kawasaki, Japan Masaitsu Nakajima, Panasonic, Moriguchi, Japan Masaitsu Nakajima, Panasonic, Moriguchi, Japan

Chair:

Until recently, TV technology (e.g. analog color TV and broadcast by air) was seen to have matured. However, the introduction of digital TV technology, including high-speed IP-based networking, has given consumers additional freedom to view content, and is presenting new technological challenges. Users experience this freedom through multiple types of devices and sources of content. The introduction of 3D imaging displays represents a great advance for TV receiver equipment. However, the gap between current TV capabilities and customer demand remains large and additional technology is necessary. The aim of this Evening Session is to discuss future technologies that could close the customer demand gap, from the viewpoints of service, platform and device.

Time 8:00 8:30 9:00 9:30

Topic Television Futures Brendan Traw, Intel, Portland, OR 3D and Smart TV in the Future David K. Min, LG Electronics, Seoul, Korea Glasses-Free 3D Technologies for Future Digital TV Systems Yuzo Hirayama, Toshiba, Kawasaki, Japan FTV (Free-Viewpoint Television) as the Ultimate 3D TV Masayuki Tanimoto, Nagoya University, Nagoya, Japan

37

EVENING SESSIONS
EP2:
Organizer: Co-Organizer: Moderator:

Tuesday February 21st, 8:00 PM

Little-Known Features of Well-Known Creatures

Un-Ku Moon, Oregon State University, Corvallis, OR Shanthi Pavan, Indian Institute of Technology, Madras, India Shanthi Pavan, Indian Institute of Technology, Madras, India

This panel discussion will feature experts from academia and industry, spanning the broad landscape of solid state circuits - analog, digital, microwave, mixed signal and RF. They will unleash their bag of tricks - things you thought you knew, but probably did not quite appreciate, an interesting way of looking at a well known circuit or a system, a less known facet of a commonly used idea, little known facts now finding increasing application

Panelists: Asad A. Abidi, University of California, Los Angeles, CA A. Paul Brokaw, Integrated Device Technology, Tucson, AZ Rinaldo Castello, University of Pavia, Pavia, Italy Mark Horowitz, Stanford University, Stanford, CA Thomas H. Lee, DARPA, Arlington, VA David Robertson, Analog Devices, Wilmington, MA

EP3:
Organizer: Co-Organizer:

What is the Next RF Frontier?

Gangadhar Burra, Texas Instruments, Dallas, TX Hossein Hashimi, University of Southern California, Los Angeles, CA Gangadhar Burra, Texas Instruments, Dallas, TX

Moderator:

What are the next BIG ideas in wireless communications? What will you see at ISSCC, five years from now? Will these new ideas be adopted by consumers? A panel of experts will make their predictions, focusing on applications ranging from low power to high speed, including: Medical RF/nano-power after tele-health, what is next? Energy-scavenged ultra-lowpower wireless techniques and integrated bio-sensors may become the frontier for the next generation of wireless technologies. mm-Wave & TerraHertz ultra-high-frequency RF circuits beyond mm-Wave frequencies show promise in medical (diagnostic), security and consumer applications. Connected home is Internet of Things going to be viable what are the challenges?

Panelists: Jan Rabaey, University of California at Berkeley, Berkeley, CA Jerald Yoo, Masdar Institute of Science & Technology, Abu Dhabi, UAE Chris Toumazou, Imperial College, London, United Kingdom Ullrich Pfeiffer, University of Wuppertal, Wuppertal, Germany Ajith Amerasekera, Texas Instruments, Dallas, TX Inyup Kang, Samsung Electronics, Gyeonggi-do, South Korea

38

SESSION 18

Wednesday February 22nd, 8:30 AM

INNOVATIVE CIRCUITS IN EMERGING TECHNOLOGIES

Session Chair: Associate Chair: Masaitsu Nakajima, Panasonic, Moriguchi, Japan Shekhar Borkar, Intel, Hillsboro, OR

18.1 Insole Pedometer with Piezoelectric Energy Harvester 8:30 AM and 2V Organic Digital and Analog Circuits K. Ishida1, T-C. Huang1, K. Honda1, Y. Shinozuka1, H. Fuketa1, T. Yokota1, U. Zschieschang2, H. Klauk2, G. Tortissier1, T. Sekitani1,3, M. Takamiya1, H. Toshiyoshi1, T. Someya1,3, T. Sakurai1 1 University of Tokyo, Tokyo, Japan 2 Max Planck Institute for Solid State Research, Stuttgart, Germany 3 JST/ERATO, Tokyo, Japan 18.2 1D and 2D Analog 1.5kHz Air-Stable Organic Capacitive Touch Sensors on Plastic Foil H. Marien1, M. Steyaert1, E. Van Veenendael2, P. Heremans1,3 1 KU Leuven, Heverlee, Belgium 2 Polymer Vision, Eindhoven, The Netherlands 3 imec, Heverlee, Belgium 9:00 AM

18.3 Bidirectional Communication in an HF Hybrid 9:30 AM Organic/Solution-Processed Metal-Oxide RFID Tag K. Myny1,2, M. Rockel1,2, A. Chasin1,2, D-V. Pham3, J. Steiger3, S. Botnaras3, D. Weber3, B. Herold4, J. Ficker4, B. Van der Putten5, G. Gelinck5, J. Genoe1,6, W. Dehaene1,2, P. Heremans1,2 1 imec, Leuven, Belgium; 2KU Leuven, Leuven, Belgium 3 Evonik Degussa, Marl, Germany; 4PolyIC, Frth, Germany 5 Holst Centre/TNO, Eindhoven, The Netherlands; 6KHLim, Diepenbeek, Belgium Break 10:00 AM

18.4 A 6b 10MS/s Current-Steering DAC Manufactured 10:15 AM with Amorphous Gallium-Indium-Zinc-Oxide TFTs Achieving SFDR > 30dB up to 300kHz D. Raiteri1, F. Torricelli1, K. Myny2, M. Nag2, B. Van der Putten3, E. Smits3, S. Steudel2, K. Tempelaars3, A. Tripathi3, G. Gelinck3, A. Van Roermund1, E. Cantatore1 1 Eindhoven University of Technology, Eindhoven, The Netherlands 2 imec, Leuven, Belgium 3 TNO Science and Industry, Eindhoven, The Netherlands 18.5 A Low-Overhead Self-Healing Embedded System for 10:45 AM Ensuring High Yield and Long-Term Sustainability of 60GHz 4Gb/s Radio-on-a-Chip A. Tang1, F. Hsiao1, D. Murphy1, I-N. Ku1, J. Liu1, S. DSouza1, N-Y. Wang1, H. Wu1, Y-H. Wang1, M. Tang1, G. Virbila1, M. Pham1, D. Yang1, Q. Gu2, Y-C. Wu1, Y-C. Kuan1, C. Chien3, M-C. Chang1 1 University of California, Los Angeles, Los Angeles, CA 2 University of Florida, Gainsville, FL 3 CreoNex Systems, Westlake Village, CA 18.6 Power-Efficient Readout Circuit for Miniaturized Electronic Nose 11:15 AM V. Petrescu, J. Pettine, D. Karabacak, M. Vandecasteele, M. Crego Calama, C. Van Hoof imec - Holst Centre, Eindhoven, The Netherlands 18.7 Towards Ultra-Dense Arrays of VHF NEMS with FDSOI-CMOS 11:45 AM Active Pixels for Sensing Applications G. Arndt, C. Dupr, J. Arcamone, G. Cibrario, O. Rozeau, L. Duraffourg, E. Ollier, E. Colinet CEA-LETI-MINATEC, Grenoble, France Conclusion 12:00 PM

39

SESSION 19

Wednesday February 22nd, 8:30 AM

20+GB/S WIRELINE TRANSCEIVERS & INJECTION-LOCKED CLOCKING

Session Chair: Associate Chair: Ken Chang, Xilinx, San Jose, CA SeongHwan Cho, KAIST, Daejeon, Korea

19.1 A 28Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver 8:30 AM in 32nm SOI CMOS Technology J. Bulzacchelli1, T. Beukema1, D. Storaska2, P-H. Hsieh1,3, S. Rylov1, D. Furrer4, D. Gardellini4, A. Prati4, C. Menolfi5, D. Hanson2, J. Hertle4, T. Morf5, V. Sharma4, R. Kelkar6, H. Ainspan1, W. Kelly2, G. Ritter2, J. Garlett2, R. Callan2, T. Toifl5, D. Friedman1 1 IBM Research, Yorktown Heights, NY 2 IBM Systems and Technology Group, Hopewell Junction, NY 3 National Tsing Hua University, Hsinchu, Taiwan; 4Miromico, Zurich, Switzerland 5 IBM Research, Zurich, Switzerland 6 IBM Systems and Technology Group, Essex Junction, VT 19.2 A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB 9:00 AM of Analog Equalization for 100GBASE-LR4 and Optical Transport Lane 4.4 Applications M. Harwood1, S. Nielsen2, A. Szczepanek1, R. Allred2, S. Batty1, M. Case2, S. Forey1, K. Gopalakrishnan3, L. Kan3, B. Killips1, P. Mishra2, R. Pande3, H. Rategh3, A. Ren3, J. Sanders2, A. Schoy3, R. Ward3, M. Wetterhorn2, N. Yeung2 1 Inphi, Northampton, United Kingdom; 2Inphi, Westlake Village, CA 3 Inphi, Santa Clara, CA 19.3 A 40nm CMOS Single-Chip 50Gb/s DP-QPSK/BPSK IDS 9:30 AM Transceiver with Electronic Dispersion Compensation for Coherent Optical Channels D. Crivelli1,2, M. Hueda1,2, H. Carrer1,2, J. Zachan3, V. Gutnik3, M. Del Barco1, R. Lopez1, G. Hatcher3, J. Finochietto2, M. Yeo3, A. Chartrand3, N. Swenson3, P. Voois3, O. Agazzi1,3 1 ClariPhy, Cordoba, Argentina; 2National University of Cordoba, Cordoba, Argentina 3 ClariPhy, Irvine, CA Break 10:00 AM 19.4 A Dual 23Gb/s CMOS Transmitter/Receiver Chipset 10:15 AM for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK Optical Transmission D. Cui, B. Raghavan, U. Singh, A. Vasani, Z. Huang, M. Khanpour, A. Nazemi, H. Maarefi, T. Ali, N. Huang, W. Zhang, B. Zhang, A. Momtaz, J. Cao Broadcom, Irvine, CA 19.5 A Versatile Multi-Modality Serial Link 10:45 AM Y. Tanaka1, Y. Hino1, Y. Okada1, T. Takeda1, S. Ohashi1, H. Yamagishi1, K. Kawasaki1, A. Hajimiri2 1 Sony, Tokyo, Japan; 2California Institute of Technology, Pasadena, CA 19.6 A 28Gb/s Source-Series Terminated TX in 32nm CMOS SOI 11:15 AM C. Menolfi1, J. Hertle2, T. Toifl1, T. Morf1, D. Gardellini2, M. Braendli1, P. Buchmann1, M. Kossel1 1 IBM, Rueschlikon, Switzerland; 2Miromico, Zurich, Switzerland 19.7 An All-Digital Clock Generator Using a Fractionally Injection-Locked Oscillator in 65nm CMOS P. Park1, H. Park2, J. Park2, S. Cho1 1 KAIST, Daejeon, Korea; 2Samsung Electronics, Yongin, Korea 19.8 A 2.4GHz Sub-Harmonically Injection-Locked PLL with Self-Calibrated Injection Timing Y-C. Huang, S-I. Liu; National Taiwan University, Taipei, Taiwan Conclusion 11:30 AM

11:45 AM

12:15 PM

40

SESSION 20

Wednesday February 22nd, 8:30 AM

RF FREQUENCY GENERATION

Session Chair: Associate Chair:

Bogdan Staszewski, TU Delft, Delft, The Netherlands Taizo Yamawaki, Renesas Mobile, Takasaki, Japan 8:30 AM

20.1 A 20Mb/s Phase Modulator Based on a 3.6GHz Digital PLL with -36dB EVM at 5mW Power G. Marzin, S. Levantino, C. Samori, A. Lacaita Politecnico di Milano, Milan, Italy 20.2 A 14.2mW 2.55-to-3GHz Cascaded PLL with Reference Injection, 800MHz Delta-Sigma Modulator and 255fsrms Integrated Jitter in 0.13m CMOS D. Park, S. Cho KAIST, Daejeon, Korea 20.3 A 40nm CMOS All-Digital Fractional-N Synthesizer without Requiring Calibration F. Opteynde, F. Opteynde Audax-Technologies, Leuven, Belgium Break 20.4 A 36mW/9mW Power-Scalable DCO in 55nm CMOS for GSM/WCDMA Frequency Synthesizers A. Liscidini1, L. Fanori1, P. Andreani2, R. Castello1 1 University of Pavia, Pavia, Italy 2 Lund University, Lund, Sweden 20.5 A Clip-and-Restore Technique for Phase Desensitization in a 1.2V 65nm CMOS Oscillator for Cellular Mobile and Base Stations A. Visweswaran, R. Staszewski, J. Long Delft University of Technology, Delft, The Netherlands 20.6 A 32nm CMOS All-Digital Reconfigurable Fractional Frequency Divider for LO Generation in Multistandard SoC Radios with On-the-Fly Interference Management K. Chandrashekar, S. Pellerano, P. Madoglio, A. Ravi, Y. Palaskas Intel, Hillsboro, OR 20.7 A 6.7-to-9.2GHz 55nm CMOS Hybrid Class-B/Class-C Cellular TX VCO L. Fanori1,2, A. Liscidini1, P. Andreani2 1 University of Pavia, Pavia, Italy 2 Lund University, Lund, Sweden Conclusion

9:00 AM

9:30 AM

10:00 AM 10:15 AM

10:45 AM

11:15 AM

11:45 AM

12:15 PM

41

SESSION 21

Wednesday February 22nd, 8:30 AM

ANALOG TECHNIQUES

Session Chair: Associate Chair:

Jafar Savoj, Xilinx, San Jose, CA Chris Mangelsdorf, Analog Devices, Tokyo, Japan 8:30 AM

21.1 A 0.3-to-1.2GHz Tunable 4th-Order Switched gm-C Bandpass Filter with >55dB Ultimate Rejection and Out-of-Band IIP3 of +29dBm M. Darvishi, R. Van der Zee, E. Klumperink, B. Nauta University of Twente, Enschede, The Netherlands 21.2 A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4th-Order Butterworth Filter Using Ring-Oscillator-Based Integrators in 90nm CMOS B. Drost1, M. Talegaonkar2, P. Hanumolu2 1 Silicon Laboratories, Corvallis, OR; 2Oregon State University, Corvallis, OR 21.3 A 65nm CMOS 1-to-10GHz Tunable Continuous-Time Lowpass Filter for High-Data-Rate Communications F. Houfaf1,2,3, M. Egot1, A. Kaiser2, A. Cathelin1, B. Nauta3 1 STMicroelectronics, Crolles, France; 2IEMN / ISEN, Lille, France 3 University of Twente, Enschede, The Netherlands 21.4 A 0.0025mm2 Bandgap Voltage Reference for 1.1V Supply in Standard 0.16m CMOS A-J. Annema1, G. Goksun2 1 University of Twente, Enschede, The Netherlands 2 Anagear B.V., Rosmalen, The Netherlands Break 21.5 A 5.58nW 32.768kHz DLL-Assisted XO for Real-Time Clocks in Wireless Sensing Applications D. Yoon, D. Sylvester, D. Blaauw; University of Michigan, Ann Arbor, MI 21.6 A 0.016mm2 144W Three-Stage Amplifier Capable of Driving 1-to-15nF Capacitive Load with >0.95MHz GBW Z. Yan1, P-I. Mak1, M-K. Law1, R. Martins1,2 1 University of Macau, Macau, China 2 Instituto Superior Tecnico, Lisbon, Portugal 21.7 A 90Vpp 720MHz GBW Linear Power Amplifier for Ultrasound Imaging Transmitters in BCD6-SOI D. Bianchi1, F. Quaglia2, A. Mazzanti1, F. Svelto1 1 University of Pavia, Pavia, Italy; 2STMicroelectronics, Cornaredo, Italy 21.8 On-Chip Gain Reconfigurable 1.2V 24W Chopping Instrumentation Amplifier with Automatic Resistor Matching in 0.13m CMOS F. Michel, M. Steyaert; KU Leuven, Leuven, Belgium

9:00 AM

9:30 AM

9:45 AM

10:00 AM 10:15 AM

10:45 AM

11:15 AM

11:30 AM

21.9 A Capacitively Coupled Chopper Instrumentation Amplifier 11:45 AM with a 30V Common-Mode Range, 160dB CMRR and 5V Offset Q. Fan, J. Huijsing, K. Makinwa; Delft University of Technology, Delft, The Netherlands 21.10 A 60V Capacitive-Gain 27nV/Hz 137dB CMRR PGA with 10V Inputs C. Birk1, G. Mora-Puchalt2 1 Analog Devices, Cork, Ireland; 2Analog Devices, Valencia, Spain Conclusion 12:00 PM

12:15 PM

42

SESSION 22
Session Chair: Associate Chair:

Wednesday February 22nd, 8:30 AM

IMAGE SENSORS
David Stoppa, Fondazione Bruno Kessler, Trento, Italy Robert Johansson, Aptina Imaging, Oslo, Norway

22.1 An 83dB-Dynamic-Range Single-Exposure Global-Shutter 8:30 AM CMOS Image Sensor with In-Pixel Dual Storage M. Sakakibara1, Y. Oike1, T. Takatsuka1, A. Kato1, K. Honda1, T. Taura1, T. Machida1, J. Okuno2, A. Ando2, T. Fukuro2, T. Asatsuma1, S. Endo2, J. Yamamoto2, Y. Nakano2, T. Kaneshige2, I. Yamamura1, T. Ezaki1, T. Hirayama1 1 Sony, Atsugi, Japan; 2Sony Semiconductor, Kumamoto, Japan 22.2 A Global-Shutter CMOS Image Sensor with Readout ADS 9:00 AM Speed of 1Tpixel/s Burst and 780Mpixel/s Continuous Y. Tochigi1, K. Hanzawa1, Y. Kato1, R. Kuroda1, H. Mutoh2, R. Hirose3, H. Tominaga3, K. Takubo3, Y. Kondo3, S. Sugawa1 1 Tohoku University, Sendai, Japan; 2Link Research, Odawara, Japan; 3Shimadzu, Kyoto, Japan 22.3 A 0.7e-rms-Temporal-Readout-Noise CMOS Image Sensor for Low-Light-Level Imaging Y. Chen1, Y. Xu1, Y. Chae1, A. Mierop2, X. Wang3, A. Theuwissen1,4 1 Delft University of Technology, Delft, The Netherlands 2 Teledyne DALSA Semiconductors, Eindhoven, The Netherlands 3 CMOSIS NV, Antwerp, Belgium; 4Harvest Imaging, Bree, Belgium Break 9:30 AM

10:00 AM

22.4 A 256256 CMOS Image Sensor with -Based 10:15 AM Single-Shot Compressed Sensing Y. Oike1,2, A. El Gamal1; 1Stanford University, Stanford, CA; 2Sony, Atsugi, Japan 22.5 A 33Mpixel 120fps CMOS Image Sensor Using 12b 10:45 AM Column-Parallel Pipelined Cyclic ADCs T. Watabe1, K. Kitamura1, T. Sawamoto2, T. Kosugi3, T. Akahori3, T. Iida3, K. Isobe3, T. Watanabe3, H. Shimamoto1, H. Ohtake1, S. Aoyama3, S. Kawahito2,3, N. Egami1 1 NHK Science & Technology Research Laboratories, Tokyo, Japan 2 Shizuoka University, Hamamatsu, Japan; 3Brookman Technology, Hamamatsu, Japan 22.6 A 14b Extended Counting ADC Implemented in a 24MPixel 11:00 AM APS-C CMOS Image Sensor J-H. Kim, W-K. Jung, S-H. Lim, Y-J. Park, W-H. Choi, Y-J. Kim, C-E. Kang, J-H. Shin, K-J. Choo, W-B. Lee, J-K. Heo, B-J. Kim, S-J. Kim, M-H. Kwon, K-S. Yoo, J-H. Seo, S-H. Ham, C-Y. Choi, G-S. Han Samsung Electronics, Yongin, Korea 22.7 A 1.5Mpixel RGBZ CMOS Image Sensor for Simultaneous 11:15 AM Color and Range Image Capture W. Kim1, W. Yibing2, I. Ovsiannikov2, S. Lee1, Y. Park1, C. Chung1, E. Fossum1,2 1 Samsung Electronics, Hwasung, Korea; 2Samsung Semiconductor, Pasadena, CA 22.8 A QVGA-Range Image Sensor Based on Buried-Channel Demodulator Pixels in 0.18m CMOS with Extended Dynamic Range L. Pancheri, N. Massari, M. Perenzoni, M. Malfatti, D. Stoppa Fondazione Bruno Kessler, Trento, Italy 22.9 A 19201080 3.65m-Pixel 2D/3D Image Sensor with IDS Split and Binning Pixel Structure in 0.11m Standard CMOS S-J. Kim, B. Kang, J. Kim, K. Lee, C-Y. Kim, Kinam Kim Samsung Advanced Institute of Technology, Yongin, Korea Conclusion 11:45 AM

12:00 PM

12:15 PM

43

SESSION 23
Session Chair: Associate Chair:

Wednesday February 22nd, 1:30 PM

Tadahiro Kuroda, Keio University, Yokohama, Japan David Ruffieux, CSEM, Neuchatel, Switzerland

ADVANCES IN HETEROGENEOUS INTEGRATION

23.1 A 2.5D Integrated Voltage Regulator Using 1:30 PM Coupled-Magnetic-Core Inductors on Silicon Interposer Delivering 10.8A/mm2 N. Sturcken1, E. OSullivan2, N. Wang2, P. Herget3, B. Webb2, L. Romankiw2, M. Petracca1, R. Davies1, R. Fontana3, G. Decad3, I. Kymissis1, A. Peterchev4, L. Carloni1, W. Gallagher2, K. Shepard1 1 Columbia University, New York, NY 2 IBM T. J. Watson, Yorktown Heights, NY 3 IBM Almaden Research Center, San Jose, CA 4 Duke University, Durham, NC 23.2 A Modular 1mm3 Die-Stacked Sensing Platform with Optical Communication and Multi-Modal Energy Harvesting Y. Lee, G. Kim, S. Bang, Y. Kim, I. Lee, P. Dutta, D. Sylvester, D. Blaauw University of Michigan, Ann Arbor, MI 23.3 A DC-Isolated Gate Drive IC with Drive-by-Microwave Technology for Power Switching Devices S. Nagai, N. Negoro, T. Fukuda, N. Otsuka, H. Sakai, T. Ueda, T. Tanaka, D. Ueda Panasonic, Seika, Japan 23.4 Nonvolatile 3D-FPGA with Monolithically Stacked RRAM-Based Configuration Memory Y. Yang Liauw, Z. Zhang, W. Kim, A. El Gamal, S. Wong Stanford University, Stanford, CA Break 2:00 PM

2:30 PM

2:45 PM

3:00 PM

44

SESSION 24

Wednesday February 22nd, 3:15 PM

10GBASE-T & Optical Frontends

Session Chair: Associate Chair:

Miki Moyal, Intel, Bet Hananya, Israel Chewnpu Jou, TSMC, Hsinchu, Taiwan 3:15 PM

24.1 A Sub-2W 10GBASE-T Analog Front-End in 40nm CMOS process T. Gupta1, F. Yang1, D. Wang1, A. Tabatabaei1, R. Singh1, H. Aslanzadeh1, A. Khalili1, S. Vats1, S. Arno1, S. Campeau2 1 Applied Micro, Sunnyvale, CA 2 Applied Micro, Kanata, ON, Canada 24.2 A 16-Port FCC-Compliant 10GBASE-T Transmitter and Hybrid with 76dBc SFDR up to 400MHz Scalable to 48 Ports F. Gerfers, R. Farjad, M. Brown, A. Tavakoli, D. Nguyen, H-T. Ng, R. Shirani Aquantia, Milpitas, CA 24.3 A 10Gb/s Burst-Mode Laser Diode Driver for Burst-by-Burst Power Saving H. Koizumi, M. Togashi, M. Nogawa, Y. Ohtomo NTT, Atsugi, Japan

3:45 PM

4:00 PM

24.4 A 10Gb/s Burst-Mode TIA with On-Chip Reset/Lock CM 4:15 PM Signaling Detection and Limiting Amplifier with a 75ns Settling Time X. Yin1, J. Put1, J. Verbrugghe1, J. Gillis1, X-Z. Qiu1, J. Bauwelinck1, J. Vandewege1, H-G. Krimmel2, M. Achouche3 1 imec - Ghent University, Gent, Belgium 2 Bell Laboratories, Stuttgart, Germany 3 III-V Lab, Marcoussis, France 24.5 25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-Based Optical Links in 90nm CMOS J. Proesel, C. Schow, A. Rylyakov IBM T. J. Watson, Yorktown Heights, NY Conclusion 4:45 PM

5:15 PM

45

SESSION 25

Wednesday February 22nd, 1:30 PM

NON-VOLATILE MEMORY SOLUTIONS

Session Chair: Associate Chair:

Tadaaki Yamauchi, Renesas Electronics, Itami, Japan Satoru Hanzawa, Hitachi Central Research Laboratory, Tokyo, Japan 1:30 PM

25.1 A 19nm 112.8mm2 64Gb Multi-Level Flash Memory with 400Mb/s/pin 1.8V Toggle Mode Interface

N. Shibata1, K. Kanda1, T. Hisada1, K. Isobe1, M. Sato1, Y. Shimizu1, T. Shimizu1, T. Sugimoto1, T. Kobayashi1, K. Inuzuka1, N. Kanagawa1, Y. Kajitani1, T. Ogawa1, J. Nakai1, K. Iwasa1, M. Kojima1, T. Suzuki1, Y. Suzuki1, S. Sakai1, T. Fujimura1, Y. Utsunomiya1, T. Hashimoto1, M. Miakashi1, N. Kobayashi1, M. Inagaki1, Y. Matsumoto1, S. Inoue1, Y. Suzuki1, D. He1, Y. Honda1, J. Musha1, M. Nakagawa1, M. Honma1, N. Abiko1, M. Koyanagi1, M. Yoshihara1, K. Ino1, M. Noguchi1, T. Kamei2, Y. Kato2, S. Zaitsu2, H. Nasu2, T. Ariki2, H. Chibvongodze2, M. Watanabe2, H. Ding2, N. Ookuma2, R. Yamashita2, G. Liang2, G. Hemink2, F. Moogat2, C. Trinh2, M. Higashitani2, T. Pham2, K. Kanazawa1 1 Toshiba, Yokohama, Japan; 2Sandisk, Milpitas, CA

25.2 Over-10-Extended-Lifetime 76%-Reduced-Error Solid-State Drives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme
S. Tanakamaru, Y. Yanagihara, K. Takeuchi; University of Tokyo, Tokyo, Japan

ADS

2:00 PM

25.3 6.4Gb/s Multi-Threaded BCH Encoder and Decoder for Multi-Channel SSD Controllers
Y. Lee, H. Yoo, I. Yoo, I-C. Park; KAIST, Daejeon, Korea

2:30 PM

25.4 Bitline-Capacitance-Cancelation Sensing Scheme with 11ns Read Latency and Maximum Read Throughput of 2.9GB/s in 65nm Embedded Flash for Automotive
M. Jefremow1,2, T. Kern1, U. Backhausen1, C. Peters1, C. Parzinger1, C. Roll1, S. Kassenetter1, S. Thierold1, D. Schmitt-Landsiedel2 1 Infineon, Neubiberg, Germany; 2Technical University Munich, Munich, Germany

2:45 PM

Break 25.5 A 64Gb 533Mb/s DDR Interface MLC NAND Flash in Sub-20nm Technology

3:00 PM 3:15 PM

D. Lee, I. Chang, S-Y. Yoon, J. Jang, D-S. Jang, W-G. Hahn, J-Y. Park, D-G. Kim, C. Yoon, B-S. Lim, B-J. Min, S-W. Yun, J-S. Lee, I-H. Park, K-R. Kim, J-Y. Yun, Y. Kim, Y-S. Cho, K-M. Kang, S-H. Joo, J-Y. Chun, J-N. Im, S. Kwon, S. Ham, A. Park, J-D. Yu, N-H. Lee, T-S. Lee, M. Kim, H. Kim, K-W. Song, B-G. Jeon, K. Choi, J-M. Han, K. Kyung, Y-H. Lim, Y-H. Jun Samsung Electronics, Hwasung, Korea

25.6 An 8Mb Multi-Layered Cross-Point ReRAM Macro with 443MB/s Write Throughput

3:45 PM

A. Kawahara1, R. Azuma1, Y. Ikeda1, K. Kawai1, Y. Katoh1, K. Tanabe2, T. Nakamura2,Y. Sumimoto2, N. Yamada2, N. Nakai2, S. Sakamoto2, Y. Hayakawa1, K. Tsuji1, S. Yoneda1, A. Himeno1, K-I. Origasa2, K. Shimakawa1, T. Takagi1, T. Mikawa1, K. Aono1 1 Panasonic, Moriguchi, Japan; 2Panasonic, Nagaokakyo, Japan

25.7 A 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using Low-Voltage Current-Mode Sensing Scheme with 45ns Random Read Time
M-F. Chang1, C-W. Wu1, C-C. Kuo1, S-J. Shen1, K-F. Lin2, S-M. Yang1, Y-C. King1, C-J. Lin1, Y-D. Chih2 1 National Tsing Hua University, Hsinchu, Taiwan; 2TSMC, Hsinchu, Taiwan

4:15 PM

25.8 128Gb 3b/Cell NAND Flash Memory in 19nm Technology with 18MB/s Write Rate and 400Mb/s Toggle Mode

4:45 PM

Y. Li1, S. Lee1, K. Oowada1, H. Nguyen1, Q. Nguyen1, N. Mokhlesi1, C. Hsu1, J. Li1, V. Ramachandra1, T. Kamei1, M. Higashitani1, T. Pham1, M. Honma2, Y. Watanabe2, K. Ino2, B. Le1, B. Woo1, K. Htoo1, T-Y. Tseng1, L. Pham1, F. Tsai1, K-H. Kim1, Y-C. Chen1, M. She1, J. Yuh1, A. Chu1, C. Chen1, R. Puri1, H-S. Lin1, Y-F. Chen1, W. Mak1, J. Huynh1, J. Chan1, M. Watanabe1, D. Yang1, G. Shah1, P. Souriraj1, D. Tadepalli1, S. Tenugu1, R. Gao1, V. Popuri1, B. Azarbayjani1, R. Madpur1, J. Lan1, E. Yero1, F. Pan1, P. Hong1, J. Kang1, F. Moogat1, Y. Fong1, R. Cernea1, S. Huynh1, C. Trinh1, M. Mofidi1, R. Shrivastava1, K. Quader1 1 Sandisk, Milpitas, CA; 2Toshiba Semiconductor, Yokohama, Japan

Conclusion

5:15 PM

46

SESSION 26

Wednesday February 22nd, 1:30 PM

SHORT-RANGE WIRELESS TRANSCEIVERS

Session Chair: Associate Chair: Ranjit Gharpurey, University of Texas at Austin, Austin, TX Woogeun Rhee, Tsinghua University, Beijing, China

26.1 A 1V 357Mb/s-Throughput TransferJetTM SoC with Embedded 1:30 PM Transceiver and Digital Baseband in 90nm CMOS M. Tamura1, F. Kondo1, K. Watanabe1, Y. Aoki1, Y. Shinohe1, K. Uchino1, Y. Hashimoto1, F. Nishiyama1, H. Miyachi1, I. Nagase2, I. Uezono2, R. Hisamura2, I. Maekawa1 1 Sony, Tokyo, Japan 2 Sony Semiconductor, Kagoshima, Japan 26.2 A 2Gb/s 150mW UWB Direct-Conversion Coherent Transceiver with IQ-Switching Carrier-Recovery Scheme T. Abe, Y. Yuan, H. Ishikuro, T. Kuroda Keio University, Yokohama, Japan 26.3 3-to-5GHz 4-Channel UWB Beamforming Transmitter 2:30 PM with 1 Phase Resolution Through Calibrated Vernier Delay Line in 0.13m CMOS L. Wang, Y. Guo, Y. Lian, C. Heng National University of Singapore, Singapore Break 26.4 An Interference-Aware 5.8GHz Wake-Up Radio for ETCS J. Choi1, K. Lee2, S-O. Yun2, S-G. Lee1, J. Ko2 1 KAIST, Daejeon, Korea 2 PHYCHIPS, Daejeon, Korea 3:00 PM 3:15 PM 2:00 PM

ADS

26.5 A 2.7nJ/b Multi-Standard 2.3/2.4GHz Polar Transmitter 3:45 PM for Wireless Sensor Networks Y-H. Liu1, X. Huang1, M. Vidojkovic1, K. Imamura2, P. Harpe1, G. Dolmans1, H. De Groot1 1 imec - Holst Centre, Eindhoven, The Netherlands 2 Panasonic, Osaka, Japan 26.6 A Meter-Range UWB Transceiver Chipset for 4:15 PM IDS Around-the-Head Audio Streaming X. Wang1, Y. Yu2, B. Busze1, H. Pflug1, A. Young1, X. Huang1, C. Zhou1, M. Konijnenburg1, K. Philips1, H. De Groot1 1 imec - Holst Centre, Eindhoven, The Netherlands 2 NXP Semiconductors, Eindhoven, The Netherlands 26.7 A 90nm CMOS 5Mb/s Crystal-Less RF Transceiver for RF-Powered WSN Nodes G. Papotto1, F. Carrara2, A. Finocchiaro2, G. Palmisano1 1 University of Catania, Catania, Italy 2 STMicroelectronics, Catania, Italy 26.8 A 915MHz 120W-RX/900W-TX Envelope-Detection Transceiver with 20dB In-Band Interference Tolerance X. Huang1, A. Ba1,2, P. Harpe1,3, G. Dolmans1, H. De Groot1, J. Long2 1 imec - Holst Centre, Eindhoven, The Netherlands 2 Delft University of Technology, Delft, The Netherlands 3 Eindhoven University of Technology, Eindhoven, The Netherlands 4:45 PM

IDS

5:00 PM

Conclusion

5:15 PM

47

SESSION 27

Wednesday February 22nd, 1:30 PM

DATA CONVERTER TECHNIQUES

Session Chair: Associate Chair:

Dieter Draxelmayr, Infineon Techologies, Villach, Austria Takahiro Miki, Renesas, Itami, Japan 1:30 PM

27.1 A 14b 3/6GHz Current-Steering RF DAC in 0.18m CMOS with 66dB ACLR at 2.9GHz G. Engel, S. Kuo, S. Rose Analog Devices, Wilmington, MA 27.2 Ring Amplifiers for Switched-Capacitor Circuits B. Hershberg1, S. Weaver1, K. Sobue2, S. Takeuchi2, K. Hamashita2, U-K. Moon1 1 Oregon State University, Corvallis, OR 2 Asahi Kasei EMD, Atsugi, Japan 27.3 A 5.37mW 10b 200MS/s Dual-Path Pipelined ADC Y. Chai, J-T. Wu National Chiao Tung University, Hsinchu, Taiwan Break 27.4 A 13b 315fsrms 2mW 500MS/s 1MHz Bandwidth Highly Digital Time-to-Digital Converter Using Switched Ring Oscillators A. Elshazly, S. Rao, B. Young, P. Hanumolu Oregon State University, Corvallis, OR 27.5 A 1.7mW 11b 250MS/s 2 Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS B. Verbruggen1, M. Iriguchi2, J. Craninckx1 1 imec, Leuven, Belgium 2 Renesas Electronics, Kawasaki, Japan 27.6 A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-Shaping SAR ADC J. Fredenburg, M. Flynn University of Michigan, Ann Arbor, MI 27.7 A 70dB DR 10b 0-to-80MS/s Current-Integrating SAR ADC with Adaptive Dynamic Range B. Malki1,2, T. Yamamoto3, B. Verbruggen1, P. Wambacq1,2, J. Craninckx1 1 imec, Leuven, Belgium 2 Vrije Universiteit Brussel, Brussels, Belgium 3 Renesas Electronics, Takasaki, Japan 27.8 A 7-to-10b 0-to-4MS/s Flexible SAR ADC with 6.5-to-16fJ/conversion-step P. Harpe1,2, Y. Zhang1, G. Dolmans1, K. Philips1, H. De Groot1 1 Holst Centre / imec, Eindhoven, The Netherlands 2 Eindhoven University of Technology, Eindhoven, The Netherlands 27.9 A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V Two-Step Pipelined ADC in 0.13m CMOS H-Y. Lee1, B. Lee2, U-K. Moon1 1 Oregon State University, Corvallis, OR 2 National Semiconductor, Santa Clara, CA Conclusion

2:00 PM

2:30 PM

3:00 PM 3:15 PM

3:45 PM

4:15 PM

4:45 PM

5:00 PM

5:15 PM

5:30 PM

48

SESSION 28
Session Chair: Associate Chair:

Wednesday February 22nd, 1:30 PM

ADAPTIVE & LOW-POWER CIRCUITS
Michael Phan, Qualcomm, Raleigh, NC Masaya Sumita, Panasonic, Moriguchi, Japan

28.1 A 4.5Tb/s 3.4Tb/s/W 6464 Switch Fabric with Self-Updating 1:30 PM Least-Recently-Granted Priority and Quality-of-Service Arbitration in 45nm CMOS S. Satpathy, K. Sewell, T. Manville, Y-P. Chen, R. Dreslinski, D. Sylvester, T. Mudge, D. Blaauw University of Michigan, Ann Arbor, MI 28.2 A 1.0TOPS/W 36-Core Neocortical Computing Processor with 2.3Tb/s Kautz NoC for Universal Visual Recognition C-Y. Tsai, Y-J. Lee, C-T. Chen, L-G. Chen National Taiwan University, Taipei, Taiwan 28.3 Conditional Push-Pull Pulsed Latches with 726fJps Energy-Delay Product in 65nm CMOS E. Consoli1, M. Alioto2,3, G. Palumbo1, J. Rabaey4 1 University of Catania, Catania, Italy 2 University of Siena, Siena, Italy 3 University of Michigan, Ann Arbor, MI 4 University of California at Berkeley, Berkeley, CA 28.4 A 200mV 32b Subthreshold Processor with Adaptive Supply Voltage Control S. Luetkemeier1, T. Jungeblut2, M. Porrmann1, U. Rueckert2 1 University of Paderborn, Paderborn, Germany 2 Bielefeld University, Bielefeld, Germany 2:00 PM

2:30 PM

ADS

2:45 PM

Break 28.5 13% Power Reduction in 16b Integer Unit in 40nm CMOS by Adaptive Power Supply Voltage Control with Parity-Based Error Prediction and Detection (PEPD) and Fully Integrated Digital LDO K. Hirairi1, O. Yasuyuki1, H. Fuketa2, T. Yasufuku2, M. Takamiya2, M. Nomura1, H. Shinohara1, T. Sakurai2 1 Semiconductor Technology Academic Research Center, Tokyo, Japan 2 University of Tokyo, Tokyo, Japan 28.6 Bubble Razor: An Architecture-Independent Approach to Timing-Error Detection and Correction M. Fojtik1, D. Fick1, Y. Kim1, N. Pinckney1, D. Harris2, D. Blaauw1, D. Sylvester1 1 University of Michigan, Ann Arbor, MI 2 Harvey Mudd College, Claremont, CA

3:00 PM 3:15 PM

3:45 PM

28.7 A 25MHz 7W/MHz Ultra-Low-Voltage Microcontroller SoC 4:15 PM in 65nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes D. Bol1, J. De Vos1, C. Hocquet1, F. Botman1, F. Durvaux1, S. Boyd2, D. Flandre1, J-D. Legat1 1 Universit catholique de Louvain, Louvain-la-Neuve, Belgium 2 P.E. International, Berkeley, CA 28.8 A 530mV 10-Lane SIMD Processor with Variation 4:45 PM Resiliency in 45nm SOI R. Pawlowski1, E. Krimer2, J. Crop1, J. Postman1, N. Moezzi-Madani3, M. Erez2, P. Chiang1 1 Oregon State University, Corvallis, OR 2 University of Texas, Austin, TX 3 Qualcomm, San Diego, CA Conclusion 5:15 PM

49

SHORT COURSE

Thursday February 23rd, 8:00 AM

Low-Power Analog Signal Processing

Organizer: Instructors: Willy Sansen, K.U. Leuven, Leuven, Belgium Christian Enz, CSEM, Neuchatel, Switzerland Willy Sansen, K.U. Leuven, Leuven, Belgium Boris Murmann, Stanford University, Stanford, CA Philip Mok, Hong Kong University of Science and Technology, Hong Kong

Overview
The reduction of the power consumption of all electronic functions is a continuous endeavor. This endeavor requires judicious comparison of analog and digital realizations from the point of view of performance per unit of power consumed. Analog signal processing offers the advantage that power consumption can be minimized at both very low and very high frequencies. This short course explores the limits in reduction of power consumption for important analog blocks. The first presentation defines the physical limits of supply voltages and power consumption based on present-day technologies and transistor models. The second presentation addresses the limits of amplifiers and filters. For all circuit blocks, figures of merit are derived, followed by circuit techniques to improve them. In the third presentation, new opportunitiesare identified to reduce the power consumption in all types of analog-to-digital converters, with emphasis on the improvement of the FOM with technology. Finally, in the fourth presentation, power minimization techniques are discussed for power management blocks such as dc-dc converters. The Short Course 8 am-9.30 am: Christian Enz: Ultra-low Power/Ultra-low Voltage Analog Circuit Design 9.30 am-10 am: Break 10 am-11.30 am: Willy Sansen: Power Limits for Amplifiers and Filters 11.30 am-12.30 am: Lunch 12.30 am-2 pm: Boris Murmann: Energy Limits in Current A/D Converter Architectures 2 pm-2.30 pm: Break 2.30 pm-4 pm: Philip Mok: Low-Power and Low-Voltage DC-DC Converter Design

OUTLINE: Ultra-Low-Power/Ultra-Low-Voltage Analog Circuit Design

The supply voltage of CMOS chips has been scaled down in recent years, today reaching the sub-1V region. Analog circuits unfortunately do not take advantage of this voltage scaling. In fact, almost all analog performance metrics are degraded at lower voltages. We first recall the fundamental limits of the design of low-power analog circuits. We then look at the main challenges when designing analog circuits for ultra-low-voltage (ULV) operation. We take a closer look at the MOS transistor operation with a particular focus on weak inversion. We then review several basic building blocks capable of operating at ULV. Instructor: Christian Enz is VP heading the Integrated and Wireless Systems Division of the Swiss Center for Electronics and Microtechnology (CSEM) in Neuchtel, Switzerland. He is also Professor at the Swiss Federal Institute of Technology, Lausanne (EPFL), where he is lecturing and supervising students in the field of analog and RF IC design. He received the PhD from the EPFL in 1989. His technical interests and expertise are in the field of ultralowpower analog and RF IC design, wireless sensor networks and semiconductor device modeling. Together with E. Vittoz and F. Krummenacher, he is the developer of the EKV MOS transistor model.

50

SHORT COURSE

Thursday February 23rd, 8:00 AM

Power Limits for Amplifiers and Filters

Increasing power consumption in amplifiers increases the speed and also reduces noise and distortion. The most common operational amplifiers, gm blocks and wideband amplifiers are compared using a power-based FOM. Also discussed are continuous-time filters, switchedcapacitor filters and GmC filters. They are classified and compared based on a unified FOM. Again power is optimized in view of speed, noise and distortion. Instructor: Willy Sansen received a PhD degree from U.C. Berkeley in 1972. Since 1980 he has been full professor at the Catholic University of Leuven, in Belgium, where he has headed the ESAT-MICAS laboratory on analog design up till 2008. He has been supervisor of sixtyfour PhD theses and has authored and coauthored more than 650 publications and fifteen books among which the Powerpoint slide based book Analog Design Essentials (Springer 2006). He was Program chair of the ISSCC-2002 conference and President of the IEEE SolidState Circuits Society in 2008-2009. He is the recipient of the D.O.Pederson award of the IEEE Solid-State Circuits in 2011. He is a Life Fellow of the IEEE.

Energy Limits in Current A/D Converter Architectures

Driven by ever-increasing application demands, the energy expended per A/D conversion has been reducedsubstantiallyover the last decade. This presentation surveys the most recent trends and investigatesenergylimits as they apply to A/D converterarchitectures commonly employedin fine-line CMOS technology (Flash, Pipeline, SAR and Oversampling Converters). Through this analysis,opportunitiesfor further improvements are identified and discussed in detail, specifically emphasizing the impact oftechnologyscaling. Instructor: Boris Murmann is an Associate Professor in the Department of Electrical Engineering, Stanford, CA. He received the Ph.D. degree in electrical engineering from the University of California at Berkeley in 2003. Dr. Murmanns research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. He is a member of the International Solid-State-Circuits Conference (ISSCC) program committee, an associate editor of the IEEE Journal of Solid-State Circuits and a Distinguished Lecturer of the IEEE Solid-State Circuits Society.

Low-Power and Low-Voltage DC-DC Converter Design

With the recent advanced development of the VLSI system, power management circuits will be operated with lower output power requirement and with lower supply voltage. Several strategies to improve the power efficiency of low-power DC-DC converter are described and their pros and cons are discussed. Different design techniques for low-voltage dc-dc converter design are also included. Instructor: Philip Mok is a Professor at the Department of Electronic and Computer Engineering, the Hong Kong University of Science and Technology in Hong Kong. He received his PhD in Electrical and Computer Engineering from the University of Toronto, Toronto, Canada, in 1995. His current research interests include power management integrated circuits and low-voltage analog integrated circuits design.

51

FORUM
F3: 10-40 Gb/s I/O Design for Data Communications
Organizer: Co-Organizer: Chair: Committee: Ken Chang, Xilinx, San Jose, CA Tony Chan Carusone, University of Toronto, Toronto, Canada Ali Sheikholeslami, University of Toronto, Toronto, Canada Bob Payne, Texas Instruments, Dallas, TX Miki Moyal, Intel, Haifa, Israel John Stonick, Synopsys, Hillsboro, OR Hisakatsu Yamaguchi, Fujitsu, Kawasaki Japan

The importance of I/O data rates beyond 10Gb/s is growing rapidly. Supporting these data rates introduces new challenges beyond those faced at lower data rates. The objective of this Forum is to present both electrical and optical I/O approaches to meeting these challenges at the architecture and circuit levels. The Forum commences with two talks offering an overview of circuits and systems issues in CMOS technology. They are followed by two presentations focusing on the challenges of 20Gb/s+ over electrical backplanes and very lossy electrical channels. The next talk compares conventional analog equalization versus digital (data-converter-based) approaches from a system perspective. The final two talks focus on optical solutions, highlighting the relative strengths and weaknesses of electrical and optical approaches. The Forum concludes with a panel discussion providing an opportunity for participants to give feedback and ask questions. The Forum is aimed at circuit designers and engineers working on high-speed wireline transceivers. Forum Agenda Time 8:00 8:20 08:30 Topic Breakfast Introduction:

Ali Sheikholeslami, University of Toronto, Toronto, Canada

10-to-40Gb/s I/O Circuits and System Design: Techniques to Improve Power Efficiency James Jaussi, Intel, Hillsboro, OR Design of 40Gb/s Broadband Transceivers in CMOS Technology Jri Lee, National Taiwan Univeristy, Taipei, Taiwan Break (What is so Hard About) SerDes Design Challenges for 20Gb/s+ Data Rates over Electrical Backplanes? Andy Joy, Texas Instruments, Northampton, United Kingdom 10-20Gb/s+ Equalizer Design for Electrical Channel with 40dB+ Loss Yasuo Hidaka, Fujitsu Laboratories of America, Sunnyvale, CA Lunch Equalization for High-Speed SerDes Systems a System-Level Comparison of Analog and Digital Techniques Vivek Telang, Broadcom, Austin, TX Optical vs. Electrical I/O: Reach, Bandwidth, Power Efficiency, Density and Cost Alexander Rylyakov, IBM T.J. Watson Research Center, Yorktown Heights, NY Break A System-Level Look at Silicon Photonics Ron Ho, Oracle, Redwood Shores, CA Panel Discussion Closing Remarks (Chair)

09:20 10:10 10:35

11:25 12:15 1:20

2:10

3:00 3:20 4:10 5:00

52

Thursday February 23rd, 8:00 AM

F4: Computational Imaging
Organizers: Makoto Ikeda, University of Tokyo, Tokyo, Japan Albert Theuwissen, Harvest Imaging, Bree, Belgium, Delft University of Technology, Delft, The Netherlands Johannes Solhusvik, Aptina Imaging, Oslo, Norway Jan Bosiers, Teledyne DALSA, Eindhoven, The Netherlands

Committee:

Computational imaging is becoming widely adopted in consumer products to reconstruct high-quality pictures from raw pixel data provided by special optics and image sensors. This forum provides details of such systems. We commence with an overview of computational photograpy and imaging. This is followed by object recognition and tracking techniques including interesting point techniques and face-detection algorithms optimized for cameras. Camera array techniques, multiple shot techniques and coded aperture techniques for improved resolution and extended depth-of-field are presented. The popular compressed sensing technique is also covered with the aim to reduce data rate without severely impacting image quality. Last, existing implementations on parallel-processing architectures are introduced. Forum Agenda Time 08:00 08:30 08:35 09:20 10:05 10:30 11:15 12:00 1:00 Topic Breakfast Introduction Makoto Ikeda, University of Tokyo, Tokyo, Japan Overview of Computational Photography and Imaging Shinsaku Hiura, Hiroshima City University, Hiroshima, Japan Interest Point and Local Descriptor Generation in Silicon Graham Kirsch, Aptina UK, Berkshire, United Kingdom Break Face Detection in Embedded Systems Petronel Bigioi, DigitalOptics, San Jose, CA Light Field Imaging with Regular Arrays of Inexpensive Cameras (RayCam) Kartik Venkataraman, Pelican Imaging, Mountain View, CA Lunch Super-Resolution by Multiple Shots: From Myths to Methods Lucas van Vliet, Delft University of Technology, Delft, The Netherlands Image and Depth from a Conventional Camera with a Coded Aperture Bill Freeman, Massachusetts Institute of Technology, Cambridge, MA Break Is Compressed Sensing Relevant to Image Sensors? Abbas El Gamal, Stanford University, Stanford, CA Processing Device Prospectives for Computational Imaging Applications Yuki Kobayashi, Renesas Electronics, Kanagawa, Japan Closing Remarks (Chair)

1:45

2:30 2:50 3:35 4:20

53

FORUM
F5: Bioelectronics for Sustainable Healthcare
Organizers: Chris Van Hoof, imec, Leuven, Belgium Wim Dehaene, Katholieke Universiteit Leuven, Leuven, Belgium Wentai Liu, UC Santa Cruz, Santa Cruz, CA

Committee: Wim Dehaene, Katholieke Universiteit Leuven, Leuven, Belgium Timothy Denison, Medtronic, Minneapolis, MN Minkyu Je, A*STAR, Singapore, Singapore Wentai Liu, UC Santa Cruz, Santa Cruz, CA Chris Van Hoof, imec, Leuven, Belgium Hoi-Jun Yoo, KAIST, Daejeon, Korea The forum gives a broad view on the role of Bioelectronics in the world of tomorrow. It starts from a holistic view on the importance of sustainable and affordable health care from a societal and economical perspective. Next the forum addresses key application challenges that need to be met to achieve those goals. The circuit and system requirements for these applications is derived. In the third part of the forum, the realization of the circuit building blocks (and their remaining challenges) is discussed. Circuit and component innovation is shown to be crucial for achieving advanced technological tools that will underpin sustainable health care. Forum Agenda Time 8:00 8:30 8:40 9:40 10:40 10:55 11:40 12:25 1:15 2:00 2:45 3:30 4:15 4:30 Topic Breakfast Introduction Chris Van Hoof, imec, Leuven, Belgium Societal and Economical Healthcare Challenges Bill Heetderks, NIH-BIBIB, Bethesda, MD Electronic System Challenges for Healthcare Gene Frantz, Texas Instruments, Dallas, TX Break Retinal Prosthesis and Hybrid Neural Interfaces James D Weiland, USC, Los Angeles, CA Chip-Level Electronic Noses for a Sustainable Society Sywert Brongersma, Holst Centre, Eindhoven, The Netherlands Lunch Low-Cost MR-compatible Neuroprosthetics Sung June Kim, Seoul National University, Seoul, Korea THz Bio-Imaging Systems Frank Chang, UCLA, Los Angeles, CA Low Noise Design and Integration Challenges for Neurophysiology Probes Zhi Yang, Singapore National University, Singapore, Singapore Low-Power Wireless and Implantable Sensor Interfaces Georges Gielen, University of Leuven, Leuven, Belgium Break Conclusion

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Thursday February 23rd, 8:00 AM

F6: Power/Performance Optimization of Many-Core Processor SoCs
Organizers: Stephen Kosonocky, Advanced Micro Devices, Fort Collins, CO Vladimir Stojanovic, MIT, Cambridge, MA Kees VanBerkel, ST Ericsson, Eindhoven, The Netherlands Ming-Yang Chao, Mediatek, Hsinchu, Taiwan Tobias Knoll, RWTH Aachen University, Aachen, Germany Joshua Friedrich, IBM, Austin, TX

Committee:

As performance scaling per-core continues to slow-down, designers are faced with a myriad of challenges in efficiently using the transistors offered by modern processes. This Forum will address next generation computing challenges in the context of highly parallel manycore processors. The key design challenge in the many-core era is management and efficient use of resources across the layers of design hierarchy. In this context, the Forum will focus on key challenges that lie ahead: Architecture balancing: homogeneous vs. heterogeneous processors Embedded multicore challenges in mobile platforms Power management and optimization On-chip network and memory system design for ease of programming and balancing of compute/communication power Design tool challenges for many-core SOCs Forum Agenda Time 08:00 08:30 08:45 09:30 10:15 10:30 11:15 12:00 11:00 11:45 Topic Breakfast Introduction Stephen Kosonocky, AMD, Fort Collin, CO Integration Choices for Heterogeneous SoCs Jim Kahle, IBM, Austin, TX Embedded Multicore in Mobile Platforms Alain Artieri, ST-Ericsson, Grenoble, France Break Heterogeneous Many-Core Processors and the Fusion System Architecture Michael Schulte, AMD, Austin, TX Power Optimization Through Many-Core Multiprocessing John Goodacre, ARM, Cambridge, United Kingdom Lunch High-Performance Energy-Efficient NoC Fabrics Mark A. Anders, Intel, Hillsboro, OR System-Level Power Management Methodology for Real-Time Applications: From Application to Silicon Se-Joong Lee, Texas Instruments, Dallas, TX Randomized Modeling of Performance and Power in Heterogeneous Multi-Core SOC Michael Frank, MediaTek, San Jose, CA The Layout Evaluation and Hierarchical Layout Method of MPSoC Yuichi Nakamura, NEC, Kawasaki, Japan Break Panel Discussion Moderator: Vladimir Stojanovic, MIT, Cambridge, MA Conclusion

2:30

3:15 4:00 4:15 5:00

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COMMITTEES
EXECUTIVE COMMITTEE
CONFERENCE CHAIR Anantha Chandrakasan, Massachusetts Institute of Technology, Cambridge, MA SECRETARY, FORUM CHAIR AND DATA TEAM CO-CHAIR Trudy Stetzler, Texas Instruments, Stafford, TX DIRECTOR OF FINANCE AND BOOK DISPLAY COORDINATOR Bryant Griffin, Penfield, NY PROGRAM CHAIR Hideto Hidaka, Renesas Electronics, Itami, Japan PROGRAM VICE CHAIR Bram Nauta, University of Twente, Enschede, The Netherlands STUDENT FORUM CHAIR AND UNIVERSITY RECEPTIONS Jan van der Spiegel, University of Pennsylvania, Philadelphia, PA WEB MANAGER AND DATA TEAM CO-CHAIR Bill Bowhill, Intel, Hudson, MA ITPC FAR EAST REGIONAL CHAIR Hoi-Jun Yoo, KAIST, Daejeon, Korea ITPC FAR EAST REGIONAL VICE CHAIR AND STUDENT FORUM VICE-CHAIR Makoto Ikeda, University of Tokyo, Tokyo, Japan ITPC FAR EAST REGIONAL SECRETARY Kazutami Arimoto, Renesas Electronics, Itami, Japan ITPC EUROPEAN REGIONAL CHAIR Aarno Prssinen, Renaesas Mobile, Helsinki, Finland ITPC EUROPEAN REGIONAL VICE CHAIR Eugenio Cantatore, Eindhoven University of Technology, Eindhoven, The Netherlands ITPC EUROPEAN REGIONAL SECRETARY Alison Burdett, Toumaz Technology, Abingdon, United Kingdom EDUCATIONAL EVENTS LIAISON Ali Sheikholeslami, University of Toronto, Toronto, Canada ADCOM REPRESENTATIVE Bryan Ackland, Stevens Institute of Technology, Old Bridge, NJ DIRECTOR OF PUBLICATIONS AND PRESENTATIONS Laura Fujino, University of Toronto, Toronto, Canada DIRECTOR OF AUDIOVISUAL SERVICES John Trnka, Rochester, MN PRESS LIAISON AND AWARDS & RECOGNITION COMMITTEE (ARC) CHAIR Kenneth C. Smith, University of Toronto, Toronto, Canada PRESS COORDINATOR Alice Wang, Texas Instruments, Dallas, TX DIRECTOR OF OPERATIONS Melissa Widerkehr, Widerkehr and Associates, Montgomery Village, MD

TECHNICAL EDITORS Jason H. Anderson, University of Toronto, Toronto, Canada Vincent Gaudet, University of Waterloo, Waterloo, Canada Glenn Gulak (Editor-at-Large), University of Toronto, Toronto, Canada James W. Haslett, University of Calgary, Calgary, Canada Shahriar Mirabbasi, University of British Columbia, Vancouver, Canada Kostas Pagiamtzis, Gennum, Burlington, Canada Kenneth C. Smith (Editor-at-Large), University of Toronto, Toronto, Canada MULTI-MEDIA COORDINATOR Dave Halupka, Kapik Integration, Toronto, Canada

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COMMITTEES
INTERNATIONAL TECHNICAL PROGRAM COMMITTEE
PROGRAM CHAIR: Hideto Hidaka, Renesas Electronics, Itami, Japan PROGRAM VICE CHAIR: Bram Nauta, University of Twente, Enschede, The Netherlands

ANALOG SUBCOMMITTEE
Chair: Bill Redman-White, NXP Semiconductors, Southampton, United Kingdom Ivan Bietti, ST Microelectronics, Grenoble, France Tony Chan Carusone, University of Toronto, Toronto, Canada Gyu-Hyeong Cho, KAIST, Daejon, Korea Baher Haroun, Texas Instruments, Dallas, TX Jed Hurwitz, Broadcom, Edinburgh, United Kingdom Minkyu Je, Institute of Microelectronics, A*STAR, Singapore Wing Hung Ki, HKUST, Clear Water Bay, Hong Kong, Peter Kinget, Columbia University, New York, NY *Kimmo Koli, ST-Ericsson Oy, Turku, Finland Jae-Youl Lee, Samsung Electronics, Yongin, Korea Tsung-Hsien Lin, National Taiwan University, Taipei, Taiwan Chris Mangelsdorf, Analog Devices, Tokyo, Japan Jafar Savoj, Xilinx, San Jose, CA Michiel Steyaert, KULeuven, Hevrelee, Belgium Axel Thomsen, Silicon Laboratories, Austin, TX Ed van Tuijl, University of Twente, Enschede, The Netherlands

DATA CONVERTERS SUBCOMMITTEE

Chair: Venu Gopinathan, Texas Instruments, Bangalore, India Brian Brandt, Maxim Integrated Products, North Chelmsford, MA *Lucien Breems, NXP Semiconductors, Eindhoven, The Netherlands Klaas Bult, Broadcom, Bunnik, The Netherlands Marco Corsi, Texas Instruments, Dallas, TX Dieter Draxelmayr, Infineon Techologies, Villach, Austria Michael Flynn, University of Michigan, Ann Arbor, MI Gabriele Manganaro, Analog Devices, Wilmington, MA Yiannos Manoli, University of Freiburg, IMTEK, Freiburg, Germany Takahiro Miki, Renesas Electronics, Itami, Japan Gerhard Mitterregger, Intel Mobile Communications Austria, St. Magdalen, Austria Un-Ku Moon, Oregon State University, Corvallis, OR Boris Murmann, Stanford University, Stanford, CA Katsu Nakamura, Analog Devices, Wilmington, MA Shanthi Pavan, Indian Institute Of Technology, Chennai, India Michael Perrott, Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates

ENERGY-EFFICIENT DIGITAL SUBCOMMITTEE

Chair: Tzi-Dar Chiueh, National Chip Implementation Center, Hsinchu, Taiwan Kazutami Arimoto, Renesas Electronics, Hyogo, Japan *Ming-Yang Chao, Mediatek, Hsinchu, Taiwan Wim Dehaene, KU Leuven, Leuven, Belgium Vasantha Erraguntla, Intel Technology India, Bangalore, India Stephen Kosonocky, Advanced Micro Devices, Fort Collins, CO Shannon Morton, Nvidia, Bristol, United Kingdom Byeong-Gyu Nam, Chungnam National University, Daejeon, Korea Michael Phan, Qualcomm, Raleigh, NC Michael Polley, Texas Instruments, Dallas, TX Masaya Sumita, Panasonic, Moriguchi, Japan Kees van Berkel, ST-Ericsson, Eindhoven, The Netherlands

HIGH-PERFORMANCE DIGITAL SUBCOMMITTEE

Chair: Stefan Rusu, Intel, Santa Clara, CA *Lew Chua-Eoan, Qualcomm, San Diego, CA Tim Fischer, AMD, Fort Collins, CO Joshua Friedrich, IBM, Austin, TX Hiroo Hayashi, Toshiba, Kawasaki, Japan Anthony Hill, Texas Instruments, Dallas, TX Atsuki Inoue, Fujitsu, Kawasaki, Japan Tanay Karnik, Intel, Hillsboro, OR Tobias Noll, RWTH Aachen University, Aachen, Germany Luke Shin, Oracle, San Jose, CA Vladimir Stojanovic, MIT, Cambridge, MA Se-Hyun Yang, Samsung, Yongin, Korea

*ADS/IDS Committee

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COMMITTEES
IMAGERS, MEMS, MEDICAL AND DISPLAYS SUBCOMMITTEE
Chair: Roland Thewes, TU Berlin, Berlin, Germany JungChak Ahn, Samsung Electronics, Yongin, Korea Jan Bosiers, Teledyne DALSA Professional Imaging, Eindhoven, The Netherlands Timothy Denison, Medtronic, Minneapolis, MN Maysam Ghovanloo, Georgia Institure of Technology, Atlanta, GA *Christoph Hagleitner, IBM Research, Ruschlikon, Switzerland Makoto Ikeda, University of Tokyo, Tokyo, Japan Robert Johansson, Aptina Imaging, Oslo, Norway Sam Kavusi, Bosch Research and Technology Center, Palo Alto, CA Shoji Kawahito, Shizuoka University, Hamamatsu, Japan Wentai Liu, UC Santa Cruz, Santa Cruz, CA Kofi Makinwa, Technical University of Delft, Delft, The Netherlands Young-Sun Na, LG Electronics, Seoul, Korea Jun Ohta, Nara Institute of Science & Technology, Nara, Japan Yusuke Oike, Sony, Kanagawa, Japan Maurits Ortmanns, University of Ulm, Ulm, Germany Aaron Partridge, SiTime, Sunnyvale, CA David Stoppa, Fondazione Bruno Kessler, Trento, Italy

MEMORY SUBCOMMITTEE
Chair: Kevin Zhang, Intel, Hillsboro, OR Colin Bill, Global Foundries, Sunnyvale, CA Leland Chang, IBM T. J. Watson Research Center, Yorktown Heights, NY Joo Sun Choi, Samsung, Hwasung, Korea Sungdae Choi, Hynix Semiconductor, Icheon, Korea Michael Clinton, Texas Instruments, Dallas, TX Jin-Man Han , Samsung Electronics, Hwasung, Korea *Satoru Hanzawa, Hitachi Central Research Laboratory, Tokyo, Japan Heinz Hoenigschmid, Elpida Memory, Munich, Germany Nicky C.C. Lu, Etron Technology, Hsinchu, Taiwan Cormac OConnell, TSMC, Ottawa, Canada Yasuhiro Takai, Elpida Memory, Sagamihara, Japan Daisaburo Takashima, Toshiba, Yokohama, Japan Ken Takeuchi, University of Tokyo, Tokyo, Japan Daniele Vimercati, Micron Technology, Agrate, Italy Tadaaki Yamauchi, Renesas Electronics, Itami, Japan

RF SUBCOMMITTEE
Chair: Andreia Cathelin, STMicroelectronics, Crolles Cedex, France Ehsan Afshari, Cornell University, Ithaca, NY Pietro Andreani, Lund University, Lund, Sweden Hooman Darabi, Broadcom, Irvine, CA Brian Floyd, North Carolina State University, Raleigh, NC *Joseph Golat, Motorola, Algonquin, IL Songcheol Hong, KAIST, Daejeon, Korea Mike Keaveney, Analog Devices, Limerick, Ireland Harald Pretl, Intel Mobile Communications, Linz, Austria Gabriel Rebeiz, University of California, San Diego, La Jolla, CA Carlo Samori, Politecnico di Milano, Milano, Italy Bogdan Staszewski, TU Delft, Delft, The Netherlands Piet Wambacq, imec, Leuven, Belgium Taizo Yamawaki, Renesas Mobile, Takasaki, Japan Masoud Zargari, Qualcomm-Atheros, Irvine, CA Jing-Hong Conan Zhan, MediaTek, HsinChu, Taiwan Michael Zybura, RF Micro Devices, Scotts Valley, CA

TECHNICAL DIRECTIONS SUBCOMMITTEE

Chair: Siva Narendra, Tyfone, Portland, OR Pascal Ancey, STMicroelectronics, Crolles, France Ahmad Bahai, National Semiconductor, Santa Clara, CA *Azeez Bhavnagarwala, GLOBALFOUNDRIES, Hopewell Junction, NY Shekhar Borkar, Intel, Hillsboro, OR Alison Burdett, Toumaz Technology, Abingdon, United Kingdom Eugenio Cantatore, Eindhoven University of Technology, Eindhoven, The Netherlands Eric Colinet, CEA-LETI, Grenoble, France Fu-Lung Hsueh, TSMC, Hsinchu, Taiwan Uming Ko, Texas Instruments, Houston, TX Tadahiro Kuroda, Keio University, Yokohama, Kanagawa, Japan Masaitsu Nakajima, Panasonic, Moriguchi, Japan David Ruffieux, CSEM, Neuchatel, Switzerland Satoshi Shigematsu, NTT Electronics, Yokohama, Japan Chris Van Hoof, IMEC, Leuven, Belgium Hoi-Jun Yoo, KAIST, Daejeon, Korea *ADS/IDS Committee

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COMMITTEES
WIRELESS SUBCOMMITTEE
Chair: David Su, Atheros Communications, San Jose, CA Didier Belot, ST Microelectronics, Crolles, France Gangadhar Burra, Texas Instruments, Dallas, TX George Chien, MediaTek, San Jose, CA Jan Crols, AnSem, Heverlee, Belgium Ranjit Gharpurey, University of Texas at Austin, Austin, TX Hossein Hashemi, University of Southern California, Los Angeles, CA Myung-Woon Hwang, FCI, Sungnam, Korea Albert Jerng, Ralink, Jhubei, Taiwan Eric Klumperink, University of Twente, Enschede, The Netherlands Shouhei Kousai, Toshiba, Kawasaki, Japan Domine Leenaerts, NXP Semiconductors, Eindhoven, The Netherlands Sven Mattisson, Ericsson AB, Lund, Sweden *Kenichi Okada, Tokyo Institute of Technology, Tokyo, Japan Yorgos Palaskas , Intel, Hillsboro, OR Aarno Parssinen, Renaesas Mobile, Helsinki, Finland Woogeun Rhee, Tsinghua University, Beijing, China Iason Vassiliou, Broadcom, Alimos, Greece

WIRELINE SUBCOMMITTEE
Chair: Daniel Friedman, IBM Thomas J. Watson Research Center, Yorktown Heights, NY Ajith Amerasekera, Texas Instruments, Dallas, TX Ken Chang, Xilinx, San Jose, CA SeongHwan Cho, KAIST, Daejon, Korea Nicola Da Dalt, Infineon, Austria Ichiro Fujimori, Broadcom, Irvine, CA Chewnpu Jou, TSMC, Hsinchu, Taiwan Jack Kenney, Analog Devices, Somerset, NJ Miki Moyal, Intel Israel, Haifa, Israel Masafumi Nogawa, NTT Microsystem Integration Laboratories, Atsugi, Japan Bob Payne, Texas Instruments, Dallas, TX Tatsuya Saito, Hitachi, Kokubunji, Tokyo, Japan Ali Sheikholeslami, University of Toronto, Toronto, Canada Jae-Yoon Sim, POSTECH, Pohang, Korea John T. Stonick, Synopsys, Hillsboro, OR *Koichi Yamaguchi, Renesas Electronics, Kawasaki, Japan Hisakatsu Yamaguchi, Fujitsu Laboratories, Kawasaki, Japan

EUROPEAN REGIONAL COMMITTEE

ITPC EUROPEAN REGIONAL CHAIR Aarno Prssinen, Renaesas Mobile, Helsinki, Finland ITPC EUROPEAN REGIONAL VICE CHAIR Eugenio Cantatore, Eindhoven University of Technology, Eindhoven, The Netherlands ITPC EUROPEAN REGIONAL SECRETARY Alison Burdett, Toumaz Technology, Abingdon, United Kingdom Members: Pascal Ancey, STMicroelectronics, Crolles, France
Pietro Andreani, Lund University, Lund, Sweden Didier Belot, STMicroelectronics, Crolles, France Ivan Bietti, STMicroelectronics, Grenoble, France Jan Bosiers, Teledyne DALSA Professional Imaging, Eindhoven, The Netherlands Lucien Breems, NXP Semiconductors, Eindhoven, The Netherlands Klaas Bult, Broadcom, Bunnik, The Netherlands Alison Burdett, Toumaz Technology, Abingdon, United Kingdom Andreia Cathelin, STMicroelectronics, Crolles Cedex, France Eric Colinet, CEA-LETI, Grenoble, France Jan Crols, AnSem, Heverlee, Belgium Nicola Da Dalt, Infineon, Austria Wim Dehaene, KULeuven, Leuven, Belgium Dieter Draxelmayr, Infineon Techologies, Villach, Austria Christoph Hagleitner, IBM Research, Ruschlikon, Switzerland Heinz Hoenigschmid, Elpida Memory, Munich, Germany Jed Hurwitz, Broadcom, Edinburgh, Scotland Robert Johansson, Aptina Imaging, Oslo, Norway Mike Keaveney, Analog Devices, Limerick, Ireland Eric Klumperink, University of Twente, Enschede, The Netherlands Kimmo Koli, ST-Ericsson Oy, Turku, Finland Domine Leenaerts, NXP Semiconductors, Eindhoven, The Netherlands Kofi Makinwa, Technical University of Delft, Delft, The Netherlands Gerhard Mitterregger, Intel Mobile Communications Austria, St. Magdalen, Austria Shannon Morton, Nvidia, Bristol, United Kingdom *ADS/IDS Committee

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COMMITTEES
European Members (continued):
Miki Moyal, Intel Iserael, Haifa, Israel Tobias Noll, RWTH Aachen University, Aachen, Germany Maurits Ortmanns, University of Ulm, Ulm, Germany Harald Pretl, Intel Mobile Communications, Linz, Austria Bill Redman-White, NXP Semiconductors, Southampton, United Kingdom David Ruffieux, CSEM, Neuchatel, Switzerland Carlo Samori, Politecnico di Milano, Milano, Italy Bogdan Staszewski, Technical University of Delft, Delft, The Netherlands David Stoppa, Fondazione Bruno Kessler, Trento, Italy Roland Thewes, TU Berlin, Berlin, Germany Kees van Berkel, ST-Ericsson, Eindhoven, The Netherlands Chris Van Hoof, imec, Leuven, Belgium Ed van Tuijl, University of Twente, Enschede, The Netherlands Iason Vassiliou, Broadcom, Alimos, Greece Daniele Vimercati, Micron Technology, Agrate, Italy Piet Wambacq, imec, Leuven, Belgium

FAR EAST REGIONAL COMMITTEE

ITPC FAR EAST REGIONAL CHAIR Hoi-Jun Yoo, KAIST, Daejeon, Korea ITPC FAR EAST REGIONAL VICE CHAIR AND STUDENT FORUM VICE-CHAIR Makoto Ikeda, University of Tokyo, Tokyo, Japan ITPC FAR EAST REGIONAL SECRETARY Kazutami Arimoto, Renesas Electronics, Itami, Japan
Members: JungChak Ahn, Samsung Electronics, Yongin, Korea Ming-Yang Chao, MediaTek, Hsinchu, Taiwan Tzi-Dar Chiueh, National Chip Implementation Center, Hsinchu, Taiwan Gyu-Hyoeong Cho, KAIST, Daejeon, Korea SeongHwan Cho, KAIST, Daejon, Korea Joo Sun Choi, Samsung, Hwasung, Korea Sungdae Choi, Hynix Semiconductor, Icheon, Korea Vasantha Erraguntla, Intel Technology, Bangalore, India Satoru Hanzawa, Hitachi Central Research Laboratory, Tokyo, Japan Hiroo Hayashi, Toshiba, Kawasaki, Japan Songcheol Hong, KAIST, Daejeon, Korea Fu-Lung Hsueh, TSMC, Hsinchu, Taiwan Myung-Woon Hwang, FCI, Sungnam, Kyunggi, Korea Atsuki Inoue, Fujitsu, Kawasaki, Japan Minkyu Je, Institute of Microelectronics, A*STAR, Singapore, Singapore Albert Jerng, Ralink, Jhubei, Taiwan Chewnpu Jou, TSMC, Hsinchu, Taiwan Shoji Kawahito, Shizuoka University, Hamamatsu, Japan Wing Hung Ki, HKUST, Hong Kong, China Shouhei Kousai, Toshiba, Kawasaki, Japan Tadahiro Kuroda, Keio University, Yokohama, Kanagawa, Japan Jae-Youl Lee, Samsung Electronics, Yongin, Korea Tsung-Hsien Lin , National Taiwan University, Taipei, Taiwan Nicky C.C. Lu, Etron Technology, Hsinchu, Taiwan Chris Mangelsdorf, Analog Devices K.K, Tokyo, Japan Takahiro Miki, Renesas Electronics, Itami, Japan Young-Sun Na, LG Electronics, Seoul, Korea Masaitsu Nakajima, Panasonic, Osaka, Japan Byeong-Gyu Nam, Samsung Electronics, Yongin, Korea Masafumi Nogawa, NTT Microsystem Integration Laboratories, Atsugi, Japan Jun Ohta, Nara Institute of Science & Technology, Nara, Japan Yusuke Oike, Sony, Kanagawa, Japan Kenichi Okada, Tokyo Institute of Technology, Tokyo, Japan Shanthi Pavan, Indian Institute Of Technology, Chennai, India Woogeun Rhee, Tsinghua University, Beijing, China Tatsuya Saito, Hitachi, Tokyo, Japan Satoshi Shigematsu, NTT Electronics, Yokohama, Japan Jae-Yoon Sim, POSTECH, Pohang, Korea Masaya Sumita, Panasonic, Moriguchi, Japan Yasuhiro Takai, Elpida Memory, Sagamihara, Japan Daisaburo Takashima, Toshiba, Yokohama, Japan Ken Takeuchi, University of Tokyo, Tokyo, Japan Koichi Yamaguchi, NEC, Sagamihara, Japan Tadaaki Yamauchi, Renesas Electronics, Itami, Japan Taizo Yamawaki, Renesas Electronics, Gunma, Japan Se Hyun Yang, Samsung, Yongin, Korea Jing-Hong Conan Zhan, MediaTek, HsinChu, Taiwan

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CONFERENCE INFORMATION
HOW TO REGISTER FOR ISSCC
Online: This is the fastest, most convenient way to register and will give you immediate email confirmation of your events. To register online (which requires a credit card), go to the ISSCC website at www.isscc.org and select the link to the registration website. FAX or mail: Use the 2012 IEEE ISSCC Registration Form which can be downloaded from the registration website. All payments must be made in U.S. Dollars, by credit card or check. Checks must be made payable to ISSCC 2012. It will take several days before you receive email confirmation when you register using the form. Registration forms received without full payment will not be processed until payment is received at YesEvents. Please read the descriptions and instructions on the back of the form carefully. Onsite: The Onsite Registration and Advance Registration Pickup Desks at ISSCC 2012 will be located in the Yerba Buena Ballroom Foyer at the San Francisco Marriott Marquis. All participants, except as noted below, should register or pick up their registration materials at these desks as soon as possible. Pre-registered Presenting Authors and pre-registered members of the ISSCC Program and Executive Committees must go to the Nob Hill Room, Ballroom level, to collect their conference materials. REGISTRATION DESK HOURS: Saturday, Sunday, Monday, Tuesday, Wednesday, Thursday, February 18 February 19 February 20 February 21 February 22 February 23 4:00 pm to 7:00 pm 6:30 am to 8:30 pm 6:30 am to 3:00 pm 8:00 am to 3:00 pm 8:00 am to 3:00 pm 7:00 am to 2:00 pm

Students must present their Student ID at the Registration Desk to receive the student rates. Those registering at the IEEE Member rate must provide their IEEE Membership number. Deadlines: The deadline for registering at the Early Registration rates is 11:59 pm Pacific Time Friday January 13, 2012. After January 13th, and on or before 11:59 pm Pacific Time Monday January 30, 2012, registrations will be processed at the Late Registration rates. After January 30th, you must register onsite at the Onsite rates. You are urged to register early to obtain the lowest rates and ensure your participation in all aspects of ISSCC 2012. Cancellations/Adjustments/Substitutions: Prior to 11:59 pm Pacific Time Monday January 30, 2012, conference registration can be cancelled. Fees paid will be refunded (less a processing fee of $75). Registration category or credit card used can also be changed (for a processing fee of $35). Send an email to the registration contractor at [email protected] to cancel or make other adjustments. No refunds will be made after 11:59 pm Pacific Time January 30, 2012. Paid registrants who do not attend the conference will be sent all relevant conference materials. Transfer of registration to someone else is allowed with WRITTEN permission from the original registrant.

MEMBERSHIP SAVES YOU ON ISSCC REGISTRATION

Take advantage of reduced ISSCC registration fees by using your IEEE membership number. If youre an IEEE member and have forgotten your member number, simply phone IEEE at 1(800) 678-4333 and ask. IEEE membership staff will take about two minutes to look up your number for you. If you come to register onsite without your membership card, you can phone IEEE then, too. Or you can request a membership number look-up by email. Use the online form at: www.ieee.org/about/help/member_support.html. If youre not an IEEE member, consider joining before you register to save on your fees. Join online at www.ieee.org/join at any time and youll receive your member number by email. If you join at the conference, you can also select a free Society membership. This offer is not available to existing IEEE members. All IEEE members are invited to drop into the Member Lounge in the Willow Room behind the IEEE Exhibit this year. Meet and greet other IEEE members and IEEE staff, learn more about products/services, IEEE grade elevations, or just relax. Upgrade your IEEE membership to Solid-State Circuits Society membership for $28. SSCS membership provides tutorials and short courses free online at sscs.ieee.org/tutorials-online. Students are eligible for conference travel grants with SSCS membership and an application. Add Society membership at sscs.ieee.org/membership or renew or join during ISSCC at the onsite IEEE Exhibit.

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CONFERENCE INFORMATION
ITEMS INCLUDED IN REGISTRATION
Technical Sessions: Registration includes admission to all technical and evening sessions starting Sunday evening and continuing throughout Monday, Tuesday and Wednesday. ISSCC does not offer partial conference registrations. Technical Book Display: A number of technical publishers will have collections of professional books and textbooks for sale during the Conference. The Book Display will be open on Monday from Noon to 8:00 pm; on Tuesday from 10:00 am to 8:00 pm; and on Wednesday from 10:00 am to 3:00 pm. Demo Sessions: Hardware demonstrations will support selected papers from industry and academia during the Social Hours. Author Interviews: Author Interviews will be held Monday, Tuesday and Wednesday evenings. Authors from each days papers will be available to discuss their work. Social Hour: Social Hour refreshments will be available starting at 5:15 pm on Monday and Tuesday in both the Book Display and Author Interview areas. University Events: Several universities are planning social events during the Conference. Check the University Events display at the conference for the list of universities, locations and times of these events. ISSCC logo umbrella: A folding umbrella will be provided to all conference registrants. Publications: Conference registration includes: -The Digest of Technical Papers in both hard copy and on CD (available onsite beginning on Sunday at 4:00 pm, and during registration hours on Monday through Wednesday). -The ISSCC 2012 Conference DVD that includes the Digest and Visuals Supplement (to be mailed in April). Student registration does not include the ISSCC 2011 Conference DVD, however it is available for purchase at a reduced fee for students.

OPTIONAL EVENTS
Educational Events: Many educational events are available at ISSCC 2012 for an additional fee. There are nine 90-minute Tutorials and two all-day Forums on Sunday. There are four additional all-day Forums on Thursday as well as an all-day Short Course. All events include a course handout in color. The all-day events also include breakfast, lunch and break refreshments. See the schedule for details of the topics and times. Womens Networking Event: ISSCC will be sponsoring a networking event for women in solid-state circuits on Monday at 12:15 pm. This luncheon is an opportunity to get to know other women in the profession anddiscuss a range of topics including leadership, work-life balance, and professional development. By registering and paying a nominal fee for this event, you will receive a ticket, a chance to build new friendships, and an opportunity to expand your professional network. Please indicate on your ISSCC registration form if you plan to attend this special event, open to women only.

OPTIONAL PUBLICATIONS
ISSCC 2012 Publications: The following ISSCC 2012 publications can be purchased in advance or onsite: Additional copies of the Digest of Technical Papers in book or CD format. Additional copies of the ISSCC 2012 Conference DVD (mailed in April). ISSCC 2012 Conference DVD at the special student price (mailed in April). 2012 Tutorials DVD: All of the 90 minute Tutorials (mailed in May). 2012 Short Course DVD: Low Power Analog Signal Processing (mailed in May). Short Course and Tutorial DVDs contain audio and written English transcripts synchronized with the presentation visuals. In addition, the Short Course DVDs contain a pdf file of the presentations suitable for printing, and pdf files of key reference material. Earlier ISSCC Publications: Selected publications from earlier conferences can be purchased. There are several ways to purchase this material: -Items listed on the registration form can be purchased with registration and picked up at the conference or mailed to you when available. -Visit the ISSCC Publications Desk. This desk is located in the registration area and has the same hours as conference registration. With payment by cash, check or credit card, you can pick up (or order for future delivery) materials at this desk. Tutorial and Short Course DVDs from prior conferences are available. See the order form for titles and prices. -Visit the ISSCC website at www.isscc.org and click on the link SHOP ISSCC where you can order online or download an order form to mail or fax. For a small shipping fee, this material will be sent to you immediately (or when available) and you will not have to wait until you attend the conference to get it.

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CONFERENCE INFORMATION
HOW TO MAKE HOTEL RESERVATIONS
TO ALL ATTENDEES WHO NEED A HOTEL ROOM: We are offering this year a $100 Marriott rebate coupon! If you register for ISSCC 2012 and spend at least three nights at the San Francisco Marriott Marquis, a credit of $100 will be applied to your hotel bill. Enjoy the convenience of staying at the Conference hotel AND save money too! See the hotel reservations site for details. Online: ISSCC participants are urged to make their hotel reservations at the San Francisco Marriott Marquis online. Go to the conference website and click on the Hotel Reservation link. Conference room rates are $215 for a single/double, $235 for a triple and $255 for a quad (per night plus tax). In addition, ISSCC attendees booked in the ISSCC group receive in-room Internet access for free. All online reservations require the use of a credit card. Online reservations are confirmed immediately. You should print the page containing your confirmation number and reservation details and bring it with you when you travel to ISSCC. Telephone: Call 800-266-9432 (US) or 506-474-2009 and ask for Reservations. When making your reservation, identify the group as ISSCC 2012 to get the group rate. Hotel Deadline: Reservations must be received at the San Francisco Marriott Marquis no later than January 30, 2012 to obtain the special ISSCC rates. A limited number of rooms are available at these rates. Once this limit is reached or after January 30th, the group rates will no longer be available and reservations will be filled at the best available rate. Changes: Before the hotel deadline, your reservation can be changed by calling the telephone numbers above. After the deadline, call the Marriott Marquis at 888-575-8934 (ask for Reservations). Have your hotel confirmation number ready.

REFERENCE INFORMATION
TAKING PICTURES, VIDEOS OR AUDIO RECORDINGS DURING ANY OF THE SESSIONS IS NOT PERMITTED Conference Website: ISSCC Email: Registration questions: Hotel Information: www.isscc.org [email protected] [email protected] San Francisco Marriott Marquis 55 Fourth Street San Francisco, CA 94103 Phone: 415-896-1600 Kenneth C. Smith University of Toronto Email: [email protected] Phone: 416-418-3034 Fax: 416-971-2286 YesEvents P.O. Box 32862 Baltimore, MD 21282 Email: [email protected] Phone: 410-559-2200 or 800-937-8728 Fax: 410-559-2217

Press Information:

Registration:

Hotel Transportation: Visit the ISSCC website Attendees page for helpful travel links and to download a document with directions and pictures of how to get from the San Francisco Airport (SFO) to the Marriott Marquis. You can get a map and driving directions from the hotel website at www.marriott.com/hotels/travel/sfodt-san-francisco-marriott-marquis/ Next ISSCC Dates and Location: ISSCC 2013 will be held on February 17-21, 2013 at the San Francisco Marriott Marquis Hotel.

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ISSCC 2012 ADVANCE PROGRAM