National Institute of Technology Durgapur

Computer Science & Engineering

Digital Logic Design Lab Manual (CSS351)

INDEX
Content Page Number

Syllabus For Digital Logic Lab 2

Experiment – 1 3
Experiment – 2 7
Experiment – 3 9
Experiment – 4 11
Experiment – 5 12
Experiment – 6 14
Experiment – 7 16
Experiment – 8 17
Experiment – 9 20
Experiment – 10 25
Experiment – 11 28
Experiment – 12 30
 SYLLABUS FOR DIGITAL LOGIC DESIGN LAB

Objective: To understand the digital logic and create various logic circuit using logic gates.

1. Introduction to digital logic laboratory, specifications of IC, study of the data sheet, concept
of Vcc, ground and verification of the truth tables.
2. Implementation of a given Boolean function using logic gates in both SOP and POS forms.
3. Verify DE Morgan’s law. Verify the Universal logic gate (NAND, NOR).
4. Implement NAND based logic circuit for any Boolean expression. Verify that F= AB + A’C’
is functionally complete.
5. Implement Half Adder. Design and verify Full adder using Half Adder. Implement the
combinational circuit to realize both Adder and Subtractor together.
6. Implement Multiplier, Comparator and code converter.
7. Implementation and verification of Decoder/De-multiplexer, Encoder and Priority Encoder.
8. Implement and verify Ripple Carry Adder, Carry Look Ahead Adder and BCD Adder.
9. Verification of state tables of RS, JK, T and D flip-flops using NAND & NOR gates.
10. Design, and verify synchronous counters.
11. Design, and verify asynchronous counters.
12. Design, and verify shift register.

STUDY AND EVALUATION SCHEME

SESSIONAL EVALUATION: -
ATTENDANCE : 10

LAB PERFORMANCE : 10
ASSIGNMENTS : 10
LAB EXAM : 50
VIVA-VOCE : 20

TOTAL : 100 MARKS

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 EXPERIMENT – 1

Aim: - Introduction to digital logic laboratory, specifications of IC, study of the data sheet,
concept of Vcc, ground and verification of the truth tables.

Apparatus Required: -
Digital Trainer kit, wires, breadboard, IC’s, Wire Cutter

GATE IC
AND 7408
OR 7432
NOT 7404
NAND 7400
NOR 7402
XOR 7486

Theory: -
Logic gates are physical devices implementing a Boolean function. It performs a logical operation
on one or more logical inputs and produce a single output. Depending on the context, the term may
refer to an ideal logic gate, one that has for instance zero rise time and unlimited fan out or it may
refer to a non-ideal physical device.

The main hierarchy of Logic gates are as follows: -

1. Basic Gates
2. Universal Gates
3. Advanced Gates

Basic Gates
1. AND gate:- Function of an AND gate is to give the output true when both the inputs are
true. In all the other remaining cases output becomes false. Following table justifies the
statement: -

Input A Input B Output

0 0 0
0 1 0
1 0 0
1 1 1

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 2. OR gate: - Function of an OR gate is to give output true when at least one of the inputs is
true. Following table justify the statement: -

Input A Input B Output

0 0 0
0 1 1
1 0 1
1 1 1

3. NOT gate: - Function of a NOT gate is to inverse the input. It converts true input to false
and vice versa. Following table justifies the statement: -

Input A Output
0 1
1 0

Universal Gates

1. NAND gate: - Function of a NAND gate is to give true output when at least one of the
inputs is false. Following table justifies the statement: -

Input A Input B Output

0 0 1
0 1 1
1 0 1
1 1 0

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 2. NOR gate: - NOR gate gives the output true when both the inputs are false. In all the other
cases output remains false. Following table justifies the statement: -

Input A Input B Output

0 0 1
0 1 0
1 0 0
1 1 0

Advanced Gates
1. XOR gate: - The function of XOR gate is to give the output true when only one of the
inputs are true. Following table explains this: -

Input A Input B Output

0 0 0
0 1 1
1 0 1
1 1 0

Procedure: -
 Fix the IC which is under observation between the half shadow line of breadboard, so there
is no shortage of voltage.
 Connect a wire to the 5V DC voltage source (Vcc) whose other end is connected to the last
pin of the IC (14th pin).
 Connect the ground of IC (7th pin) to the ground terminal of the trainer kit.
 Connect the input pins of the trainer kit with the input pins of one of the gate of the IC by
using connecting wires. (In accordance to IC provided).
 Connect output pins to the led on the trainer kit.
 Switch on the power supply.
 If the led glows then the output is true, otherwise the output is false, which is numerically
denoted as 1 and 0 respectively.

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Result: -
All gates are verified. Observed output matches with the theoretical concepts.

Precautions: -
 All connections should be made neat and tight.
 Digital lab kits and ICs should be handled with utmost care.
 While making connections main voltage should be kept switched off.
 Never touch live and naked wires.

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 EXPERIMENT – 2

Aim: - Implementation of a given Boolean function using logic gates in both SOP and POS forms
Two input SOP - A’. B + A. B՛
Two input POS - (A+B) (B+C) (A+C՛)

Apparatus required: - Digital Trainer kit, wires, breadboard, IC’s, Wire Cutter
.
Theory: -
a) SOP: - It is the Sum of product form in which the terms are taken as 1. It is denoted in
the K-map expression by sigma (∑)

A’.B. + AB’

Logic Circuit of this expression: -

A B AB’ A’B A’B+AB’

0 0 0 0 0
0 1 0 1 1
1 0 1 0 1
1 1 0 0 0

b) POS: - It is the product of the sums form in which the terms are taken as 0. It is denoted
in the K-Map expression by the Sign pie (π)

(A+B) (B+ C) (A + C՛)

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Circuit Diagram

Result: - The given Boolean Expressions are implemented using IC (7408, 7432, 7404) and truth
tables are verified.

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 EXPERIMENT – 3

Aim:
1. Verify DE Morgan’s law.
2. Verify the Universal logic gate (NAND, NOR).

Apparatus: - IC 7404 (NOT Gate), IC 7408 (AND Gate), IC 7432 (OR Gate), Digital Trainer Kit,
Wires, Wire Cutter.

Theory: De Morgan’s law states that the negation of a disjunction is the conjunction of the
negations; and the negation of a conjunction is the disjunction of the negations; Using Boolean
logic it can be written as:
̅̅̅̅̅̅̅̅
1. 𝐴 + 𝐵 = 𝐴′ . 𝐵′
2. ̅̅̅̅
𝐴𝐵 = 𝐴′ + 𝐵′
NAND and NOR gates are the universal logic gate which implies that any logic function can be
realized using NAND or NOR gate.
Verification: De-Morgan’s law can be verified by implementing the following circuit

The universal logic gates (NAND, NOR) can verified by implementing basic gates (AND, OR,
NOT) using NAND/NOR. The following figures depicts the circuit.

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 NAND as a universal logic gate

NOR as a universal logic gate

Results: De-Morgan’s law and universal logic gate are verified.

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 EXPERIMENT – 4

Aim:
1. Implement NAND based logic circuit for any Boolean expression.
2. Verify that F= AB + A'C' is functionally complete.
Apparatus: - IC 7400 (NAND Gate), 7408 (AND gate), 7432 (OR gate), 7404 (NOT gate),
Digital Trainer Kit, Wires, Wire Cutter.
Theory
In this experiment XOR gate and XNOR gate will be implemented using only NAND gate.
Functionally completeness of the expression F= AB + A'C' can verified by implementing AND
gate and NOT gate or OR gate and NOT gate using this expression. Functionally completeness
denotes that any logical function can by implemented using the mentioned function.
Circuit Diagram:

XNOR Gate using NAND

The completeness of the function F(A, B, C) = AB + A'C' can be verified by the following
F(A, B, 1) = AB + A'1'= AB (AND gate)
F(0, 0, C) = 0.0+ O'C'= C' (NOT gate)
Implement the above two equations to verify them.
Results:, XOR and XNOR has been implemented using NAND gate. Functionality completeness
of the function F= AB + A'C' has been verified.

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 EXPERIMENT – 5

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 A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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 EXPERIMENT – 6

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 EXPERIMENT – 7

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 EXPERIMENT – 8

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 EXPERIMENT – 9

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 EXPERIMENT – 10

Aim: -
Design and verify the 4-bit synchronous up, down and up-down counter using J k flip-flop

Apparatus Required: -
IC7476 (J K flip-flop), IC 7408 (AND Gate), Digital Trainer kit, wires, breadboard, IC’s, Wire
Cutter

Theory: -
The counters which use clock signal to change their transition are called “Synchronous
counters”. This means the synchronous counters depends on their clock input to change state
values. In synchronous counters, all flip flops are connected to the same clock signal and all flip
flops will trigger at the same time.

State Table

Clock pulse Q4 Q3 Q2 Q1 Output Output

1st Low Low Low Low 0 0
2nd Low Low Low High 1 1
3rd Low Low High Low 2 10
4th Low Low High High 3 11
5th Low High Low Low 4 100
6th Low High Low High 5 101
7th Low High High Low 6 110
8th Low High High High 7 111
9th High Low Low Low 8 1000
10th High Low Low High 9 1001
11th High Low High Low 10 1010
12th High Low High High 11 1011
13th High High Low Low 12 1100
14th High High Low High 13 1101
15th High High High Low 14 1110
16th High High High High 15 1111

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Diagram

4 bit Synchronous up-counter

4 bit Synchronous down-counter

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 4 bit Synchronous up-down counter

Result: - All type of synchronous counters has been implemented using J K flip-flop with
variable configuration.

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 EXPERIMENT – 11

Aim: -
Design and verify the asynchronous up, down counter using D flip-flop and up-down counter
using J K flip-flop.

Apparatus Required: -
IC7474 (D flip flop), IC7476 (J K flip-flop), IC 7408 (AND Gate), Digital Trainer kit, wires,
breadboard, IC’s, Wire Cutter

Theory: -
Asynchronous counters are those whose output is free from the clock signal. Because the flip
flops in asynchronous counters are supplied with different clock signals, there may be delay in
producing output. The required number of logic gates to design asynchronous counters is very
less. So they are simple in design. Another name for Asynchronous counters is “Ripple
counters”. The number of flip flops used in a ripple counter is depends up on the number of
states of counter (ex: Mod 4, Mod 2 etc). The number of output states of counter is called
“Modulus” or “MOD” of the counter. The maximum number of states that a counter can have is
2n where n represents the number of flip flops used in counter. For example, if we have 2 flip
flops, the maximum number of outputs of the counter is 4 i.e. 22. So it is called as “MOD-4
counter” or “Modulus 4 counter”.

Diagram

4 bit Asynchronous up-counter

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 4 bit Asynchronous down-counter

3 bit Asynchronous up-down counter

Result: - All type of Asynchronous counters has been implemented.

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 EXPERIMENT – 12

Aim: -
Design and verify a 4 bit unidirectional shift register

Apparatus Required: -
IC7474 (D flip flop), Digital Trainer kit, wires, breadboard, IC’s, Wire Cutter

Theory: -
Flip flops can store a single bit of binary data i.e. 1 or 0. But if we need to store multiple bits of
data, we need multiple flip flops. As a single flip flop is used for one bit storage, n flip flops are
connected in an order to store n bits of data. In digital electronics, a Register is a device which is
used to store the information. Register is a group of flip flops used to store multiple bits of data.
For example, if a computer is to store 4 bit data, then it needs a set of 4 flip flops. The input and
outputs of a register are may be serial or parallel based on the requirement. When a number of flip
flops are connected in series, this arrangement is called a Shift Register. A shift register is a
sequential circuit which stores the data and shifts it towards the output on every clock cycle.

Diagram: -

4 bit unidirectional shift register

Result: -
All gates are verified. Observed output matches with the theoretical concepts.

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