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Finite State Machine (FSM) When the sequence of actions in your design depend on the state of sequential elements, a finite state machine (FSM) can be implemented FSMs are widely used in applications that require prescribed sequential activity
Example:
Sequence Detector Fancy counters Traffic Light Controller Data-path Controller Device Interface Controller etc.

Finite State Machine (FSM) (cont.) All state machines have the general feedback structure consisting of:
Combinational logic implements the next state logic
Next state (ns) of the machine is formed from the current state (cs) and the current inputs

State register holds the value of current state

Next State Inputs

Next-State Logic

Memory

Current State

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Types of State Machines Moore State Machine

Inputs

ns Next-State Logic State Register

cs Output Logic

Outputs

Next state depends on the current state and the inputs but the output depends only on the present state
next_state(t) = h(current_state(t), input(t)) output = g(current_state(t))

Types of State Machines (cont.) Mealy State Machine

Output Logic

Inputs

ns Next-State Logic State Register

cs

Outputs

Next state and the outputs depend on the current state and the inputs
next_state(t) = h(current_state(t), input(t)) output(t) = g(current_state(t), input(t))

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Typical Structure of a FSM

module mod_name ( ); input ; output ; parameter size = ; reg [size-1: 0] current_state; wire [size-1: 0] next_state; // State definitions `define state_0 2'b00 `define state_1 2b01 always @ (current_state or the_inputs) begin // Decode for next_state with case or if statement // Use blocked assignments for all register transfers to ensure // no race conditions with synchronous assignments end always @ (negedge reset or posedge clk) begin if (reset == 1'b0) current_state <= state_0; else current_state <= next_state; end //Output assignments endmodule

Next State Logic

State Register

Sequence Detector FSM

Functionality: Detect two successive 0s or 1s in the serial input bit stream

reset reset_state 0 1

out_bit = 0
1

FSM Flow-Chart

out_bit = 0 read_1_zero
0 0 0

read_1_one

out_bit = 0

read_2_zero

read_2_one

out_bit = 1

out_bit = 1

; et at s _t e s er = et at s _t x e n ; e n o _ 1 _ d a er = et at s _t x e n ) 1 = = ti b _ ni ( ; or e z _ 2 _ d a er = et at s _t x e n ) 0 = = ti b _ ni ( : ; et at s _t e s er = et at s _t x e n ; e n o _ 1 _ d a er = et at s _t x e n ) 1 = = ti b _ ni ( ; or e z _ 2 _ d a er = et at s _t x e n ) 0 = = ti b _ ni ( : ; et at s _t e s er = et at s _t x e n ; e n o _ 1 _ d a er = et at s _t x e n ) 1 = = ti b _ ni ( ; or e z _ 1 _ d a er = et at s _t x e n

)ti b _ ni

Sequence Detector FSM (cont.)

Sequence Detector FSM (cont.)

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4
; 0 : 1 ? ) ) e n o _ 2 _ d a e r = = g e r _ et at s ( || ) o r e z _ 2 _ d a e r = = g e r _ et at s ( ( = ti b _t u o

e udomdne e udomdne elllludomdne e udomdne ng ssa ngiissa

esacdne esacdne esacdne esacdne :::tttllluafffed ua ed ua ed es e es e eslllle es e

es es ffffiiii esllll es

ffffiiii eno_2_daer es e es e eslllle es e es e es e ffffiiii eslllle es e ffffiiii eno_1_daer

; et at s _t e s er = et at s _t x e n ; et at s _t e s er = et at s _t x e n ; e n o _ 2 _ d a er = et at s _t x e n ) 1 = = ti b _ ni ( e ; or e z _ 1 _ d a er = et at s _t x e n ) 0 = = ti b _ ni ( : ; et at s _t e s er = et at s _t x e n ; e n o _ 2 _ d a er = et at s _t x e n ) 1 = = ti b _ ni ( ; or e z _ 1 _ d a er = et at s _t x e n ) 0 = = ti b _ ni ( :

es e es e esllle

fi e sl e

ciiiigollll ettttatttts--ttttxen //////// c go e a s xen c go e a s-- xen c go e a s xen

; et at s _t x e n = < g er _ et at s ; et at s _t e s er = < g er _ et at s

fi orrez_2_daerr o ez_2_dae orrez_2_daerr o ez_2_dae e sl e fi e sl e fi orrez_1_daerr o ez_1_dae orrez_1_daerr o ez_1_dae e sl e fi e sl e

es e es e eslllle es e

)t e s er

) 1 = = t e s e r ( fi egdesop rro egdesop o egdesop @ syaw a egdesop @ syaw a egdesop rro kcolc egdesop( @ syawlllla egdesop o egdesop @ syaw a retsiger etats // ; 0 0 1 b' 3 ; 1 1 0 b' 3 ; 0 1 0 b' 3 ; 1 0 0 b' 3 ; 0 0 0 b' 3 = e n o _ 2 _ d a er = or e z _ 2 _ d a er = e n o _ 1 _ d a er = or e z _ 1 _ d a er = et at s _t e s er

rre emarrap e ema ap rrettttemarrap e ema ap re emarap e ema ap rretttemarrap retemarap rre emarrap e ema ap rrettttemarrap e ema ap rre emarrap e ema ap rrettttemarrap e ema ap noitaralced etatS // gerr ge gerr ge up uo up uo ttttupttttuo up uo upn upn ttttupniiii upn eludom

; et at s _t x e n , g er _ et at s ] 0: 2[ ;ti b _t u o ;ti b _ ni ,t e s e r , k c ol c ; )ti b _t u o ,ti b _ ni ,t e s e r , k c ol c ( t c et e d _ q e s

) 0 = = ti b _ ni ( fi etttattts_ttteserr e a s _ e s er :etats_teser e a s_ ese ) g er _ et at s( e s a c rro o @ syaw a @ syaw a rro ger_etats( @ syawlllla o @ syaw a

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First-in First-out Memory (FIFO)

A FIFO consists of block of memory and a controller that manages the traffic of data to and from the FIFO A FIFO provides access to only one register cell at a time (not the entire array of registers) A FIFO has two address pointers, one for writing to the next available cell, and another one for reading the next unread cell The pointers for reading and writing are relocated dynamically as commands to read or write are received A pointer is moved after each operation A FIFO can receive data until it is full and can be read until it is empty

FIFO Features (cont.)

A FIFO has:
Separate address pointers and datapaths for reading and writing data Status lines indicating the condition of the stack (full, almost full, empty etc.)

The input (write) and output (read) domains can be synchronized by two separate clocks, allowing the FIFO to act as a buffer between two clock domains (Dual Clock FIFOs) A FIFO can allow simultaneous reading and writing of data (however
synchronization is necessary if read/write parts are different clock domains)

The write signal is synchronized to the read clock using clock synchronizers FIFOs are usually implemented with dual-port RAMs with independent read- and write-address pointers and registered data ports (see www.idt.com)

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FIFO Structure
stack_height -1

data_in write_to_stack clk_write

stack_full stack_half stack_empty data_out read_from_stack

FIFO Buffer

rst

clk_read

Internal Signals
write_ptr

0 stack_width -1 0

Input-output Ports
read_ptr

Example: Synchronous FIFO with handshake PUSH Side POP Side

DATA_in VALID_in STALL_out

DATA_out

FIFO
{DEPTH, WIDTH}
clk rst

VALID_out stall_in

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FIFO SPECIFICATION Parametric WIDTH PARAMETRIC DEPT ( >= 2) Simple handshake based on stall-go flow control protocol
To push data in the fifo, the valid is must be 1 and stall_out must be 0 To pop data from the fifo, stall_in must be 0, and valid_out ust be 1. When the fifo is FULL the stall_out must be 1; When the fifo is empty, valid_out out must be 0.

The latency of the FIFO must be 1 clock cycle The FIFO must allow simultaneous reading and writing of data Use a FF based asynchronous read-synchronous write dual port RAM

Example: FIFO

VALID FULL - S TALL clk rs t FS M

VALID S TALL - ( ! REQUES T)

P US H P ointer EN 0 1 DATA 2 3 4

P OP P ointe r

DATA

n-1

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Validation: Functional Test

testbench. v Stimuli

Simple_Adder.v DATA VALID STALL DATA VALID STALL

FIFO

reset

clock