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Mini Project - FSM

This document describes implementing a Mealy finite state machine (FSM) using VHDL. A Mealy FSM uses both the input and current state to determine the next state and output. The document provides details on Mealy FSM logic and writes VHDL code to design a Mealy FSM with 4 states. It shows the RTL view and simulation results of the VHDL code, demonstrating the implementation of a Mealy FSM.

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Parth Shah
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279 views5 pages

Mini Project - FSM

This document describes implementing a Mealy finite state machine (FSM) using VHDL. A Mealy FSM uses both the input and current state to determine the next state and output. The document provides details on Mealy FSM logic and writes VHDL code to design a Mealy FSM with 4 states. It shows the RTL view and simulation results of the VHDL code, demonstrating the implementation of a Mealy FSM.

Uploaded by

Parth Shah
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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ELECTRONICS AND COMMUNICATION ENGG DEPT.

GOVERNMENT ENGINEERING COLLEGE, SECTOR -28, GANDHINAGAR-302028

MINI PROJECT
AIM : IMPLEMENTATION OF Mealy FSM (Finite State Machine) USING VHDL. Description:
A finite-state machine (FSM) is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one state at a time;

The state it is in at any given time is called the current state. It can change from one state to another when initiated by a triggering event or condition, this is called a transition.

Mealy FSM uses only input actions, i.e., output depends on input and state. The use of a Mealy FSM leads often to a reduction of the number of states. Mealy FSM Logic

VLSI TECHNOLOGY AND DESIGN

Subject Code: 161004

ELECTRONICS AND COMMUNICATION ENGG DEPT.

GOVERNMENT ENGINEERING COLLEGE, SECTOR -28, GANDHINAGAR-302028

sThe next state and output of an FSM is a function of the input and of the current state.

VHDL Code:
library ieee; use IEEE.std_logic_1164.all; entity fsm is port (clk : in std_logic; reset : in std_logic; input : in std_logic; output : out std_logic ); end fsm; architecture behavioral of fsm is type state_type is (s0,s1,s2,s3); signal current_s,next_s: state_type; begin process (clk,reset) begin if (reset='1') then current_s <= s0; elsif (rising_edge(clk)) then current_s <= next_s; end if; end process; process (current_s,input) begin case current_s is when s0 => VLSI TECHNOLOGY AND DESIGN Subject Code: 161004

ELECTRONICS AND COMMUNICATION ENGG DEPT.

GOVERNMENT ENGINEERING COLLEGE, SECTOR -28, GANDHINAGAR-302028

if(input ='0') then output <= '0'; next_s <= s1; else output <= '1'; next_s <= s2; end if; when s1 => if(input ='0') then output <= '0'; next_s <= s3; else output <= '0'; next_s <= s1; end if; when s2 => if(input ='0') then output <= '1'; next_s <= s2; else output <= '0'; next_s <= s3; end if;

when s3 => if(input ='0') then output <= '1'; next_s <= s3; else output <= '1'; next_s <= s0; end if; end case; end process; end behavioral;

VLSI TECHNOLOGY AND DESIGN

Subject Code: 161004

ELECTRONICS AND COMMUNICATION ENGG DEPT.

GOVERNMENT ENGINEERING COLLEGE, SECTOR -28, GANDHINAGAR-302028

RTL View:

Simulation Result:

VLSI TECHNOLOGY AND DESIGN

Subject Code: 161004

ELECTRONICS AND COMMUNICATION ENGG DEPT.

GOVERNMENT ENGINEERING COLLEGE, SECTOR -28, GANDHINAGAR-302028

Conclusion: This way we can design & implement mealy FSM in VHDL.

VLSI TECHNOLOGY AND DESIGN

Subject Code: 161004

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