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Paper Title: On Obtaining Maximum Length Sequences for Accumulator-Based

Serial TPG
Authors: D. Kagaris, P. Karpodinis, and D. Nikolos


Contact Author : D. Kagaris
Electrical & Computer Eng. Dept.,
Southern Illinois University,
Carbondale, IL 62901, USA
Voice : (618) 453 7973
FAX : (618) 453 7972
e-mail: [email protected]








2
On Obtaining Maximum Length Sequences for
Accumulator-Based Serial TPG

D. Kagaris
1
, P. Karpodinis
2,3
, and D. Nikolos
2,3

1
Electrical & Computer Eng. Dept., Southern Illinois University, Carbondale, IL 62901, USA

2
Computer Engineering & Informatics Dept., University of Patras, 26500 Greece
3
Computer Technology Institute, 3 Kolokotroni St., 262 21 Patras, Greece
[email protected], [email protected], [email protected]


ABSTRACT
Arithmetic function modules, which are available in many circuits, can be utilized to
generate test patterns and compact test responses. In this paper, we propose an accumulator-
based scheme along with a procedure to find maximum length sequences for bit serial Test
Pattern Generators. The proposed scheme achieves good fault coverage with low hardware
overhead and short test sequences.

1. Introduction
BuiltIn SelfTest (BIST) [1-4] is a design for testability strategy that reduces the need
for external test and can be used
1
to determine faulty parts at all levels in the hierarchy (core to
chip to board to system) during manufacture and to diagnose problems in the field. In BIST test
pattern generation, response monitoring and evaluation are handled on-chip with the use of extra
hardware structures. Common BIST schemes used in practice for many years are based on the
use of Linear Feedback Shift Registers (LFSRs) or cellular automata for test pattern generation
and response compaction. Such conventional approaches impose hardware overhead and may
lead to performance degradation, during normal operation mode, due to the insertion of extra
multiplexers in the signal paths.
Recently, new Arithmetic-BIST [5-13] schemes were proposed based on the use of
adders, subtracters, multipliers and shifter modules that already exist in modern general purpose
processors and digital signal processing units. The advantage of Arithmetic-BIST against the

A preliminary version of this paper was presented in the 10

th
IEEE International OnLine Testing
Symposium (IOLTS) and it is included in the conference proccedings: P. Karpodinis, D. Kagaris, and D.
Nikolos, Accumulator Based Test-per-Scan BIST. Proccedings of the 10
th
IEEE International OnLine
Testing Symposium, pages 193-198, 2004.

This research was partially supported by the EPEAEK-II Pythagoras Program.

3
LFSR-based BIST is that due to the reuse of existing on-chip modules, hardware overhead and
performance degradation are reduced or virtually eliminated. Arithmetic BIST schemes for test-
per-clock as well as for test-per-scan environment have been considered [6-13]. In this paper we
concentrate on the arithmetic test-per-scan BIST environment. Test-per-scan BIST can find
application in:

Sequential circuits with scan paths.
Embedded cores with an isolation ring.
Circuits with boundary scan.
Portions of multi-chip modules, which require the transfer of test data in a bit-serial way.

The quality of the random properties of the bit serial test sequence generated by a bit
position of an accumulator or an adder is poor [11]. Although the fault coverage can be
improved using a parallel/serial accumulator (in that case the register of the parallel accumulator
is modified to function as a shift register), it remains generally low even for long test sequences.
Therefore these simple arithmetic units cannot be used efficiently for bit serial test pattern
generation. To this end, three new bit serial test pattern generation schemes based on the use of
adder-multiplier or accumulator-multiplier pairs were recently proposed in [10, 11]. These
schemes compared to an LFSR bit serial test pattern generator have the advantage that achieve
similar fault coverage with similar number of test patterns, while they do not impose any
hardware overhead since they are already part of the functional circuit. The disadvantages of the
schemes proposed in [10, 11] can be summarized to the following:

1. Their applicability is limited to applications in which the required configuration of the
adder-multiplier or accumulator-multiplier is available and
2. since a multiplier-adder or multiplier-accumulator is used for test pattern generation,
these schemes have increased power and energy consumption during testing.

Recently in [12] it was shown that an accumulator can be modified to operate, in test
mode, as a Non-Linear Feedback Shift Register (NLFSR) and that it can be used effectively for
bit-serial test pattern generation [13] as well as for test response compaction [12, 14]. The
disadvantage of this test pattern generator is that often prohibitively long time is required for
finding a pair of accumulator initial value and Constant Additive Value (CAV) for which the
generated sequence is efficient with respect to its length and the achieved fault coverage. In this
paper we propose a slightly different accumulator based configuration which has the great





4
advantage that the effort required for finding an efficient test sequence is similar to the effort
required in the case that the test pattern generator is an LFSR. Furthermore, the proposed
accumulator based configuration in most cases compares favorably to LFSRs and the other
arithmetic-function-based bit-serial sequence generators with respect to the attainable fault
coverage and the required test sequence length.
The rest of the paper is organized as follows: The next section reviews bit serial test
pattern generation schemes based on arithmetic units. Section 3 presents the new accumulator-
based bit serial test pattern generation scheme. Section 4 gives comparative experimental results
of the proposed scheme with previous schemes, and Section 5 concludes

2. Arithmetic-based Bit-Serial Test Pattern Generators
Bit-serial test pattern generation based on arithmetic units was firstly investigated in [10].
In particular Rajski and Tysjer [10] presented a datapath configuration which consists of a K
K multiplier, a 2K 2K adder and 2K register (see Figure 1).
A d d e r
M u l t i p l i e r
S
e
l
e
c
t
R e g i s t e r
2 K
2 K
K
M
K

Figure 1. The multiplier-accumulator structure presented in [10] for bit-serial test pattern
generation.
In each step the K lower significant bits of the register are multiplied with a constant M and the
product is added to the rest K most significant bits of the register. Thus the state transitions are
described by the following equation:

R(t) = [MR
(L)
(t-1) + R
(H)
(t-1)] mod 2
2K






5
where R(t) denotes the contents of the register, while R
(L)
(t) and R
(H)
(t) are the K less significant
and the K most significant bits of the register respectively. The bit-sequence that feeds the scan
path is generated by the least significant bit position of the register. The constants M, which
guarantee a maximum period, have been derived experimentally for K = 3 up to 16 along with
the corresponding period for each K.
All application specific circuits are tailored to and optimized for specific tasks. Hence,
their busses do not connect registers and functional units in a completely regular fashion. In
order to cope with the variety of hardware structures Stroele [11] asserts that we need a set of
many different pattern generators. Then we will be able to choose those pattern generators that
can be easily configured from the available arithmetic function units and are best suited for the
specific situation. To this end Stroele [11] investigated the suitability of several simple and
more complex arithmetic modules for bit-serial test pattern generation.
Stroele [11] shown that 2's complement adders, 1's complement adders as well as stored
overflow bit adders are not suitable for bit-serial test pattern generation due to the poor random
quality of the sequences generated from any bit position. Stroele [11] has also investigated the
capabilities of two additional schemes called Multiply & Add and Multiply & Accumulate
respectively (see Figure 2).
( b )
A d d e r
M U X
R e g i s t e r
S h i f t e r
M u l t i p l i e r
2 K
2 K
2 K
2 K
w
2 K
K
A d d e r
R e g i s t e r
S h i f t e r
M u l t i p l i e r
u
w
2 K
2 K
K
( a )
u

Figure 2. The Multiply-Add (a), and the Multiply-Accumulate (b) schemes [11].






6
The first one consists of a K K multiplier, a 2K 2K adder and register, while the design is
completed with the use of an extra shifter which selects in every step the K-lower significant
bits of the register. The state transitions are described by the following equation:

R(t) = [wR
(L)
(t-1) + u] mod 2
2K


which in other words means that in each time step the lower significant bits of the register are
multiplied with a constant w and the product is added to u. As presented in [11] the sequence
generated by the multiply-add configuration consists of a long cycle passing through 2
K
states,
when the constant additive value u is odd and the constant w is an element of {4x+1 | x N}.
The source of the serial random vectors is the bit position R
K-1
, which generates bit-sequences
with period 2
K
.
The second structure needs an extra 2K bits wide 2-to-1 multiplexer and a new pattern
is produced in every two cycles. During the first cycle the K-lower significant bits of the register
R
(L)
(t) are multiplied with the constant w and the product is added to the contents of the register.
In the second cycle the constant additive value u is also added to the register's value. The
presented function is described by the following recursive equations:

R(t+1) = [R(t) + wR
(L)
(t)] mod 2
2K
, and
R(t+2) = [R(t+1) + u] mod 2
2K

The Multiply-Accumulate configuration generates random patterns with period 2
2K
when the
constant additive value u is odd and the constant w is a multiple of 4. Then the sequence
produced by the most significant bit of the register has exactly the same period.
The use of one of the above mentioned bit-serial sequence generators, supposes the
availability of the corresponding adder-multiplier or accumulator-multiplier configuration in the
circuit. In [13] it was shown that an accumulator behaving, in test mode, as an NLFSR can be
used efficiently for bit-serial test pattern generation. The structure proposed in [13] (figure 3)
consists of a K-bit adder, a K-bit register, K 2-to-1 multiplexers M
0
, M
1
, , M
K-1
, a XOR gate
and an extra flip-flop (D-FF). In normal mode, T = 0, the output R
i
, 0 i K-1, of the register
drives the B
i
input of the adder, while the exclusive-OR gate and the D-FF flip-flop are not used.
In test mode, T = 1, the output R
i
, 0 i K-1, of the register drives the B
i+1
input of the adder
and the output R
K
along with the output carry (of the adder) feed the additional exclusive-OR
gate. Additionally, the output of the D-FF flip-flop drives the B
0
input of the adder while C
in

receives the value zero. Functionally we can say that in test mode the contents of the register are





7
shifted one position to the left and are then added with a constant value u and the value D of the
D-FF flip-flop. We store the K bits of the result are stored back to the register and the K-bit at
the D-FF. The functionality of the above scheme can be described by the following equations:

1 K
1 K
[2s(t) u] mod2 , s(t) 2
s(t 1)
[2s(t) u 1] mod2 , s(t) 2
K
K
+
+
+ <
+ =

+ +

M
K-2
Adder
M
2
M
1
M
0
Register
D-FF
. . .
M
K-1
CAV u
K
K
. . .
.

.

.
C
in
C
out
R
0
R
1
R
K-2
R
K-1
A B
S

Figure 3: The Accumulator behaving in test mode as a NLFSR scheme [13].

where s(t) denotes the state of the register R(t) and the extra flip-flop D(t), considering D(t) as
the most significant bit of the s(t).
Several constant additive values have been derived experimentally for K = 5 up to K =
31, but for many values of K (such as 7, 10, 12, 13, 17, 20, 22, 24, 26, 28, 30, 31), CAVs
achieving maximum period bit sequences do not exist. The Most Significant Bit of the Register
(R
K-1
) was chosen to be the source of the random test sequence. Hereafter, the above scheme
will be called ANLFSR.
A modification is also presented in [13] where the bit sequence generated from the
output of an exclusive-OR gate that receives as inputs the sequences generated by the most
significant bits of the upper and the lower half of the register has better random properties. This
scheme will be referred to as Enhanced ANLFSR, EANLFSR.





8
We have to note that any of the schemes proposed in [10,11,13] can also be implemented
in software in a microprocessor environment.

3. The Proposed Scheme
3.1 Hardware Description
The basic module of the proposed test pattern generator scheme is similar to the architecture
proposed in [13]. Thus, it consists of a K-bit adder and a K-bit register, while the structure is

M
K-1
Adder
M
2
M
1
M
0
Register
D-FF
. . .
M
K-2
CAV u
K
K
. . .
.

.

.
C
in
C
out
R
0
R
1
R
K-2
R
K-1
R
b
A B
S


Figure 4: The proposed Accumulator-XOR (ACC-XOR) scheme.

completed with the use of K 2-to-1 multiplexers, an exclusive-OR gate, and an extra D flip-flop.
Furthermore, the proposed architecture uses an extra exclusive-OR gate, as shown in Figure 4.
During normal mode, i.e., T = 0, the ith bit of the register, denoted as
i
R , 0 i K-1, drives
the ith bit of the input of the adder,
i
B . During test mode the bit
i
R , 0 i K-1, drives the
1 i
B
+

input of the adder and the most significant bit of the register,
1 K
R , feeds the exclusive-OR





9
gate, along with the outcome carry of the addition. Moreover, the extra exclusive-OR gate is fed
by the output of the D flip-flop, along with one bit position of the K -bit register. The outcome
of the extra exclusive-OR gate feeds the least significant bit position
0
B of the adder.
Assume that ( ) s t denotes the state of the K-bit register, ( ) R t , and ( ) D t the state of the extra D
flip-flop, considering ( ) D t as the most-significant bit of ( ) s t . Also, let T denote the output of
the extra exclusive-OR gate. Then, the next state ( 1) s t + can be described by the following
equation:
1
( 1) [2 ( ) ] mod 2
K
s t s t u T
+
+ = + + (6)

We will refer to the ACC-XOR scheme with size K , bit position (for the XOR) b , and
CAV u as ( ) A K b u , , . We are of cource interested in ( ) A K b u , , schemes which have
maximum period sequences. A scheme with cycle period of
1
2 1
K+
will be refered to as
primitive, borrowing the term from the linear case.
Stroele has proven [9] that if the transition diagram, of an arbitrary finite state machine
with K -state bits, contains state sequences of period 2
K
-1, then the generated bit sequence of
each bit position i, i=0,1,,k-1 has period 2
K
-1. Therefore, when the proposed test pattern
generator, with K+1 state bits, operates under a constant input and produces a state cycle of
length 2
K+1
-1, then the sequence generated from the j-th bit position, 0 1 j K , has also
period 2
K+1
-1.
Since bit serial test pattern generation is our primary interest, we can choose in principle
any of these bit positions. We have chosen to use the Most Significant Bit of the Register (R
K-1
)
as the source of the random test sequence, based upon the observation in [15] which states that
the least significant bits of a pseudorandom number sequence are much less random than the
most significant ones.

3.2 Finding primitive A(K, b, u) schemes
A brute force approach to test for primitive ( ) A K b u , , schemes is prohibitive, as it requires
2 2
K K
K simulation steps. In the following we propose a procedure to speed up the search,
based on the following basic lemmas:

Lemma 1.1 The result of XORing the bit at position b (starting from 0) with the carry bit (at
position K ) is given by





10
( )%2
2 2
K b
s s
r
( (
= +
( (

,

where % denotes the modulo (mod) operator.
Proof: The result of XORing the bit at position b (indexing starting from 0) with the carry bit
(at position K) can, by definition, be expressed mathematically as

1
%2
( )%2
2 2
b
K b
s s
r
+
(
(
= +
(
(


(1)

Let the quotient and remainder of s in the division by
1
2
b+
be
1
q and
1
r respectively, that
is,
1
1 1
2
b
s q r
+
= + . Let also
2
q and
2
r be the quotient and remainder of
1
r in the division by
2
b
, that is,
1 2 2
2
b
r q r = + . Finally, let
3
q and
3
r be the quotient and remainder of s in the
division by 2
b
, that is,
3 3
2
b
s q r = + . Then
1
1 2 2 3 3
2 2 2
b b b
s q q r q r
+
= + + = + , from which
it follows simultaneously that
2 3
r r = and
3 1 2
2 q q q = + due to the integer division property.
In particular,
3 2
mod 2 q q = and so by replacing
3 2
q q , with their equivalent expressions we
have
%2
( )%2
2 2 2
b
b K b
s s s (
( (
= +
(
( (


. So (1) can be rewritten as ( )%2
2 2
K b
s s
r
( (
= +
( (

.

The search for ACC-XOR schemes of given length K resulting in maximum length
sequences involves in principle the trial of all pairs of b and u values, where 0 1 b K ,
1 2 1
K
u , and the identification through simulation of the cyclic structure of the resulting
states. To speed up the search, we eliminate several ( ) A K b u , , schemes based on the following
criteria:

(I) elimination of certain ( ) A K b u , , schemes that cannot be primitive, based only on
mathematical formulas, and not on simulation
(II) elimination of certain ( ) A K b u , , schemes that cannot be primitive, based on the
identification, through simulation, of a certain non-primitive ( ) , , A K b u scheme
with > u u .








11
3.2.1 Elimination without simulation
The nonprimitiveness of several ( ) A K b u , , schemes can be determined a priori through
mathematical formulas, based on the following lemmas and theorems:

Lemma 1.2 If
1
2
2
K
b
u
+
(
(

is odd, then ( ) A K b u , , contains a cycle of length 1 (state
1
2
+

K
u ).
Proof: Let s be a state such that
1
2
K
s u
+
= . Then the next state is
1
[2 ( ) 2] 2
2 2
K
K b
s s
s s u % %
+
( (
= + + +
( (

, that is,

1 1
1 1
2 2
[2 2 2 ( ) 2] 2
2 2
K K
K K
K b
u u
s u u % %
+ +
+ +
( (
= + + +
( (

. Since 2
K
u < , we have that
1
2
1
2
K
K
u
+
(
=
(

. Since
1
2
2
K
b
u
+
(
(

is odd, the term inside parentheses above is even and so it is
equal to 0 mod 2. Therefore,

1 1 1 1 1 1
[2 2 2 ] 2 (2 (2 )) 2 2
K K K K K K
s u u % u % u s
+ + + + + +
= + = + = = .

Lemma 1.3 If
1
2 1
2
K
b
u
+
(
(

is even, then ( ) A K b u , , contains a cycle of length 1 (state
1
2 1
+

K
u ).

Proof: Let s be a state such that
1
2 1
K
s u
+
= . Then the next state is
1
[2 ( ) 2] 2
2 2
K
K b
s s
s s u % %
+
( (
= + + +
( (

, that is,
1 1
1 1
2 1 2 1
[2 2 2 2 ( ) 2] 2
2 2
K K
K K
K b
u u
s u u % %
+ +
+ +
( (
= + + +
( (

. Since 2
K
u < ,
we have that
1
2 1
1
2
K
b
u
+
(
=
(

. Since
1
2 1
2
K
b
u
+
(
(

is even, the term inside parentheses
above is odd and so it is equal to 1 mod 2. Therefore,
1 1 1 1 1 1
[2 2 2 2 1] 2 (2 (2 1)) 2 2 1
K K K K K K
s u u % u % u s
+ + + + + +
= + + = + = = .

If the relations in the Lemmas 1.2 and 1.3 above hold simultaneously for some ( ) A K b u , , ,
then we have:





12
Theorem 1.1 If for some ( ) A K b u , , scheme,
1
2
2
K
b
u
+
(
(

is odd and
1
2 1
2
K
b
u
+
(
(

is even,
then that scheme is not primitive.


By a similar proof we have also the following lemmas:

Lemma 1.4 If
1
2
2
K
b
u
+
(
(

is even, then ( ) A K b u , , contains a cycle of length 1 (state
1
2 1
+

K
u ).

Lemma 1.5 If
1
2 1
2
K
b
u
+
(
(

is odd, then ( ) A K b u , , contains a cycle of length 1 (state
1
2
+

K
u ).

If the relations in the lemmas 1.4 and 1.5 above hold simultaneously for some ( ) A K b u , , , then
we have:

Theorem 1.2 If for some ( ) A K b u , , scheme,
1
2
2
K
b
u
+
(
(

is even and
1
2 1
2
K
b
u
+
(
(

is odd,
then that scheme is not primitive.


For example, by Theorem 1.1 the scheme (5 3 24) A , , is not primitive as it contains two cycles
of length 1 on states 40 and 39. Scheme (5 3 16) A , , is also not primitive according to the
Theorem 1.2, as it contains two cycles of length 1 on states 48 and 47.

3.2.2 Elimination through simulation
The general idea here is the following: Assume that for some scheme ( ) A K b u , , we have
found by simulation that it contains a cycle of length
1
2 1
K
l
+
< and the states in the cycle
satisfy certain conditions specified below. Then a cycle of the same length will also be present
in scheme ( ) A K b u x , , + , for an appropriate value of x , preventing ( ) A K b u x , , + from
being primitive. This is based on the following lemmas and theorems:






13
Lemma 1.6 Successive states
l
s s s , , ,
2 1
of ) , , ( u b K A correspond to successive states
l
s s s , , ,
2 1
of ) , , ( u b K A with x s s
i i
= where x u u = , provided that

0 2 %
2 2 2 2
=
|
|
.
|

\
|
(

+
(

b
i
b
i
K
i
K
i
x s s x s s


Proof: Consider states
1
s and
1
s of ) , , ( u b K A and ) , , ( ) , , ( x u b K A u b K A + = respectively,
such that x s s =
1 1
. The next state
1 +

i
s is given as

1
1
2 % 2 %
2 2
2
+
+
|
|
.
|

\
|
|
|
.
|

\
|
(

+
(

+ + =
K
b
i
K
i
i i
s s
u s s

and by induction on the relation x s s
i i
= ,
1
1
2 % 2 %
2 2
) ( ) ( 2
+
+
|
|
.
|

\
|
|
|
.
|

\
|
(

+
(

+ + + =
K
b
i
K
i
i i
x s x s
x u x s s
But
1
1
2 % 2 %
2 2
2
+
+
|
|
.
|

\
|
|
|
.
|

\
|
(

+
(

+ + =
K
b
i
K
i
i i
s s
u s s
from which it follows that
x s s
i i
=
+ + 1 1

provided that
0 2 %
2 2 2 2
=
|
|
.
|

\
|
(

+
(

b
i
b
i
K
i
K
i
x s s x s s


Theorem 1.3 If scheme ( ) A K b u , , contains a cycle
1 2 1 l
s s s s , , ..., , of length
1
2 1
K
l
+
< such
that the cycle contains no state
i
s , 0 2
K
i
s < < that is a multiple of 2
b
, then a cycle of the same
length containing states
1 2 1
1 1 1 1
l
s s s s , , ..., , exists also in scheme ( 1) A K b u , , + .

Proof: According to Lemma 1.6, the following relation must be satisfied ( 1 = x )






14
0 2 %
2
1
2 2
1
2
=
|
|
.
|

\
|
(

+
(

b
i
b
i
K
i
K
i
s s s s
.

The range of values for
i
s is | | 1 2 0
1

+ K
. Consider the following cases:
(i)
K
i
s 2 = : The first term in the relation above (i.e.,
(

K
i
s
2
) equals 1, the second term
(

K
i
s
2
1
equals 0, the third term
(

b
i
s
2
is even and the fourth term
(

b
i
s
2
1
is odd, making the
overall sum even and thus satisfying the condition.
(ii) 0 =
i
s : The first and third terms are 0. The second term equals
(

K
2
1
in this case, and
since
(
a a = for any real number a , 1
2
1
2
1
=
(
(
(

=
(

K K
. For the same reason, the
fourth term equals 1, making the overall sum even and thus satisfying the condition.
(iii)
b
i
s 2 , for any positive integer , i.e.,
i
s is not a multiple of
b
2 . Then the first and
second terms are equal, and the third and fourth terms are equal also, making the overall sum
even and thus satisfying the condition.
(iv)
b
i
s 2 = , for any positive integer ,
b K
< < 2 0 , i.e.,
i
s is a multiple of
b
2 other than
0 or
K
2 . Then the first and second terms equal 0, the third term equals and the fourth term
equals 1 , making the overall sum odd and thus violating the condition.

Theorem 1.4 If scheme ( ) A K b u , , contains a cycle
1 2 1 l
s s s s , , ..., , of length
1
2 1
K
l
+
< such
that the cycle contains no state
i
s with
1
2 2 2
K K b
i
s
+
< + or
1
0 2
b
i
s
+
< then a cycle of the
same length containing states
1 1 1 1
1 2 1
2 2 2 2
b b b b
l
s s s s
+ + + +
, ,..., , exists also in scheme
( 1) A K b u , , + .

Proof: According to Lemma 1.6, the following relation must be satisfied (
1
2
+
=
b
x )

0 2 %
2
2
2 2
2
2
1 1
=
|
|
.
|

\
|
(

+
(

+ +
b
b
i
b
i
K
b
i
K
i
s s s s
.
Consider the following cases:





15
(i)
1
2 2 2
+
+ <
b K
i
K
s : Since the maximum value of
i
s is 1 2
1

+ K
, term
(

K
i
s
2
in the
relation above equals 1, and term
(

+
K
b
i
s
2
2
1
equals 0. Term
(

+
+
1
1
2
2
b
b
i
s
equals
2
2
2
2

(

=
(

b
i
b
i
s s
. So the overall sum is odd, that is, these values of
i
s violate the
condition. (For the special case 1 = K b , the value
K
i
s 2 = also violates the condition as
term
(

+
K
b
i
s
2
2
1
equals 2.)
(ii)
1
2 0
+
<
b
i
s : Term
(

K
i
s
2
equals 0 (assuming 1 < K b ). Term
(

+
K
b
i
s
2
2
1
equals
1
2
2
2
2
1 1
=
(

=
(

+ +
K
i
b
K
b
i
s s
. The last two terms have even sum for the same reasons as in (i)
above. So the overall sum is odd, that is, these values of
i
s violate the condition. (For the
special case 1 = K b , the value
1
2
+
=
b
i
s also violates the condition as the first term equals
1
2
2
=
(

K
K
, but the second term equals 0
2
2 2
=
(

K
K K
.) For the remaining values of
i
s , the
first term equals the second term and the third term equals the fourth, making the overall sum
even and thus satisfying the condition.

The value of x in Theorem 1.3 is 1 x = and in Theorem 1.4 is
1
2
b
x
+
= . The eliminated
( ) , , A K b u schemes are obtained as follows:

Assume that we have found by simulation that scheme ( ) A K b u , , contains a cycle
satisfying the condition in Theorem 1.3. Let d be the minimum amount among all states in
the cycle by which a state can be reduced without becoming a multiple of 2
b
other than 0 or
2
K
. Then we know that all schemes ( 1), ( 2),..., ( ) A K b u A K b u A K b u d , , + , , + , , + are
also nonprimitive.
Assume that we have found by simulation that scheme ( ) A K b u , , contains a cycle
satisfying the condition in Theorem 1.4. Let d be the minimum number of times among all
states in the cycle by which a state can be reduced by
1
2
b+
each time, without falling in the
forbidden regions
1
[2 , 2 2 )
K K b+
+ or
1
[0, 2 )
b+
. Then we know that all schemes





16
1 1 1
( 2 ), ( 2 2 ),..., ( 2 )
b b b
A K b u A K b u A K b u d
+ + +
, , + , , + , , + are also nonprimitive.

The search procedure using the above criteria is quite effective. For instance, it finds the
two primitive schemes (20, 8,181808) A and (20, 8,866768) A , which are the only possible
ones for 20 K = and 8 b = , by doing only 5507 simulations instead of the
20
2 1 = 1048575
simulations (one for each value of u , 1 2 1
K
u ) that would be required under the brute
force approach. Note that each simulation in either case requires
1 21
2 2
K+
= basic steps to
determine the cyclic structure of the candidate scheme (20,8, ) A u .
In Table 1 we present a sample of bit positions and CAVs that ensure a maximum period for
each K. As we can see for all values of K from K =5 up to K = 31 we have schemes that yield
maximum length sequences. (For each register size, we report at most 12 satisfying samples.)

Register Size (Bit position, CAV)
5 (2, 26)
6 (2, 38) (3, 54) (4, 24)
7 (3, 54)
8 (4, 210) (6, 176)
9 (2, 118) (4, 310) (6, 496)
10 (2, 518) (7, 666) (8, 932)
11 (4, 1158) (6, 1130) (9, 1224)
12 (3, 2236) (5, 2588) (6, 3558) (7, 2248) (8, 3614) (9, 3104) (10, 2318)
13 (2, 4198) (3, 4508) (6, 6738) (7, 4284) (8, 7954) (9, 5712) (10, 6834) (11, 7582)
14 (2, 8830) (3, 9926) (5, 15230) (6, 12266) (9, 13896) (11, 11558) (12, 16092)
15 (4, 11260) (6, 27448) (7, 23210) (8, 29856) (11, 13852)
16 (4, 40802) (5, 20124) (6, 10822) (8, 30796) (10, 33194) (11, 36104) (12, 49770)
(13, 51286)
17 (2, 63158) (3, 76012) (4, 88108) (5, 87180) (6, 94278) (7, 58836) (8, 88344)
(9, 95318) (10, 95128) (11, 76620) (12, 74932) (15, 126714)
18 (3, 163254) (5, 26166) (6, 49538) (8, 33312) (9, 44688) (11, 22674) (12, 50678)
(13, 39898) (14, 256484)
19 (2, 267854) (3, 262140) (4, 337062) (6, 367924) (7, 272004) (8, 335756)
(9, 437864) (10, 446656) (11, 364900) (12, 353128) (15, 403832) (16, 299418)
20 (2, 529762) (3, 213338) (4, 400354) (7, 195074) (8, 866768) (9, 283654)
(10, 174322) (12, 118472) (13, 171278) (14, 354756) (16, 254530) (18, 1048534)
21 (2, 1652154) (3, 1628926) (6, 1089634) (7, 1652382) (11, 1441998)
(13, 1023958) (14, 1522736) (15, 1738414) (16, 1276168) (17, 1240604)
(18, 1800070) (19, 1289956)
22 (4, 2097144) (5, 2085914) (6, 736714) (7, 1986620) (9, 1038914) (10, 2094588)
(13, 2367380) (14, 2794960) (15, 2718932) (17, 3102930) (19, 3134336)





17
(20, 4030170)
23 (2, 4610110) (3, 6261634) (6, 6439946) (7, 6455686) (9, 6200834)
(10, 5898892) (12, 5882022) (13, 6476080) (14, 4071030) (15, 4835746)
(20, 3827474)
24 (3, 8985292) (5, 10050842) (6, 12105358) (9, 13283262) (10, 9474304)
(11, 13327194) (12, 6907358)
25 (2, 20739558) (4, 14241020) (6, 20085030) (7, 15244154) (10, 7919528)
26 (2, 33554430) (8, 51181336)
27 (4, 112775046) (6, 100350538) (7, 122824516) (8, 17357136)
28 (2, 133652770) (5, 153470694)
29 (2, 516563642) (4, 254504228) (6, 14501472)
30 (3, 533119780) (4, 294390828)
31 (7, 1197375798) (7, 1338246558) (7, 1430906754)
Table 1: A sample of bit positions and CAVs that ensure maximim period for each K.

We note again that in the case of an ANLFSR or EANLFSR, maximum length sequences do
not exist for several accumulator sizes.
The hardware required so that an accumulator to behave, in test mode, as a NLFSR
(ANLFSR scheme) is equal to 1.7K+6.5 equivalent gates, while for the EALFSR is equal to
1.7K+8.5 [13]. The hardware required for the proposed accumulator scheme is equal to that
required for the EALFSR, that is equal to 1.7K+8.5. The hardware overhead of the MAC [10],
Multiply-Add and Multiply-Accumulate schemes [11] is zero. However, they assume the
existence of a multiplier-accumulator or multiplier-adder pair in the circuit. According to our
scheme only the existence of an accumulator is required. In most LFSR based test-per-scan
BIST, the LFSR is a dedicated circuit. In this case the hardware required for the implementation
is equal to 3.6K+2m where m is the number of the XOR gates. We can see that the hardware
overhead imposed by modifying the accumulator is roughly equal to the half of the cost of the
LFSR. In the case that an existing register is modified to function in test mode as a LFSR then
the cost is equal to 1.7K+2m equivalent gates, which is similar to the cost of our scheme.

4. Evaluation and Comparisons
In order to evaluate the quality of the test sequences generated by our scheme a lot of
experiments were conducted using the ISCAS'89 benchmarks [17]. We assume that the primary
inputs, the internal flip-flops and the primary outputs are connected to a single scan chain. The
fault coverage in every case was calculated as the fraction of the number of faults detected by
the test vectors of the test pattern generator over the total number of faults.





18
For each one of the bit serial test pattern generators that are evaluated, the number of
clock cycles that are used to produce and shift-in a new test vector were chosen to be relatively
prime to the period of the generated sequence, in order to guarantee that a maximum number of
different patterns can be applied to the CUT.
Two sets of experiments were performed: one set using 16-bit and the other one using
24-bit wide accumulators, adders or LFSRs. For each type of pattern generator scheme, 4
different configurations (in terms, accordingly, of primitive polynomial, input constants, CAV,
etc.) were tried. For each such configuration, 5 different seeds were further tried, resulting in 20
experiments for each type of pattern generator and benchmark circuit. The primitive
polynomials for the LFSRs were chosen from [2]. The input constants for the arithmetic bit
serial test pattern generation structures where chosen according to the results reported in [10] for
the MAC structure and the theorems presented in [11] for the multiply-add and multiply-
accumulate schemes.
[11] [13]
CUT LFSR
Mul&Add Mul&Acc
[10]
MAC
ANLFSR EANLFSR
Proposed
s27 22 19 21 25 22 17 14
s208 1466 91.74% 99.08% 3154 96.33% 1745 1591
s298 231 99.83% 374 559 292 174 162
s349
99.41%
155
99.41%
101
99.41%
129
99.41%
201
99.41%
133
99.41%
74
99.41%
101
s382 342 211 385 501 99.87 323 296
s386 2128 88.21% 2517 2832 2126 1811 2263
s420 94.54% 69.76% 81.22% 90.39% 82.10% 93.23% 94.65%
s444
97.52%
191
97.52%
202
97.52%
262
97.52%
287
97.52%
255
97.52%
267
97.52%
353
s510 392 98.33% 523 917 99.41% 558 366
s526
99.91%
10868
88.02% 99.81%
99.91%
22461
99.91%
11182
99.91%
7894
99.91%
6029
s641 99.45% 95.64% 98.51% 98.82% 98.59% 98.82% 99.53%
s713 94.39% 90.74% 93.55% 93.83% 93.62% 93.83% 94.46%
s832
98.98%
15071
78.07% 95.55%
98.98%
17047
90.93%
98.98%
17226
98.98%
15039
s838 65.19% 51.87% 57.14% 61.03% 58.64% 63.53% 65.09%
s953 26195 77.91% 93.18% 99.95% 89.77% 99.95% 24962
s1196 99.79% 83.74% 95.40% 99.71% 55131 99.88% 99.96%
s1238 96.57% 80.41% 92.29% 96.57% 96.77% 96.65% 96.73%
s1423
99.09%
26679
94.73% 98.38% 98.98% 99.05%
99.09%
24285
99.09%
13944
s1494
99.47%
2505
88.82% 99.13%
99.47%
4421
99.47%
3360
99.47%
3588
99.47%
3822
s5378 98.81% 88.21% 97.52% 98.38% 98.76% 98.84% 98.85%
s9234 89.59% 65.02% 85.59% 87.57% 87.29% 89.53% 89.43%
s13207 98.23% 78.39% 92.69% 90.57% 98.54% 98.60% 98.69%

Table 2: Results achieved by the pattern generators with 16-bit wide accumulators, adders or
LFSRs for the ISCAS'89 benchmark circuits





19
The CAVs for the ANLFSR and EANLFSR schemes were selected according to the data of
Table 1 presented in [13], for the case of 16-bit wide accumulator, while they were randomly
selected for the case of 24-bit wide accumulator, because there was no information about the
proper selection of the constant additive in Table 1 of [13].
Each entry in Tables 2 and 3 gives the smallest number of test vectors required to
achieve 100% single stuck-at fault coverage, or the fault coverage obtained after applying 64K
patterns to the corresponding CUT, or the fault coverage obtained along with the required
number of test vectors when more than one schemes achieve the same fault coverage. The best
results obtained for each benchmark circuit are shaded.
Tables 2 and 3 clearly show that the bit-sequences produced by the proposed scheme in
most cases outperform both the LFSR and the other arithmetic module based test pattern
generators.
[11] [13]
CUT LFSR
Mul&Add Mul&Acc
[10]
MAC ANLFSR EANLFSR
Proposed
s27 8 13 13 25 14 16 16
s208 1905 1946 16140 3935 2269 1249 1266
s298 209 212 197 177 273 303 174
s349
99.41%
95
99.41%
101
99.41%
80
99.41%
125
99.41%
174
99.41%
148
99.41%
100
s382 341 267 358 303 247 266 160
s386 2269 1590 2365 3193 2135 1329 1427
s420 96.18% 83.62% 84.17% 94.32% 80.23% 94.32% 97.27%
s444
97.52%
269
97.52%
203
97.52%
217
97.52%
222
97.52%
218
97.52%
261
97.52%
296
s510 402 573 741 768 617 462 482
s526
99.91%
9439
99.14% 99.91%
99.91%
12101
99.91%
12280
99.91%
10906
99.91%
8245
s641
99.77%
47415
98.43% 98.67% 98.74% 98.82% 99.53%
99.77%
63966
s713
94.67%
47415
93.48% 93.69% 93.76% 93.83% 94.46%
94.67%
63966
s832
98.98%
9542
95.97%
98.98%
17961
98.98%
17842
98.98%
16413
98.98%
12851
98.98%
12642
s838 65.78% 57.84% 58.80% 62.79% 63.17% 65.25% 67.32%
s953 22658 96.07% 36859 14599 20503 25757 17828
s1196 42489 97.70% 99.21% 99.96% 43439 20590 37040
s1238
96.77%
24461
94.55% 96.04% 96.73%
96.77%
43439
96.77%
20590
96.77%
36520
s1423
99.09%
20931
98.60%
99.09%
23222
99.05% 98.88%
99.09%
37178
99.09%
12766
s1494
99.47%
3456
99.43%
99.47%
6955
99.47%
4910
99.47%
4195
99.47%
3047
99.47%
4340
s5378
98.86%
62626
96.99% 98.81%
98.86%
63918
98.82%
98.86%
52860
98.86%
50969
s9234 90.21% 81.21% 88.31% 89.34% 89.10% 90.17% 89.60%
s13207 98.76% 88.98% 98.36% 98.60% 98.66% 98.71% 98.78%

Table 3: Results achieved by the pattern generators with 24-bit wide accumulators, adders or
LFSRs for the ISCAS'89 benchmark circuits





20
The increase in the accumulator size has clearly resulted in certain improvements in the
obtained fault coverage and in many cases has lead to a considerable reduction of the required
test length to achieve 100% fault coverage, in comparison to the results obtained with a 16-bit
wide accumulator.
Apart from the achievable fault coverage and the required test sequence length another
feature is very significant. The effort required for finding an efficient test sequence, with respect
to fault coverage and its length. To have an estimation of the required effort we give in Table 4
the maximum, the average and the standard deviation of the fault coverage over the 20 test
sequences generated by each test pattern generator with size K = 16 in our experiments. From
Table 4 we can easily see that the standard deviation of the fault coverage for the test sequences
generated by the proposed scheme, an LFSR or MAC [10] is very small, while for the rest
arithmetic-function based methods [11, 12] is significantly larger. From Table 4 we can also see
that in most cases the average fault coverage obtained by the test sequences generated by our
method is larger than the average fault coverage obtained by other schemes. So we conclude
that the effort required for finding an efficient test sequence generated by our method is small.

[11] [13]
CUT Metrics LFSR
Mul&Add Mul&Acc
[10]
MAC ANLFSR EANLFSR
Proposed
s526
Max
Avg
Dev
99.90%
99.33%
0.49
88.02%
86.74%
1.32
99.81%
99.52%
0.30
99.90%
99.90%
0
99.90%
99.72%
0.59
99.90%
99.71%
0.52
99.91%
99.91%
0
s641
Max
Avg
Dev
99.45%
98.80%
0.40
95.37%
94.33%
0.72
98.51%
98.35%
0.17
98.82%
98.74%
0.11
98.59%
98.42%
0.48
98.82%
98.58%
0.23
99.53%
98.87%
0.34
s713
Max
Avg
Dev
94.39%
93.81%
0.36
90.74%
89.81%
0.65
93.55%
93.41%
0.15
93.83%
93.76%
0.10
93.62%
93.47%
0.43
93.83%
93.61%
0.21
94.46%
93.87%
0.30
s832
Max
Avg
Dev
98.98%
97.88%
1.95
78.066%
76.74%
0.95
95.55%
91.38%
4.40
98.98%
98.98%
0
90.93%
85.02%
3.21
98.98%
98.39%
2.13
98.98%
98.98%
0
s838
Max
Avg
Dev
65.19%
63.53%
1.55
51.87%
47.88%
2.54
57.14%
50.13%
7.34
61.03%
60.13%
1.28
58.63%
56.63%
2.17
63.54%
61.04%
3.08
65.09%
62.34%
1.27
s953
Max
Avg
Dev
100.00%
99.75%
0.32
77.91%
76.73%
1.42
93.18%
86.62%
6.91
99.95%
99.79%
0.22
89.768%
88.75%
1.59
99.95%
98.77%
2.34
100.00%
99.45%
0.58
s1196
Max
Avg
Dev
99.79%
99.71%
0.08
83.74%
79.59%
2.79
95.40%
94.59%
0.86
99.71%
99.60%
0.15
100.00%
99.45%
1.17
99.88%
99.10%
2.04
99.96%
99.87%
0.08
s1238
Max
Avg
Dev
96.57%
96.48%
0.06
80.41%
76.45%
2.50
92.29%
91.50%
0.83
96.57%
96.45%
0.17
96.77%
96.23%
1.20
96.65%
95.93%
1.93
96.73%
96.66%
0.05
s1423
Max
Avg
Dev
99.09%
99.05%
0.04
94.73%
93.65%
0.70
98.38%
98.03%
0.37
98.98%
98.96%
0.02
99.05%
98.82%
0.48
99.09%
98.93%
0.24
99.09%
99.08%
0.03
s1494
Max
Avg
99.47%
99.47%
88.82%
88.18%
99.13%
97.19%
99.47%
99.47%
99.47%
99.42%
99.47%
99.19%
99.47%
99.47%





21
Dev 0 0.48 2.05 0 0.16 0.29 0
s5378
Max
Avg
Dev
98.81%
98.81%
0
88.21%
88.01%
0.18
97.52%
96.18%
1.37
98.38%
98.36%
0.03
98.76%
96.20%
7.59
98.84%
96.30%
7.53
98.85%
98.76%
0.11
s9234
Max
Avg
Dev
89.59%
89.10%
0.50
65.02%
64.04%
0.91
85.59%
79.13%
6.62
87.57%
87.49%
0.11
87.29%
81.90%
8.82
89.53%
85.98%
9.69
89.43%
89.05%
0.19
s13207
Max
Avg
Dev
98.23%
98.17%
0.06
78.39%
76.88%
1.41
92.69%
88.18%
4.61
90.57%
90.18%
0.54
98.54%
95.36%
7.13
98.60%
95.92%
7.03
98.69%
98.50%
0.17

Table 4: Standard deviation of fault coverage.
5. Conclusions
In this paper we have shown that an accumulator based test pattern generator can be used
efficiently for bit serial test pattern generation and in most cases, compares favorably to LFSR
and other arithmetic function based bit serial sequence generators. Furthermore, our scheme has
the advantage of wider applicability against the other arithmetic function based bit serial
sequence generators proposed in [10, 11] since it can be applied even in circuits that an
accumulator-multiplier or adder-multiplier configuration [10, 11] is not available. The proposed
accumulator based bit-serial test pattern generator has also the very significant feature that the
effort required for finding an efficient test sequence, with respect to fault coverage and its
length, is less than or equal to an LFSR.
References
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Testable Design, Computer Science Press, New York, NY, 1990.
[2] P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudo-Random
Techniques, New York: Johh Wiley & Sons, 1987.
[3] M. Bushnell and V. Agrawal, Essentials of Electronic Testing for Digital, Memory &
Mixed Signal VLSI circuits, Kluwer Academic Publishers, 2000.
[4] H. J. Wunderlich, BIST for systems-on-a-chip, Integration, The VLSI Journal, vol. 26,
no.1-2, pp. 55-78, December 1998.
[5] J.Rajski and J.Tyszer, Arithmetic BuiltIn SelfTest for Embedded Systems, Prentice
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