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CE 2704 - Digital Logic Design

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Dr. Ehsan Ali
Assumption University of Thailand
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Semester 2/2024
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 Contents

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1 Module 7 - Assignments Answers 2
1.1 Copyright Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

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1.2 Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

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 Chapter 1

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Module 7 - Assignments Answers

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1.1 Copyright Notice

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This PDf file is generated by Dr. Ehsan Ali and contains the answers to all the assignments of Mod-
ule 7 of CE2704 Digital Logic Design - academic semester 2/2024. The material in this PDF file is
copyrighted. and cannot be shared whatsoever to any third party or online websites, forums, etc.
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 1.2 Assignments
1. When using a sensitivity list with a procedural block, what will cause the block to trigger?
When there is a state change on any of the signals in the list.

2. When a sensitivity list is not used with a procedural block, when will the block trigger?
The block will trigger at the start of the simulation. An initial block will trigger once at the

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beginning, whereas an always block will trigger repeatedly throughout the simulation’s runtime.

3. When are statements executed when using blocking assignments?

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4. When are statements executed when using non-blocking assignments?

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Statements are executed at the end of the block when using non-blocking assignments.

5. What is the difference between a begin/end and fork/join group when each contain multiple state-
ments?

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A begin/end statement group evaluates the multiple statements in the order that they are listed,
whereas a fork/join statement group evaluates the multiple statements in parallel.

6. What type of procedural assignment is used when modeling sequential logic?

7. What signals should be listed in the sensitivity list when modeling combinational logic?
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All input signals should be listed in the sensitivity list when modeling combinational logic.

8. What signals should be listed in the sensitivity list when modeling sequential logic?
Only the rising edge of the clock signal should be listed in the sensitivity list when modeling
sequential logic.
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 9. Design a Verilog model to implement the behavior described by the 4-input truth table in the
following figure. Use procedural assignment and an if-else statement. Declare the module to
match the block diagram provided. Use the type wire for the inputs and the type reg for the
output. Hint: Notice that there are far more input codes producing F = 0 than producing F = 1.
Can you use this to your advantage to make your if-else statement simpler? Include your source
code and simulation waveform.
Answer:

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 10. Design a Verilog model to implement the behavior described by the 4-input truth table in Fig. 1.9.
Use procedural assignment and a case statement. Declare the module to match the block diagram
provided. Use the type wire for the inputs and the type reg for the output. Include your source
code and simulation waveform.
Answer:

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 11. Design a Verilog model to implement the behavior described by the 4-input maxterm list in the
following figure. Use procedural assignment and a case statement. Declare the entity to match the
block diagram provided. Use the type wire for the inputs and type reg for the output. Include
your source code and simulation waveform.
Answer:

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 12. The following figure shows the topology of a 4-bit shift register when implemented structurally
using D-Flip-Flops. Design a Verilog model to describe this functionality using a single proce-
dural block and non-blocking assignments instead of instantiating D-Flip-Flops. The figure also
provides the block diagram for the module port definition. Use the type wire for the inputs and
type reg for the outputs. Include your source code and simulation waveform.
Answer:

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 13. Are system tasks synthesizable? Why or why not?
System tasks are not synthesizable because they are not associated with real circuitry and are thus
ignored by the synthesizer.

14. What is the difference between the tasks $display() and $write()?
$display() prints with an appended newline, but $write() does not.

15. What is the difference between the tasks $display() and $monitor()?

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$monitor() prints whenever the value of an argument changes, whereas $display() prints the value
of the argument in all cases.

16. What is the data type returned by the task $fopen()?

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A unique integer file descriptor is returned by $fopen().

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 17. Design a Verilog test bench to verify the functional operation of the system in Fig. 1.9. Your test
bench should drive in each input code for the vector ABCD in the order they appear in the truth
table (i.e., "0000", "0001", "0010", ...). Have your test bench change the input pattern every 10
ns using delay within your procedural block. Include your source code, simulation waveform, and
simulation console output.
Answer:

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 18. Design a Verilog test bench to verify the functional operation of the system in the following figure
with automatic checking. Your test bench should drive in each input code for the vector ABCD
in the order they appear in the truth table (i.e., "0000", "0001", "0010", ...). Have your test bench
change the input pattern every 10 ns using delay within your procedural block. Use the report
and assert statements to output a message on the status of each test to the simulation transcript
window. For each input vector, create a message that indicates the current input vector being
tested, the resulting output of your DUT, and whether the DUT output is correct. Include your
source code, simulation waveform, and simulation console output.

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Answer:

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 The answer continues on next page:

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 19. Design a Verilog test bench to verify the functional operation of the system in the following figure
with automatic checking. Your test bench should drive in each input code for the vector ABCD
in the order they appear in the truth table (i.e., "0000", "0001", "0010", ...). Have your test bench
change the input pattern every 10 ns using delay within your procedural block. Print the results
to an external file named "output_vectors.txt" using $fdisplay(). Include your source code,
simulation waveform, and simulation console output and the external file content. Include your
source code, simulation waveform, and simulation console output.

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Answer:

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 20. Design a Verilog test bench to verify the functional operation of the system in Fig. 1.10 with
automatic checking. Your test bench should drive in each input code for the vector ABCD in the
order they appear in the truth table . Have your test bench change the input pattern every 10 ns
using delay within your procedural block. Create an input text file called "input_vectors.txt" that
contains each input code for the vector ABCD (i.e., "0000", "0001", "0010", ...), each on a separate
line in the file as shown in the following figure. Use $readmemb() to read the data from external
file and verify the design using the read data. Include your source code, simulation waveform, and
simulation console output.

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The answer is on next page:

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