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Reduced Instruction Set Computer (RISC) 32bit Processor on Field Programmable Gate Arrays (FPGAs) Implementation
Thanigaivel.V*, V. Subramanian**, K. Priyadharsan***
Abstract: This paper concerned with the Reduced Instruction Set Computer (RISC) processor on a Field Programmable Gate Arrays (FPGAs). The processor has been designed with VHDL, synthesized using Xilinx ISE 9.1i Web pack, with ModelSim simulator, and then implement on Xilinx Spartan 2E FPGA that has 143 presented Input/ Output pins and 50MHz clock oscillator. The test bench waveforms for the different parts of the processor are obtainable and the system architecture is established.
Key words- Processor, HDL,FPGA, RISC, CPU.
INTRODUCTION The Computer Engineering is very much concerned with the cost and performance of components domain. in the implementation Reduced development board, DIO1, and DIO2 extension boards from Digilent have been used for the hardware implementation. The Web pack from Xilinx and ModelSim has been used for synthesis and simulation.
Instruction Set Computer (RISC) focuses on reducing the number and complexity of instructions in the machine.1,
2
Field
System Construction The RISC processor presented in this paper consists of three components as shown in Figure .1, these Components are the Control Unit (CU), the Data Path, and the ROM. The Central Processing Unit (CPU) has 17 instructions. In the following sections we will describe the design of the three main components of the processor. http://www.srji.co.cc
Programmable Gate Arrays (FPGAs) are growing fast with cost reduction compared to ASIC design. In this paper a low cost 32bit RISC Processor has been designed and synthesized, the design has been described using VHDL,
4, 5, 6, 7 3
and
some
components have been implemented and tested on Xilinx FPGA. Spartan 2E
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ROM then decoding the parts of the order. The decoding state will also select the next state depending on the order; the control unit will jump to the correct state based on the order given. After all states of a running order are finished, the last one will return to the fetch state which will allow us to process the next order in the program.
Figure .1 System constructions
Figure .2 shows the state diagram for the control unit.
Plan of the ROM The central processing unit has a built in ROM which enables us to program simple code and execute it. It is a basic 16x32 ROM and it is 32bit allied. The List of signals in the ROM list. Address: address sent by the control unit
Data out : data that is contained the given address Read Ready CLK Reset : signal to enable reading from the ROM : signal to indicate when the ROM is Ready for reading : clock signal : Initial reset signal
Figure 2: control unit Design
Design of the Data Path The Data Path consists of subunits that are necessary for performing all of arithmetic and logic operations. A Data path is a hardware that performs data processing operations.8, 9, 10, and 11 It is one of two types of modules used to represent a digital system, the other being a control unit. The Data path model we designed consists of the units necessary to perform all the operations on the data selected by the control unit. The components include a Register File, Arithmetic/Logic Unit, Memory Interface and Branching Unit as shown in Figure 3.The Register File holds http://www.srji.co.cc
Plan of the Control Unit The control unit plan is based on allows each state to run at one clock cycle, the first state is the reset which is initializes the central processing unit internal registers and variables. The machine goes to the reset state by enabling the reset signal for a certain number of clocks. Following the reset state would be the instruction fetching and decoding states which will enable the suitable signals for reading order data from the
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the table of the 32 general purpose registers available to the CPU, it has two output ports (output1, outpu2) and one input port, also it has a 16 bit bus connected directly to the Control Unit to pass immediate data. The ALU design consists of two input ports and one output port which mainly performs operations on two operands. It has a design similar to the control unit which selects an operation based on a code given by the ALUCL. The Memory Interface was designed to RESULTS There are 5 main signals that are viewed in throughout the simulation. The sim_clock signal is the clock generated for the simulation and runs at 50Mhz, instruction fetch signal shows when the control unit requests data from the ROM, the instruction address 32bit bus is the address of the instruction being fetched, the instruction data 32bit bus is the data sent out from the ROM, and the reset state is enabled for 3.5 cycle to give enough time for all units to reset and initialize, after that we can see the first instruction beginning at address 0 is executed followed by all the proceeding instructions until the instruction at address 40 Which is the shift half word SHW. CONCLUSION 32bit RISC Process has been design and implemented in hardware on Xilinx Spartan 2E FPGA. The design has http://www.srji.co.cc accommodate simple load/store operations with the 16x32 memory. The effective address is calculated by adding the content of the address register and the immediate data. The Branch Unit calculates a given condition by the control unit and raises a branch flag whether the condition is met or not, and if the flag is raised, it sends the branch address back to the control unit in order to replace the program counter. The control lines coming from the control unit operate all the units in the data path. The path starts from the register file that has two output ports which are connected to all the other units, after that the processing is done by one of the other units then finally returned back to the register files input port using the multiplexer. The signals used in the data path are forwarded from the control unit to each subcomponent as needed.
Figure 3: Data Path
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been achieved using VHDL and simulated with ModelSim. Digilent Spartan 2E progress board has been used for the hardware part. Most of the goals were achieve and simulation shows that the processor is working perfectly, but the Spartan 2E FPGA was not sufficient for implementing the whole design into a real hardware, since the total accessible logic
gate in Spartan 2E is 200K Logic Gate, which was not enough for implementing the whole processor, but parts of the processor have been implemented and test in a real hardware. Future work will be added by increasing the number of instructions and make a pipelined plan with fewer clocks cycles per instruction.
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CORRESPONDENCE
*Centre for Research and Development, PRIST University, Vallam, Thanjavur613403, Tamilnadu, India. EMail: [email protected]. **Centre for Research and Development, PRIST University, Vallam, Thanjavur613403, Tamilnadu, India. E-Mail: [email protected]. ***Centre for Research and Development, PRIST University, Vallam, Thanjavur613403, Tamilnadu, India. E-Mail: [email protected]
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