NXP IC Technical Questions and Answers - 2006 Table of Contents P82B96 for long distance communication......................................................................................

1 What effect will lowering the resistor connected to Dref and Gref have on the GTL2002?.......... 2 I2C with a fiber optic modem ......................................................................................................... 2 Applying Reset Signal Continuously with Vcc .............................................................................. 3 MOSFET has its body diode between Source and Drain ............................................................... 3 I2C Multi-Master Topology............................................................................................................ 3 Changing Vcc supply to the P82B96 .............................................................................................. 3 Outputs are pulled up to 3.3V even prior to the GTL2005 being powered .................................... 4 Can PCA9543 clock stretch ............................................................................................................ 4 Channel behavior of PCA9543A without active or passive pull-up............................................... 4 Pull-up resistors on PCA9500......................................................................................................... 4 Dynamic address change of PCA9500 ........................................................................................... 4 Differential device to use with PCA82C250/1 ............................................................................... 5 Bench test methodology of SE98.................................................................................................... 5 Noise filter on PTC pin of the PCF8582......................................................................................... 5 Bias current on address pins of the NE1617A ................................................................................ 6 Alternate address EEPROM ........................................................................................................... 6 Signal on input of GTL2005 with power down .............................................................................. 6 GPIO on The MicroTCA backplane ............................................................................................... 6 What does remote I/O expander mean............................................................................................ 7 Application for NE1619.................................................................................................................. 7 Software for Mac OS for PCA9633D16......................................................................................... 7 Uneven power on PCA9517 Vcca/Vccb......................................................................................... 7 No specification for VOH and IOH on GTL2005 .......................................................................... 8 Can GTL2002 effectively replace the MAX13013 ........................................................................ 8 Fm+ coexistence with Fm and Sm devices..................................................................................... 8

P82B96 for long distance communication

Question We need to use the P82B96 to send I2C signals over a long link. Due to the special logic levels of the P82B96 on its Sx and Sy pins, and subsequent diminished noise margin, we'll need to maximize the pull-up resistors connected to that part of bus. But the larger pull-up resistors limit the total allowable bus capacitance. I'd like to put a PCA9511 between the P82B96's Sx and Sy pins and the rest of the bus, to isolate the rest of the bus from the special logic levels of the P82B96. Do you see any problems in doing this? Adding a PCA9511 will add delay; do you have a spec on how much insertion delay this part exhibits? Answer - The bad news is that you can't connect PCA9511 to the Sx side of P82B96 because the PCA9511 (and other related parts) require their input pin held below 0.5V to guarantee transmission of a logic low. You already recognize that P82B96 can't do that; it only guarantees 0.79V at 25C and 200uA. Maybe these alternatives might help...

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NXP IC Technical Questions and Answers - 2006

1) When using P82B96 in an opto-isolation application it is only necessary to have one P82B96 to split and re-combine the I2C signal without latching. That means that on one side you need to use P82B96. On that side you must try to make the compromise about Vol levels because that compromise is the key to splitting the I2C signal. But on the other side you can simply split/recombine the I2C signal using conventional logic ICs and that means you get perfectly standard logic switching levels on that side. So if you can achieve the compromise on ONE side then the other side needs no compromise. Here is an example. In this case differential signals are used to carry the I2C information but it's exactly the same if you use fibers. Note that P82B96 is at one end and LVC logic at the other. We have on our future development list a dedicated IC to pair with P82B96 but until then you can use standard Picogates.

2) You can use the PCA9517 which uses the special logic levels of our PCA9515 buffer (similar to the Sx side of P82B96) on one side and perfectly normal logic levels on the other side. Of course you can connect the standard logic level side of PCA9517 to the Sx side of P82B96 and then the logic levels you interface with are those of PCA9515. It gives you Vol = 0.6V max - even when sinking 6mA - so you can have a low pull-up and allow lots of capacitance. Your connected chips must guarantee Vol = 0.4V but that is required of all I2C parts. So now you have perfectly standard logic on one side of you link and Vol < 0.6V on the other.

What effect will lowering the resistor connected to Dref and Gref have on the GTL2002?
Answer - The 200k ohm pull-up allows a small leakage current through the clamp transistor and set the gate potential to SREF + VT which essentially clamped the S1,2 side to SREF. The pull-up value is kept large so as to keep the leakage current small. When the pull-up is strong, the voltage clamp still works but you will see a larger leakage current. The resistor value will dictate how much leakage current will be and is calculated as follows.

I2C with a fiber optic modem

Question - My application is to interface I2C with a fiber optic modem, which has a TTL input/output. What is your recommendation for accomplishing this? I will be using the P82B96 Dual bi-directional bus buffer and I am not sure how to best handle the Tx/Rx (Ty/Ry) interface to TTL. Answer - In practice, no interface is really needed because the TTL levels actually will conform to the I2C requirements, it's just that in the strictest interpretation they may not. The one that can fail is the one that says the output 'high' is only guaranteed to be 2.1V and theoretically that fails I2C when the bus voltage is > 3V. If P82B96 was used to convert TTL to I2C then the best way is to connect the TTL to the Sx side and use the joined Tx/Rx side as a perfectly conforming I2C side. While some will say the 0.8V (max) low required by TTL is marginal at Sx, in practice there is no problem because TTL switches at 1.4V and Sx can be arranged to output 0.79V (max) by using a 200uA pull-up resistor for those who are extra strict. So, if any interface is really needed, the arrangement would be Sx connects to the TTL signals and you use a weak pull-up on Sx to whatever the TTL supply is.

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NXP IC Technical Questions and Answers - 2006 Applying Reset Signal Continuously with Vcc
Question - What happens to both devices when they have been being inputted re-set signal continuously with Vcc? Does something unexpected phenomenon happen or is this condition banned? Answer - SMBus/I2C state machine is held in their default state, so the condition is HiZ and PCA9551/PCA9539 don't make ACK against call of their slave address.

MOSFET has its body diode between Source and Drain

Question - Normally, MOSFET has its body diode between Source and Drain. According to data sheet, FETs consisting push-pull output is MOSFETs. Therefore, even if there is no ESD diode between I/O and Vdd, it seems there is current pass due to body diode of MOSFET. So I can assume that current limiter is needed when Vi is above Vdd. Answer - There is actually no ESD on any of the I/O Expander from Philips. By the way, in order to answer "you don't need current limiter on I/O when Vi is above Vdd. However, page 5 of PCA9534 data sheet indicates ESD protection diode between I/Os and Vdd, it means there is current pass from I/O to Vdd.

I2C Multi-Master Topology

Question - Regarding the I2C Multi-Master Topology. In our system we have two aggregate cards (main cards) and a few peripheral cards. Do the two masters need to have any handshake channel between them in order to prevent collisions on the I2C bus? Answer - When you have two masters and all masters having the same voltage level, the master does synchronization and arbitration automatically by the built-in protocol and there is no need for external circuit to manage it. On the SCL line, both masters continue to goes through clock synchronization - the device that has the longest low dictates the low of the master clock and the one that has the shortest high dictates the high of the clock. On the SDA line, the bus arbitration can go on for an unlimited number of bits. For more detail on clock synchronization and bus arbitration, please refer to the attached I2C specification (see page 11 and 12 for regarding how master does clock synchronization and bus arbitration).

Changing Vcc supply to the P82B96

Question How does the system performance change with the change in supply voltage of P82B96. Answer - The quick answer to the question is that changing Vcc supply to the P82B96 is not likely to cause any big changes in system performance. So when you operate a 15V bus with Vcc=5V the only parameter that is affected by Vcc is the switching threshold for the bus signals on the 15V bus. The effects on the system performance (compared to using Vcc=15V) that can change the system performance will be these.

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NXP IC Technical Questions and Answers - 2006

a) There will be a shorter propagation delay for rising edges on the 15V bus because the bus will be sensed as 'high' at Rx as soon as it rises to 2.5V. b) If there are differences in the ground potential (which is likely with 200m cables) then the system is less tolerant to noise on the 15V bus when the P82B96 supply is 5V. If you are using a much lower speed, so delays are not the limitation, and you believe the limitations are due to problems with ground differences or noise then please give some more details about the cable characteristics (resistance, characteristic impedance) and the values and physical arrangement of bus pull-ups (one each end ?

Outputs are pulled up to 3.3V even prior to the GTL2005 being powered
Question - The +3V pin of the device is connected to a 3.3V supply, but the TTL outputs have pull-ups to a different 3.3V rail (this is because the device that receives these outputs must have its inputs pulled up to a separate 3.3V rail). So, it is possible that the TTL outputs are pulled up to 3.3V even prior to the GTL2005 being powered. Is this acceptable for the device? Answer - The 3.3 V side of the GTL2005 LVTTL output is essentially an ALVT output cell, which is the output is specifically designed to be over voltage tolerant when un powered. There is however some dynamic current as the output configures to the over voltage condition.

Can PCA9543 clock stretch

Question - During the switch over, is there any logic within the pca9543a that does a clock stretch? Answer - No, there is no SCL output on the PCA9543A so the device can't clock stretch. A device that does drive the SCL output can clock stretch through the PCA9543A active channel.

Channel behavior of PCA9543A without active or passive pull-up

Question - If channel a does not have pull ups on it when there is no active device what will the behavior be like? Answer - Channel A will be pulled up to 1V below Vcc of the PCA9543A (not upstream channel pull up voltage) through the FETs.

Pull-up resistors on PCA9500

Question - I went through the PCA9500 datasheet and didn't see the value of the internal pull-up resistors actually quantified. The datasheet does mention "strong" in defining the resistance. Do you have the actual data of all of the internal pull-ups on this part? Answer - The GPIO of the PCA9500 uses dynamic current source to pull-up on acknowledge clock and a small current source to hold the line high. So, it does not make sense to translate it to a resistor value, but you can simply look at it as a weak pull-up when used as an input, and as a fast rise time from low to high as an output.

Dynamic address change of PCA9500

Question - our customer will use the pca9555 and want to use the part in a "dynamic mode".

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NXP IC Technical Questions and Answers - 2006

He selects the address of the part with the 3 address pins, writes the data to the part and afterwards (after the first "communication" with the part) he wants to change the address of the part by changing the setup of the address pins (I think he uses some digital I/O for switching the resistor setup of the address pins). Answer - "Dynamic addressing is possible using some of the I/O of the PCA9555 to the address pin inputs. Make sure they do a stop/restart after the address pin state is changed and then use the new address of the PCA9555"

Differential device to use with PCA82C250/1

Question Could you please help Alex on the differential device part number that can be used with the P82B96? Answer - When I search my mail history for 'differential' I find around 100 discussions of this subject using many different ICs from many different manufacturers. The answer is that because P82B96 can split the bi-directional I2C bus into two uni-directional data streams it's possible to transmit those simple logic signals over just about any logic transmission media that the customer selects. Unfortunately most of those differential driver devices are not sold by Philips so the only differential signaling system that we promoted, using Philips drivers, has been the use of CAN transceivers such as PCA82C250 or PCA82C251. It is also possible to use more modern Philips' CAN transceivers provided you keep in mind that they have power-down features that can be activated by inactivity on their signal I/Os.

Bench test methodology of SE98

Question What is the bench test methodology of SE98? I am looking for a bench setup with a general guideline of testing the SE98 over temperature and voltages. For example, how do we characterize the temperature sensors over temperature and over voltages, what is the soak time per temperature and what is the step (1C, 10C, and etc). Answer - If you are only interested in the temp error evaluation at bench then it is simple: Test equipment: - Calibrated thermal bath and thermometer for setting the device temp environment with an accuracy level of 0.05C. Test method: - Design Evaluation: _The temp error is scanned from -40C to 120C, with 1C per step, 1 minutes soak time and only at the typical Vdd of 3.3 V _Sample size: 3 devices - Device Characterization: _The temp error is measured at a few specific temp points and Vdd levels: Temp = 0C, 25C. _The temp characteristics charts are built from those measured points.

Noise filter on PTC pin of the PCF8582

Question - A resistor and capacitor are connected to the PTC pin of the PCF8582 (see page3 appnote AN453): What is the reason to connect those components to this pin? Answer - The 2nF capacitance together with the pull-up resistor formed low pass filter. So, if the system has high frequency noise, then the low pass helps to filter the noise preventing PTC from inadvertently trip.

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NXP IC Technical Questions and Answers - 2006 Bias current on address pins of the NE1617A
Question - Why does the address pins of the NE1617A have a bias current? What is the max current value on ADD pin? Answer - Actually the address "dynamic" bias current has been improved as shown with the charts below. Note that because they are the dynamic bias currents only provided by the device for sensing the address levels at the address pins in a short time (about 20uS) at power-up or starting point of each conversion, they cannot be seen with a regular DVM but can be monitored using a scope. The directions as well as the current values are varied depending upon the connection at the device address pins as described below:

Alternate address EEPROM

Question - I need an EEPROM but with another I2C address range. Do you know another one? Answer - Yes, the only alternate address EEPROM we have is the PCF85103. If you use one of the mux/switches you can isolate the same addressed EEPROMs you need from each other and simply put one on the bus at a time. The all default with all channels open on start up except the PCA9547 which has channel 0 connected for immediate communication with the slaves on that channel.

Signal on input of GTL2005 with power down

Question - Can the input of the GTL2005 device be driven to a positive potential while the VCC is disabled? Answer Yes, the LVTTL side is based on ALVT cells so it is over voltage tolerant, and the GTL I/O is open drain with a comparator input and all ESD is to ground only.

GPIO on The MicroTCA backplane

Question - The MicroTCA backplane, a derivation of the ATCA standard, supports a number of open collector outputs which go out on the bus to other boards. All these boards run at a nominal 3.3V, though differences in voltage can lead to issues with pseudo open collector output supported by some GPIO devices. Either process or ESD diodes can lead to problems if the output is pulled up to a slightly higher voltage on another board. This isnt quite as problematic as trying to drive a 12V output, but it would be nice if the OC mode of operation could operate at around 5V without issues. How much past 5V can they go (to account for different ground references? Answer - Our GPIO are 5.5 V max tolerant, so operating the VCC at 3.3 V and pull-up 5.5 V is o.k. Practically, ATCA uses GPIO for output control or sensing input status, so difference in VCC and output pull-up is o.k. When the I/Os are used to drive LED, then the difference in VCC and pull-up VCC would result the LED being not completely turned off when the output driver is off. Thus, if you use the output to turn on or off the LED, you should pull-up the LED supply to the same level as the GPIO's VCC. Make sure the ground potential difference is important, what I can say is keep the I/O level + any ground offset seen at the chip no more than 5.5 V. On the same note, regardless of VCC or I/O voltage

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differences, you should widen the long trace to minimize the inductance to minimize any transient voltage preventing the output driver from being damaged.

What does remote I/O expander mean

Question - What exactly does remote mean? Answer - Remote I/O expander means the I/O expander is an external chip. It is like any I/O expanders in terms of its application and function except that its I/O circuit is quasibidirectional. Follow up question - If a set of instructions / data transmitted from MCU, can the PCF8575 process on its own, independently? Follow up answer - The PCF8575 is quasi-bidirectional GPIO meaning the I/Os has weak upper transistor which behave as logic 1 or over-powered by input logic 0, and strong lower transistor to drive a logic 0; the upper transistor also has stronger transistor which only turns on for 1/2 clock cycle during the ninth clock and off the entire time to ensure fast turn on for output that drives a logic 1. Thus the I/Os behave as input or output by simply programming it as output driving a logic 1 or output driving logic 0. You can send an I2C command to read the input ports to see which input(s) has been triggered, or send a command to configure the output drive logic 0 or logic 1. All 16 I/O are entirely independent and can be used either as input or output ports.

Application for NE1619

Question - We want to use in our project the I2C Volt Monitor of Philips type: NE1619. Answer - If you need to configure this pin to VID4, you must write to the configuration register. For Pentium/Pro processor, this information is used for indicating the operating voltage capability of the processor (part of Heceta specification) that other devices to query the processor's operating voltage via the NE1619 instead of using separate hardware pins connecting to the processor. One other application for the VID pins is general purpose inputs to monitor a high or low at the input that can be read via VID register.

Software for Mac OS for PCA9633D16

Question We need to develop software for Mac OS X system that manages your PCA9633D16 device. Have you a module board that can be connected directly to a USB port and send data to I2C devices, dynamically from user program running on the computer? Have you some idea how I can do this task? Answer The Win-I2CUSB dongle can be used. The product can be ordered from the http://www.demoboard.com/win-i2cUSBDLL.htm

Uneven power on PCA9517 Vcca/Vccb

Question - PCA9517 has two power supply pin; Vcca/Vccb. In case Vcca is powered but Vccb isn't powered, is this condition still safe? Answer - If Vccb is not powered, it is safe meaning the device does not get into a strange stage. This means if you don't want A-side to connect to B-side, the you would want to pull the EN pin LOW.

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If Vccb floats to ground, A-side and B-side will NOT connect regardless of the condition of EN pin.

No specification for VOH and IOH on GTL2005

Question - I am having some problems using the GTL2005 and the data sheet seems to be missing some info. I don't see any value for Ioh or Voh for port A the GTL port. Answer - The reason why VOH and IOH are not specified is there is no high side driver for GTL.

Can GTL2002 effectively replace the MAX13013

Question - Can GTL2002 effectively replace the MAX13013 for 48MHz operation for totem pole I/O? The Maxim device appeared to have built-in high side low side driver and 1-shot circuitry - it looked like an interesting translation device. Answer - Yes it has a one-shot. And it buffers the two sides so that although the driver must be strong to over drive the weak hold circuit it only sees one side of the part. The GTL2002 does not isolate the capacitance, and if the data path is low voltage side to high voltage side a pull-up resistor is required on the high voltage side. The total capacitance and the effective pull-up determine the maximum frequency. If the data path is from high voltage side to low voltage side and the high voltage side is driven by a totem pole output and the distances/ capacitance is small it will probably work. However if the path is low voltage side to high voltage side and the pull-up resistor is a high value and the capacitance (sum of both sides) is not low it will probably not work.

Fm+ coexistence with Fm and Sm devices

Question What happens when an Fm+ part needs to talk to another Fm+ part but there are other Standard Mode parts hanging on the same IIC bus? What happens when an Fm+ part needs to talk to another Fm+ part but there are other Standard Mode parts hanging on the same IIC bus? Does the presence of Standard Mode devices preclude 1Mbps transfers between FM+ devices? How do the Standard Mode parts ignore an Fm+ transaction? state machine is robust enough that as long as you don't send that devices address after start condition it would not cause problems if the bus was operating above its maximum rated bus speed) to higher bus speeds so like in this example Jeff could point to the "tolerance" rating of the SM device in the data sheet and say "it is tolerant to FM+" so it would be OK to put all the devices on the same bus allowing the master to use FM+ frequency when communicating with FM+ devices without the designer having to isolate the SM device with bus switch or buffer?

Answer - For voltage range it is clear that if you had three parts, A and B with Vcc range 2.3 to 5.5 and C with 3.0 to 3.6 that on the same Vcc rail you could have all three at 3.0 to 3.6V but not C if Vcc was 2.5V or 5V. It is a little less analogize but if C was 5V tolerant since then you could have A and B at 5V interfacing to C but C would still have to have Vcc at 3.3V

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So for I2C devices, if FM+ could operate at SM, FM and FM+ and SM could operate at SM, if you have both FM+ and SM devices on the same bus the maximum bus speed is SM. If the SM device was FM+ tolerant (it could be on the bus at the higher bus speeds and not cause problems but it could not operate at that bus speed (e.g., like Vcc 3.0 to 3.6V but 5V tolerant I/O)) then you could have both SM and FM+ devices on the same bus, operating at SM when communicating with the SM device and FM+ when communicating with the FM+ device. We don't currently rate our devices tolerant to frequencies higher than in the AC table although we know some operate too much higher frequencies and might be tolerant to even higher speeds. Our FM+ parts are backward compatible, but you can only run an IIC system at the speed of the slowest part. So they can be used in 100 KHz and 400 KHz systems. The real caution is that in a system containing a mix of SM, FM, and FM+ parts can only be operated at the speed of the slowest part, so if maximum speed is wanted it is necessary to segregate different speed grade functions onto different IIC busses. We discussed Fm+ tolerance with the designers and it turns out to be a bad idea. Bottom line is that the maximum bus speed can't be any higher than the slowest device on the active bus. If you have mixed devices then you need to be able to isolate the slower ones if you want to run the higher speed devices faster. We'll look into doing Fm+ switches with integrated pull up resistors to allow Fm+ master and Fm+ slaves to go to 1MHz using lower value pull ups when switch isolates SM or FM devices but then allow communication with SM/FM devices at their maximum speed. Specific to your last paragraph below, do we offer an isolation device such that there is an SM IIC interface on one side and an FM+ interface on the other? For voltage range it is clear that if you had three parts, A and B with Vcc range 2.3 to 5.5 and C with 3.0 to 3.6 that on the same Vcc rail you could have all three at 3.0 to 3.6V but not C if Vcc was 2.5V or 5V. It is a little less analogies but if C was 5V tolerant since then you could have A and B at 5V interfacing to C but C would still have to have Vcc at 3.3V So for I2C devices, if FM+ could operate at SM, FM and FM+ and SM could operate at SM, if you have both FM+ and SM devices on the same bus the maximum bus speed is SM. If the SM device was FM+ tolerant (it could be on the bus at the higher bus speeds and not cause problems but it could not operate at that bus speed (e.g., like Vcc 3.0 to 3.6V but 5V tolerant I/O)) then you could have both SM and FM+ devices on the same bus, operating at SM when communicating with the SM device and FM+ when communicating with the FM+ device.

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