Cst 307

MICROPROCEssORs AND
MICROCONtROLLERs
Introduction
 A microprocessor is a multipurpose, programmable,
clock-driven, register-based electronic device.

 Read binary instructions from memory

 Accept binary data as input

 Process data according to instructions

 Provides output
 Programmable: It can be instructed to perform given
task
 Multipurpose: It can perform various sophisticated
computing functions
 Clock driven: It is operating by a clock or timing
mechanism
 Registers: Type of memory that quickly accept, store
and transfer data & instructions
Microprocessor based System
 ALU- various computing functions
 Arithmetic operations- addition, subtraction
 Logic operations- AND, OR, exclusive OR

 Register array
 Consists of various registers identified by letters B, C, D,
E, H & L
 Store data temporarily during the execution of program

 Control unit
 Provides necessary timing and control signals to all
operations
 Controls the flow of data between MP, memory &
peripherals
 Memory- 2 sections
 ROM- Programs do not need alternation, non-volatile, retaining
its contents even when the power is off
 R/W Memory- known as RAM- user memory, volatile, contents
are lost when the power is turned off
 System bus
 Common communication path
 Group of wires to carry bits. Divided into 3
 Control bus
 Data bus
 Address bus
 Control bus: bidirectional bus
Transfer control and timing signals between MP and peripherals
 Data bus: Transmit data from MP to peripherals or vice versa
 Address bus: Unidirectional bus
Send address of peripheral from MP to device
Evolution of Microprocessor

 4 – Bit Microprocessors
 8 – Bit Microprocessors
 16 – Bit Microprocessors
 32 – Bit Microprocessors
 64 – Bit Microprocessors

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4 – Bit Processors

 INTEL 4040
 INTEL 4004
 In 1974
 In 1971
 1St μp by Intel

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8 – Bit Processors

 INTEL 8008
 In 1972
 INTEL 8085
 1st 8-bit μp
 In 1976
 Execute 50,000 instructions per
second  8-bit data bus and 16-bit address
bus
 INTEL 8080
 Execute 7,69,230 instructions per
 In 1974
seconds
 Execute 5,00,000 instructions
 It could access 64 KB of memory
per seconds

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16 – Bit Processors

 INTEL 8086  INTEL 8088

 In 1978  In 1979
 1st 16-bit μp  Cheaper version of 8086
 16-bit data bus and 20-bit address bus  16-bit processor with 8-bit external data bus
 Execute 2.5M instructions per second  Execute 2.5M instructions per seconds
 Could access 1MB of memory
 Had Multiply and Divide instructions

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32 – Bit Processors

 INTEL 80386
 INTEL 80486
 In 1986
 In 1989
 1st 32-bit μp
 8 KB of cache memory introduced
 32-bit data bus and 32-bit address bus
 Execute 2.5M instructions per second
 Could access 4GB of memory
 Different versions:
 80386 DX, 80386 SX, 80386 SL

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32 – Bit Processors

 INTEL PENTIUM
 INTEL PENTIUM PRO
 In1993
 In 1995
 Originally named 80586
 32-bit data bus and 32-bit address bus
 It could address 4GB of memory

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32 – Bit Processors

 INTEL PENTIUM II – 1997

 INTEL PENTIUM II XEON -1998
 INTEL PENTIUM III – 1999
 INTEL PENTIUM IV – 2000
 INTEL DUAL CORE – 2006

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64 – Bit Processors

 INTEL CORE 2
 INTEL CORE i7
 INTEL CORE i5
 INTEL CORE i3
 INTEL CORE i9

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8085 MICROPROCESSORS
8085 MICROPROCESSORS

 8-bit general purpose μp

 16 – bit address. Capable of addressing 64 k of memory
 Has 40 pins
 Requires +5 V power supply
 Can operate with 3 MHz clock
8086 MICROPROCESSORS

• 16 bit Microprocessor
• Launched in 1978
• Powerful instruction set, and did high speed calculations.
• 8086 has powerful set of registers known as general purpose
and special purpose registers.
• All of them are 16 bit registers.
• 16-bit Arithmetic Logic Unit
• 16-bit data bus
• 20-bit address bus
Register organisation of 8086
Flag register
Physical Address Formation
Pin Configuration of 8086
 AD15-AD0: These are the multiplexed memory I/O
address and data lines.
 Address remains on the lines during T1 state, while the
data is available on the data bus during T2, T3, Tw and
T4.
 Here T1, T2, T3 & T4 are the clock states of a machine
cycle.
 Tw is the wait state.
• A19/S6,A18/S5,A17/S4,A16/S3: These are the time multiplexed
address and status lines.

• During T1, these are the most significant address lines for
memory operations.
• During memory or I/O operations, status information is available
on those lines for T2,T3,Tw and T4.

• S5 denotes the status of interrupt enable flag bit and is updated

at the beginning of each clock cycle.

• The status line S6 is always low.

 The S4 and S3 together indicate which segment register is presently being
used for memory accesses.

 BHE/S7: The bus high enable is used to indicate the transfer of data
over the higher order ( D15-D8 ) data bus.
 It goes low for the data transfer over D15-D8 and is used to derive
chip selects of odd address memory bank or peripherals.
 S7 is not currently used
 RD : Read signal used for read operation.
 This signal, when low indicates the peripheral that the
processor is performing memory or I/O read operation.
 RD is active low during T2, T3, Tw of any read cycle.

• READY : This is the acknowledgement from the slow device or

memory that they have completed the data transfer.
• When high, it indicates that the device is ready to transfer
data.
• When low, then microprocessor is in wait state.

• CLK- Clock Input : Clock input provides the basic timing for
processor operation and bus control activity.
• INTR-Interrupt Request : This is a level triggered input.
• If any interrupt request is pending, the processor enters the
interrupt acknowledge cycle.
• Internally masked by resetting the interrupt enable flag.

• TEST: This input is examined by a ‘WAIT’ instruction.

• If the TEST pin goes low, execution will continue, else the
processor remains in an idle state.

• RESET: It is a system reset pin.

• This input causes the processor to terminate the current activity
and start executing from FFFF0 H

• NMI-Non-maskable Interrupt : Edge triggered input. Not

maskable internally by the software
• MN/MX : Processor operates in either minimum or
maximum mode.

• 8086 works in two modes:

• Minimum Mode
• Maximum Mode
• If MN/MX is high, it works in minimum (single processor)
mode .
• If MN/MX is low, it works in maximum (multiprocessor)
mode
Pin Description for Minimum Mode
• M / IO

• Low indicates that CPU is having an I/O operation.

• High indicates that CPU is having a memory operation.
• Becomes active in the previous T4 and remains active
till final T4 of the current cycle.
• INTA

• This is an Interrupt Acknowledge signal.

• When it goes low, it means processor has accepted the
interrupt
• When microprocessor accepts INTR signal, it
acknowledges the interrupt by generating this signal.
• It is active low during T2, T3 and Tw of each interrupt
acknowledge cycle.
• ALE

 This is an Address Latch Enable signal.

 Indicate the availability of the valid address on

address/data lines.
• DT/ R

• This is a Data Transmit/Receive signal.

• It decides the direction of data flow through the
transceiver.
• It is high when processor sends out data.
• Low when processor receives data.
• DEN

• This is a Data Enable signal.

• Indicates the availability of valid data over
address/data bus
• It is an active low signal from the middle of T2 until the
middle of T4.
• HOLD, HLDA

• When hold line goes high, it indicates to the processor

that another master is requesting the bus access.
• The processor, after receiving the HOLD request, issues
the HLDA signal in the middle of the next clock cycle
after completing the current bus cycle.
• When the processor detects the HOLD line low, it
lowers the HLDA signal.
Pin Description for Maximum Mode
• S0, S1, S2

 Indicate the type of operation carried out by the

microprocessor.

• Becomes active during T4 of the previous cycle and

remain active during T1 and T2 of the current bus cycle.
S2 S1 S0 Status
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive
LOCK

 Indicates that other system bus masters will be

prevented from gaining the system bus, while
the lock signal is low.

 Activated by the ‘lock’ prefix instruction and

remains active until the completion of the next
instruction.
QS1, QS0 – QUEUE SATUS

 These pins provide the status of prefetch

instruction queue.
 Active during the clock cycle after which the
queue operation is performed
Prefetch Instruction Queue operation
• Steps followed by the Microprocessor for Pipelining:
– The CS:IP is loaded with the required address from
which the execution is to be started.
– Initially, the queue will be empty and the
microprocessor starts a fetch operation to bring one
byte of instruction code.
– The first byte is a complete opcode in case of some
instructions (one byte opcode) and it is a part of
opcode in case of two byte long opcode instruction,
where the remaining part of opcode lie in 2nd byte.
• Steps followed by the Microprocessor for Pipelining:
– Opcodes along with data are fetched in the queue.
when the first byte from the queue goes for decoding
and interpretation, one byte in the queue becomes
empty and subsequently the queue is updated.

– The microprocessor does not perform the next fetch

operation till at least two bytes of the instruction
queue are emptied.

– After decoding the first byte, the decoding circuit

decides whether the instruction is of single opcode
byte or double opcode byte.
• Steps followed by the Microprocessor for Pipelining:

– If it is single opcode byte, the next bytes in the queue

are treated as data bytes.

– Otherwise, the second byte is then decoded in

continuation with the first byte to decide the
instruction length and no of subsequent bytes to be
treated as instruction data.

– A similar procedure is repeated till the complete

execution of program
 RQ/GT0 and RQ/GT1

• These are Request/Grant pins.

• Used by other local bus masters, to force the processor

to release the local bus at the end of the processors
current bus cycle.

• After receiving the request, CPU sends acknowledge

signal on the same lines.

• RQ/GT0 has higher priority than RQ/GT1.

MEMORY SEGMENTATION IN 8086

• In segmentation memory scheme ,the complete

physically available memory may be divided into a
number of logical segments .

• Each segment is 64k Bytes in size and is addressed by

one of the segment registers.

• 8086 is able to address 1 M bytes of physical memory.

MEMORY SEGMENTATION IN 8086

• The complete 1M bytes of memory can be divided into

16 segments , each of 64K bytes size .

• Addresses of the segments may be assigned as 0000H

to F000H .
• Offset address values are from 0000H to FFFFH .
• Physically address range 00000H to FFFFFH
• Types Of Segmentation

• 1. Overlapping Segment
• A segment starts at a particular address and its maximum size can
go up to 64 KB.
• If another segment starts before this 64 kB locations of the first
segment, then the two are said to be Overlapping Segment

• 2. Non-Overlapping Segment
• A segment starts at a particular address and its maximum size can
go up to 64 KB.
• If another segment starts after this 64 KB location of the first
segment, then the two segments are said to be Non-Overlapping
Segment.
Advantages of segmented memory scheme

1. Allows the memory capacity to be 1MB although the actual

addresses to b e handled are of 16 bit size.
2. Allows the placing of code, data and stack portions of the same
program in different parts(segments) of memory for data and code
protection
3. Permits a program and data to be put into different area of
memory each time the program is executed i.e. provision for
relocation is done
PHYSICAL MEMORY ORGANIZATION
• The 1MB memory is physically organized as odd bank and
even bank, each of 512kbytes, addressed in parallel by
the processor.
• Byte data with even address is transferred on D7-D0 and
byte data with odd address is transferred on D15-D-8 bus
lines.
• The processor provides two enable signals BHE and A0,
and for selecting of either even or odd or both the banks.
• Memory chips are only 1 Byte size i.e., they can store only
one byte in one memory location.
• To store 16 bit data, two successive memory locations are
used

• The lower byte of 16 bit data can be stored in first

memory location while the second byte is stored in next
location.

• In a 16 bit read or write operation both of these bytes will

be read or written in a single machine cycle.

• Thus the complete memory map of 8086 system is

divided into even and odd address memory banks.
MINIMUM MODE OF 8086
 In a minimum mode 8086 system, 8086 is operated in min
mode by strapping its MN/MX pin to logic 1.

 There is a single microprocessor in the minimum mode

system.

 In this mode, all the control signals are given out by the
microprocessor chip itself.

 The remaining components in the system are clock

generator, latches, transceivers, memory & I/O devices.
• Clock generator
• Generates clock from crystal oscillator
• Synchronizes external signal with the system clock.

• Latches:
• Separates valid address from address/data signals
• Controlled by ALE signal

• Trans-receivers:
• Bidirectional buffers (also called data amplifiers)
• Separates valid data from time multiplexed address/data bus
• Controlled by DEN and DT/R
• The DEN signal indicates the availability of valid data over the
address/data lines.
• The DT/R signal indicates direction of data, i.e. from or to the
processor.
• The system contain

• I/O devices – used for input –output operations

• ROM – used for monitor storage

• RAM – used for users program storage

• 8086 has 20 address lines and 16 data lines

• So the 8086 CPU requires three address latches and two data
buffers for the complete address and data separation.

• CS Logic indicates Chip Select Logic

• ‘e’ and ‘o’ suffixes indicate even and odd address memory banks
• The timing diagram can be categorized in two parts:
• the timing diagram for read cycle
• the timing diagram for write cycle
Timing diagram for read cycle
• The read cycle begins in T1 with the assertion of ALE signal and M / IO
signal.

• The BHE and A0 signals address low, high or both bytes.

• From T1 to T4 , the M/IO signal indicates a memory or I/O operation.
• At T2, the address is removed from the local bus and is sent to the
output. The read (RD) control signal is also activated in T2.
• The read (RD) signal causes the address device to enable its data
bus drivers. After RD goes low, the valid data is available on the
data bus.
• The addressed device will drive the READY line high.
8086 Minimum Mode Write Cycle
A write cycle also begins with the assertion of ALE and the
emission of the address.
 The M/IO signal is again asserted to indicate a memory or I/O
operation.
 In T2, after sending the address in T1, the processor sends the
data to be written to the addressed location.

 The data remains on the bus until middle of T4 state.

Maximum MODE OF 8086
 8086 operated in maximum mode by MN/MX to logic 0

 In maximum mode, there may be more than one processor in

the system configuration

 The other components in the system are same as in the minimum

mode system

 The processor derives the status signals S2, S1 and S0

 Another chip called bus controller derives the controller signals

using status information
Bus controller chip - IC8288
 The basic function of bus controller chip IC8288, derive
control signals like RD, WR, DEN, DT/R, ALE, etc. using
the information made available by the processor on the
status lines

 The bus controller chip has input lines S2, S1 and S0 and
CLK

 It derives the output

 ALE, DEN, DT/R, INTA
 MRDC, MWTC, IORC, IOWC
Timing diagram for read cycle
 S0,S1,S2 are set at the beginning of bus cycle
 8288 bus controller will output a pulse on its ALE and apply a
required signal to its DT/R pin during T1
 In T2, 8288 will set DEN = 1 thus enabling transceiver
 For an input, 8288 it will activates MRDC or IORC. These
signals are activated until T4
 For an output, the AMWC or AIOWC is activated from T2 to T4
and MWTC or IOWC is activated from T3 to T4
 The status bits S0 to S2 remain active until T3, and become
passive during T3 and T4
Timing diagram for write cycle