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FPGA Design, Development and Programming Tutorial

Overview

This Field Programmable Gate Arrays (FPGA) design and development tutorial provides a high level overview of
programming techniques and architectures for rapid development of FPGA-based hardware with National
Instruments CompactRIO and R Series intelligent DAQ systems. Use this guide to understand how LabVIEW
graphical programming tools can enable you to quickly develop reconfigurable hardware logic and successfully
architect complex applications containing FPGAs, real-time processors, networking and general purpose PCs.

This document illustrates recommended software architectures and introduces you to the hundreds of built-in
functions and tools in LabVIEW that streamline the development of sophisticated embedded applications. These
integrated hardware/software tools enable you to quickly and reliably design, prototype and deploy advanced
reconfigurable FPGA systems.

Table of Contents

1. Development Overview
2. Step 1: LabVIEW FPGA Application Development
3. Step 2: LabVIEW Real-Time Application Development
4. Step 3: LabVIEW for Windows Application Development
5. Summary
6. Appendix: Reconfigurable Hardware Platforms

Development Overview
You can use LabVIEW to quickly develop sophisticated and reliable embedded systems containing user programmable
FPGA chips, real-time processors, and industrial networking to Human Machine Interface (HMI). Embedded system
application development can be divided into three stages:

1. Developing the LabVIEW FPGA application for Input/Output (I/O), timing, synchronization, high speed control and
signal processing.
2. Developing the LabVIEW Real-Time application for deterministic floating point analysis and control as well as
fieldbus communication with a networked host computer.
3. Developing the LabVIEW for Windows application for graphical user interfaces, supervisory control and historical
datalogging.

Figure 1 and 2 below demonstrate the distribution of these three steps in the NI CompactRIO Reconfigurable
Embedded System and the R Series Intelligent DAQ System.

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Figure 1. CompactRIO Reconfigurable Embedded System Overview

The CompactRIO Embedded system consists of C Series I/O modules, a reconfigurable CompactRIO chassis
containing the FPGA and a CompactRIO Real-Time controller capable of performing deterministic floating point
calculations. The Reconfigurable Chassis communicates with the Real-Time controller over an internal PCI Bus. With
a -40 to 70 C temperature range and ability to withstand more than 50 G of shock, the CompactRIO Embedded
System is an extremely rugged production-ready OEM subsystem for high speed distributed field computing
applications.

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Figure 2. R Series Intelligent DAQ System Overview

R Series intelligent DAQ devices are PC-based plug-in boards featuring onboard FPGA hardware technology. With this
system, the FPGA is located on the PXI/PCI R Series device and an expansion chassis containing I/O modules is
connected with a digital cable. Each R Series device contains up to 8 analog inputs and outputs and up to 160 digital
I/O channels. Additional I/O can be added using the expansion chassis and C Series modules. If the FPGA interface
computer is operated in real-time mode, an additional networked host PC can be used to provide a graphical user
interface (GUI) for the intelligent DAQ system using LabVIEW 8 shared variable technology. R Series intelligent DAQ
systems are easy integrated with Motion, Vision, Modular Instruments, Data Acquisition and other PC-based plug in
devices from National Instruments.

For more information about converting your desktop or industrial PC into a LabVIEW Real-Time system refer to the
“Dedicated Real-Time Target” link below.

See Also:
NI CompactRIO Reconfigurable Control and Acquisition System Whitepaper
Dedicated Real-Time Target
R Series Intelligent DAQ Product Selection Guide

Step 1: LabVIEW FPGA Application Development

LabVIEW FPGA application development is the first step involving interaction with the I/O modules and analyzing the
acquired signals. The FPGA makes it easy to create advanced applications requiring high speed control, precise
timing, triggering and synchronization. LabVIEW FPGA offers intuitive function blocks (called Virtual Instruments or
VIs) that make the process of acquiring and generating both analog and digital signals straightforward. Functions
from the FPGA Device I/O pallet can be used for any application requiring interaction with signals; ranging from a
simple analog input reading from a thermocouple to generating PWM signals for precise control of a servo motor. The
hot swappable Input/Output modules acquire the signals, perform signal conditioning and communicate the digital
signals to the FPGA. Figure 3 shows the FPGA I/O Pallet.

Figure 3. FPGA Device I/O Pallet

With LabVIEW FPGA you can customize hardware to acquire at high rates with high accuracy. You can precisely
control timing in your application by placing a Loop Timer. The Loop Timer gives you the option to control the timing
of a loop as either a multiple of the hardware clock with rates in the order of nanoseconds or in microseconds or
milliseconds. With a hardware clock rate of 40 MHz the Loop Timer can be used to achieve loop rates as multiples of
25 nanoseconds. Figure 5 shows a simple LabVIEW FPGA function for reading an analog input channel and updating a
digital channel every 2 microseconds..

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Figure 4. Typical FPGA I/O Application with Loop Rate Timer

LabVIEW FPGA Module includes extremely powerful, ready to use, fixed-point functions to process signals directly on
the FPGA. The FPGA Math & Analysis pallet contains a wide range of functions such as a discrete PID VI for high
speed control applications, a “Sine Generator” Express VI which generates a point-by-point sine wave using direct
digital synthesis, a “Discrete Normalized Integrator.vi” which integrates a discrete input signal using forward Euler
integration and utility functions such as the “Linear Interpolation.vi” which performs linear interpolation to
approximate a function between two known points. Figure 5 presents some of the advanced intellectual property (IP)
function blocks that are included with the LabVIEW FPGA module.

Figure 5. FPGA Math & Analysis Pallets

The Saturation Arithmetic functions found on the FPGA Math & Analysis>>Saturation Arithmetic pallet can be used to
handle integer overflow when performing mathematical operations on the FPGA. These functions can be configured to
saturate at the maximum or minimum value for the data type in the event of an overflow condition, simplifying the
process of developing your own FPGA-based digital signal processing (DSP) applications. Figure 6 presents the
Saturation Add Function.

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Figure 6. Saturation Add

LabVIEW FPGA Module includes an Interrupt function, shown in Figure 7, to facilitate synchronization of execution
timing and data transfer with the LabVIEW Real-Time host applications.

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Figure 7. LabVIEW FPGA Interrupt Function

Advanced functions included with the module let you integrate Hardware Description Language (HDL), write to and
read from the FPGA FIFO, and use occurrences in your FPGA application. HDL is a low level text-based programming
language used for FPGA hardware design.

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Figure 8. HDL Interface Node in LabVIEW FPGA

FPGAs have an inherent parallel architecture allowing you to execute multiple control loops simultaneously without
effecting the loop's execution time. When combined with the LabVIEW dataflow programming paradigm and C Series
simultaneously sampling I/O modules, it becomes a straightforward process to create custom hardware circuitry with
deterministic parallel loops. For example, using LabVIEW FPGA and CompactRIO you can run multiple PID control
loops in parallel without slowing down your application.

Use the links below to learn more about the benefits of FPGA-based control systems.

See Also:
Learn more about the performance and reliability benefits of FPGA-based control systems.
Controlling Industrial Actuators Valves and Motors with LabVIEW FPGA

Step 2: LabVIEW Real-Time Application Development

LabVIEW Real-Time is a powerful tool used for performing deterministic floating point processing of the data acquired
in the FPGA application. The FPGA interface pallet makes it easy to perform real-time communication between the
FPGA and the real-time or Windows host application. FPGA registers are created simply by defining a front-panel
control or indicator on the FPGA application, and can then be written or read by the host at high speed while the
applications are running. Figure 9 presents the FPGA interface pallet.

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Figure 9. FPGA Interface Pallet

When developing a host application, the Open FPGA Reference function is first used to open and run a specified FPGA
application, or establish a connection to an FPGA application that is already running. Then the FPGA Read/Write
Control can be used to read data from the FPGA indicators or write data to the controls. When using the CompactRIO
R Series Intelligent DAQ configuration (Figure 2), it is possible to communicate with the FPGA application from
LabVIEW for Windows or LabVIEW Real-Time. Figure 10 shows an example of a simple host application that interacts
with the FPGA application of Figure 4.

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Figure 10. Simple Host Application for Live Communication with the FPGA

Refer to the CompactRIO Tutorial linked below for a step by step process of creating a LabVIEW FPGA application and
its RT Host VI.

With LabVIEW Real-Time you can deterministically execute more than 100 LabVIEW built-in functions for control and
signal processing, such as:
· PID Control
· Fuzzy Logic
· Joint Time Frequency Analysis
· Sound and Vibration Analysis

Figure 11 presents the recommended architecture for an advanced Real-Time application. The time-critical control
loop contains functions to communicate with the FPGA and perform any necessary deterministic processing. The
normal priority loop contains communication functions and is used to interact with LabVIEW for Windows and log any
data.

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Figure 11. Typical Architecture for Advanced CompactRIO Applications

LabVIEW 8 shared variable technology make it extremely simple to share data between loops deterministically and to
automatically publish data values over the Ethernet network to create multi-node distributed CompactRIO systems.
The LabVIEW 8 Datalogging and Supervisory Control (DSC) module extends this even further by enabling automatic
logging of shared variable data into a historical database.

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Figure 12. Deterministic communication between real-time threads is easy with shared variable
technology

Direct Memory Access (DMA) for LabVIEW FPGA is a technology for high speed data transfer that dramatically
improves programming ease of use and performance. Using DMA, you can easily transfer high speed buffered
waveform data from FPGA memory to real-time host processor memory with minimal CPU usage. Using
first-in-first-out (FIFO) buffers configured for DMA mode is highly efficient because the FPGA automatically handles
data transfers to the host memory over the PCI bus. DMA is also useful for debugging and probing your FPGA
application, because you can sample any register in your FPGA application at speeds up to 40 MHz, depending on the
number of channels. Note: For transferring single-point data, the the FPGA Read/Write Control methodology
explained above is well suited (see Figure 10 above).

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Figure 13. DMA provides easy data transfer for high speed buffered waveforms

Use the links below to learn more about creating intelligent distributed I/O applications with LabVIEW 8 shared
variables and DMA.

See Also:
LabVIEW 8 Shared Variables: Optimize Your Automation with Distributed Intelligence
CompactRIO Tutorials
Using the LabVIEW 8 DMA FIFO to Develop High-Speed Data Acquisition Applications
Live Online Tutorial: Share Data among Remote Nodes with the Shared Variable

Step 3: LabVIEW for Windows Application Development

The final step is to design a user interface for your application. The graphical environment of LabVIEW makes it
extremely easy to create professional looking user interfaces and connect them to networked embedded systems.
Your LabVIEW human machine interface (HMI) can contain graphs, charts, gauges, buttons, sliders and numeric
controls. Figure 14 shows the HMI for a CompactRIO application that reads quadrature encoder feedback from a
motor and calculates the velocity and acceleration of the motor shaft.

Figure 14. LabVIEW for Windows User Interface

NI DIAdem can be used in conjunction with your LabVIEW for Windows application to log large amounts of test data.
NI DIAdem easily integrates with LabVIEW and offers logical tools for managing your data. With built in functions for
analysis and report generation NI DIAdem is the ideal choice for data management. For more information about
DIAdem refer to the application note linked below.

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You can also take advantage of the LabVIEW Datalogging and Supervisory Control (DSC) Module. The LabVIEW DSC
Module is the best way to develop distributed monitoring and control systems or to automatically log shared variable
data to a historical database. With the LabVIEW DSC Module you can view real-time and historical data, configure
alarms and events, set up security on your applications, easily network to PLCs or other devices through OPC or
industrial fieldbus protocols, create operator interfaces for large distributed multi-node systems, and efficiently log
data to a historical database. The DSC Module features intuitive wizards and dialog boxes to help you develop high
channel count applications quickly and reliably.

See Also:
National Instruments DIAdem Application Note
What Is the LabVIEW Datalogging and Supervisory Control Module?
LabVIEW 8 DSC Module Features
HMIs and Industrial Touch Panels for LabVIEW

Summary

CompactRIO provides a completely customizable, powerful package. LabVIEW FPGA technology gives you the power
to design custom hardware for high performance I/O, communication and control applications using easy, high level
graphical programming. LabVIEW development tools help you get your application up and running quickly by
providing a powerful graphical programming tool chain with hundreds of built in function blocks for motion control,
PID, logic and analysis.

See Also:
Learn more

Appendix: Reconfigurable Hardware Platforms

CompactRIO Embedded System

A CompactRIO embedded system features a real-time embedded processor, 4 or 8-slot reconfigurable chassis
containing a user-programmable FPGA, and hot-swappable industrial I/O modules. This low-cost embedded
architecture delivers open access to low-level hardware resources for rapid development of custom stand-alone or
distributed control and acquisition systems.

Figure 15. CompactRIO Reconfigurable Embedded System

CompactRIO R Series Intelligent DAQ System

The CompactRIO R Series intelligent DAQ system uses the same industrial C Series I/O modules to provide
high-performance signal conditioning and industrial expansion I/O for PCI or PXI/CompactPCI R Series FPGA devices.
Intelligent DAQ systems feature user-defined, onboard processing for complete flexibility of system timing and
triggering. Instead of a fixed ASIC for controlling device functionality, intelligent DAQ uses an FPGA-based system
timing controller to make all analog and digital I/O configurable for application-specific operation.

Figure 16. CompactRIO R Series Intelligent DAQ System

For more information about the different CompactRIO setups refer to the “NI CompactRIO Reconfigurable Control and
Acquisition System Whitepaper” linked below.

See Also:
NI CompactRIO Reconfigurable Control and Acquisition System Whitepaper
R Series Intelligent DAQ Frequently Asked Questions (FAQ)

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