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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 14, NO. 12, DECEMBER 2004

A Miniature 25-GHz 9-dB CMOS Cascaded Single-Stage Distributed Amplier

AbstractA 25-GHz complementery metal oxide semiconductor (CMOS) cascaded single-stage distributed amplier (CSSDA) using standard 0.18- m CMOS technology is presented in this letter. It demonstrates the highest gain-bandwidth product (GBP) with smallest chip area reported for a fully-integrated CMOS wideband amplier using a standard Si-based integrated circuit process. The chip size including testing pads is only 0.36 mm2 , and the ratio of GBP to chip size achieves 552 GHz/mm2 . This circuit is the rst CSSDA realized in CMOS technology, and represents state-of-the-art performances. Index TermsComplementary metal oxide semiconductor (CMOS), distributed amplier, helical inductor, microwave monolithic integrated circuit (MMIC).

I. INTRODUCTION ISTRIBUTED circuits can defy some of the performance trade-offs in conventional circuits by taking advantage of multiple parallel signal paths. A distributed amplier has a more relaxed gain-bandwidth trade-off than a conventional amplier since the parasitic capacitances of the transistor are absorbed into the transmission lines or the LC ladder lter to become part of the passive network. Table I summarizes the recently reported performances of complementery metal oxide semiconductor (CMOS) broadband ampliers compared with this work [1][9]. Using the 0.6- m CMOS process, a fully integrated DA using on-chip planar spiral inductors achieves a measured pass-band gain of 6.1 dB with 5.5-GHz unity-gain bandwidth [1]. On the other hand, a fully differential DA achieves 5.5-dB pass-band gain and 8.5-GHz unity gain bandwidth [2]. Using a silicon-on-sapphire (SOS) n-type metal oxide semiconductor eld effect transistor (n-MOSFET) process to avoid the substrate loss, a DA with a bandwidth of 10 GHz and 5-dB gain was demonstrated in a 0.5- m SOS n-MOSFET (NMOS) process [3]. For DAs using 0.18- m CMOS process, a three stage DA designed with coplanar strip
Manuscript received February 1, 2004; revised March 18, 2004. This work was supported in part by the NTU-TSMC Joint-Development Project and the National Science Council under Contracts NSC 92-2213-E-002-069 and NSC 93-2752-E-002-002-PAE. The review of this letter was arranged by Associate Editor A. Stelzer. M.-D. Tsai and H. Wang are with the Department of Electrical Engineering and Graduate Institute of Communication Engineering, National Taiwan University, Taipei 10617, Taiwan, R.O.C. (e-mail: [email protected]; [email protected]). K.-L. Deng was with the Department of Electrical Engineering and Graduate Institute of Communication Engineering, National Taiwan University, Taipei 10617, Taiwan, R.O.C., and he is now with Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C. C.-H. Chen, C.-S. Chang, and J. G. J. Chern are with the Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C. Digital Object Identier 10.1109/LMWC.2004.837387

lines demonstrated a low frequency gain of 5 dB, sloping down to 1 dB at 15 GHz [4], two DAs using high impedance coplanar waveguides as inductive elements demonstrated 8 and 10-dB gain up to 10 GHz, respectively [5], and DAs of 14-GHz and 22-GHz bandwidth were also demonstrated in [6], [7]. The highest operation frequency of DA using 100-GHz 0.18- m CMOS technology based on modied source degeneration (parallel RC network) achieved 4-dB gain and 39-GHz bandwidth [8], and a 27-GHz CPW 0.18- m CMOS DA had a measured gain of 6 dB [9]. A fully integrated conventional DA, however, suffers the disadvantage of huge chip size. Another type of distributed circuit called cascaded single-stage distributed amplier (CSSDA) in CMOS technology were also presented their simulation results but no measurement data were demonstrated [10], [11]. A CSSDA with huge chip size has also been proposed to achieve wide bandwidth and realized in GaAs HEMTs or hybrid circuits [12], [13]. In this letter, a miniature CSSDA based on cascade conguration and monolithic helical inductors using a commercial CMOS process is rst demonstrated. The gain-bandwidth product of our miniature chip is believed to be the highest among the recently published results for CMOS distributed ampliers. 0.48 mm, The chip size including testing pads is only 0.75 and the ratio of GBP to chip size achieves 552 GHz/mm . This circuit is the rst CSSDA realized in CMOS technology, and represents state-of-the-art performances. II. CIRCUIT DESIGN AND FABRICATION In the design of wideband distributed ampliers, articial transmission lines can be realized by multiorder LC ladder network. In conjunction with active devices connected in parallel, the parasitic capacitance of active devices is absorbed into the LC ladder network. The inductor can be realized with transmission lines or spiral inductors [1][9]. However, the drawback is large die size. In order to reduce chip size, the inductance of the articial transmission line is realized with helical inductors. Helical inductor occupies less chip area than that of planar spiral since the turn is expanded vertically as shown in Fig. 1(a). Usually, top metal is thicker than the lower metal layers, and thus -factor of helical inductor would be lower than that of planar spiral inductor. However, the area occupation of helical inductor is much smaller. Furthermore, smaller area gives smaller substrate loss, so only little performance degradation of the helical inductor over the planar spiral inductor in circuit is prospective [14]. For example, a 2-nH of helical inductor can achieve peak quality factor of eight at 5 GHz and self-resonance frequency of 16 GHz [15].

1531-1309/04$20.00 2004 IEEE

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TSAI et al.: MINIATURE 25-GHz 9-dB CMOS CASCADED SINGLE-STAGE DISTRIBUTED AMPLIFIER

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TABLE I RECENTLY REPORTED PERFORMANCE OF CMOS DISTRIBUTED AMPLIFIER. SOS: SILICON-ON-SAPPHIRE. CPW: COPLANAR WAVEGUIDE. CPS: COPLANAR STRIP LINES. CC: CASCODE CONFIGURATION. DC BIAS USING BIAS-T

Fig. 1. (a) Cross-sectional view of helical inductor. (b) Simplied circuit schematic of cascaded single-stage distributed amplier (CSSDA). Fig. 2. Measured small signal gain and I/O return losses.

The schematic of the CMOS CSSDA is shown in Fig. 1(b). It consists of an input, output, and interstage transmission lines formed by using lumped helical inductors, coupled through the transconductance of the MOSFETs. The intrinsic gate and drain would increase the loss of the articial transresistance mission line and thus degrade the gain and bandwidth. In this study, the cascade conguration is used for the gain cells. The cascade gain cell can increase the drain resistance and reduce the loading in transmission line, also has higher maximum available gain compared to a common-source FET. The cascade devices of this design employ a 20- damping resistor in the gate of common-gate transistor to improve the high frequency stability. Since the characteristic impedance of the inter-stage articial ) can be different from the input and transmission line ( output impedance, it shows that the gain can be increased by the gate voltage of the inter-stage transmission line with increasing [12]. With the target gain and bandwidth, the increasing

also can reduce the required gain stages and reduce chip area. In this circuit, only two stages are used. The helical inductors were simulated with a full-wave EM simulator to ensure the model accuracy. The MMIC micrograph is shown in Fig. 4 with a chip size of 0.36 mm including testing pads. The chip is fabricated by TSMCs 0.18- m MS/RF technology [16], [17], with a 2- m AlCu top metal layer. The substrate conductivity is approximately 10 S/m. With optimized CMOS technology and and of better deep n-well, this technology provides a than 60 and 55 GHz, respectively. III. EXPERIMENTAL RESULTS The CMOS CSSDA chip was tested via on-wafer probing. , and return losses ( Fig. 2 shows the measured gain and ). The power gain is about 9 dB with a 3-dB frequency

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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 14, NO. 12, DECEMBER 2004

25-GHz bandwidth, which indicates the highest gain-bandwidth product of reported to date for broadband CMOS ampliers. The highest gain-bandwidth product is also achieved in only 0.36 mm chip area. This amplier has potential for the signal amplication for the receiver in the optical communication application. Since this CSSDA was fabricated using a commercial 0.18- m CMOS technology, it can be easily integrated with other front-end circuits to build CMOS transceivers without requiring any additional masks or post-processing steps. REFERENCES
[1] B. M. Ballweber, R. Gupta, and D. J. Allstot, A fully integrated 0.55.5-GHz CMOS distributed amplier, IEEE J. Solid State Circuits, vol. 35, pp. 231239, Feb. 2000. [2] H. Ahn and D. J. Allstot, A 0.58.5-GHz fully differential CMOS distributed amplier, IEEE J. Solid State Circuits, vol. 37, pp. 985993, Aug. 2002. [3] P. F. Chen et al., Silicon-on-sapphire MOSFET distributed amplier with coplanar waveguide matching, in Proc. IEEE RFIC Symp., 1998, pp. 161164. [4] B. Kleveland et al., Monolithic CMOS distributed amplier and oscillator, in Proc. IEEE Int. Solid-State Circuits Conf., 1999, pp. 7071. [5] B. M. Frank, A. P. Freundorfer, and Y. M. M. Antar, Performance of 110-GHz traveling wave ampliers in 0.18-m CMOS, IEEE Microwave Wireless Compon. Lett, vol. 12, pp. 327329, Sept. 2002. [6] R. C. Liu, K. L. Deng, and H. Wang, A 0.622-GHz broadband CMOS distributed amplier, in Proc. IEEE RFIC Symp., 2003, pp. 13106. [7] R. C. Liu, C. S. Lin, K. L. Deng, and H. Wang, A 0.514-GHz 10.6-dB CMOS cascode distributed amplier, in Proc. IEEE VLSI Circuits Symp., 2003, pp. 139140. [8] H. Shigematsu, M. Sato, T. Hirose, F. Brewer, and M. Rodwell, 40 GB/s CMOS distributed amplier for ber-optic communication systems, in Proc. IEEE Int. Solid-State Circuits Conf., 2004, pp. 476477. [9] R. E. Amaya, N. G. Tarr, and C. Plett, A 27 GHz fully integrated CMOS distributed amplier using coplanar waveguide, in Proc. IEEE RFIC Symp., 2004, pp. 193196. [10] A. Worapishet, M. Chongcheawchamnan, and S. Srisathit, Broadband amplication in CMOS technology using cascaded single-stage distributed amplier, Electron. Lett., vol. 38, pp. 675676, July 2002. [11] , On the feasibility of cascaded single-stage distributed amplier topology in digital technology, in Proc. IEEE Midwest Symp. Circuits Systems, 2002, pp. 354257. [12] B. Y. Banyamin and M. Berwick, Analysis of the performance of fourcascaded single-stage distributed ampliers, IEEE Trans. Microwave Theory Tech., vol. 48, pp. 26572663, Dec. 2000. [13] K. L. Deng, T. W. Huang, and H. Wang, Design and analysis of novel high-gain and broad-band GaAs pHEMT MMIC distributed ampliers with traveling-wave gain stages, IEEE Trans. Microwave Theory Tech., vol. 51, pp. 21882196, Nov. 2003. [14] J. Gil, S. S. Song, H. Lee, and H. Shin, A 119:2 dBc=Hz at 1 MHz, 1.5 mW, fully integrated, 2.5-GHz, CMOS VCO using helical inductors, IEEE Microwave Wireless Compon. Lett., vol. 13, pp. 457459, Nov. 2003. [15] M. D. Tsai, Design of 5-GHz low-voltage and gain-controllable CMOS low noise amplier, M.S. thesis, Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2003. [16] H. M. Hsu et al., A 0.18-m foundry RF CMOS technology with 70-GHz Ft for single chip system solutions, in IEEE Int. Microwave Symp. Dig., 2001, pp. 18691872. [17] C. H. Diaz et al., A 0.18-m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications, in Proc. IEEE VLSI Technical Symp., 1999, pp. 1112.

Fig. 3. Measured group delay.

Fig. 4. Microphotograph of the CMOS CSSDA with a chip size of 0.75 0.48 mm (including testing pads).

band up to 25 GHz, and return losses are better than 8 dB. The measured -parameters results agree with the simulated results reasonably. The measured group delay, as shown in Fig. 3, is about 45 ps with variation of 30 ps from 1 to 20 GHz. The meadBm at 10 GHz. The two-tone test sured output dB is result shows that the output IP3 is about 8 dBm at 10 GHz. The supply voltage is 3.5 V and consumes 17 mA. Although the dc bias current goes through termination resistors, the total power consumption (60 mW) is still comparable with those of the reported DAs using bias-T to supply drain voltages [4], [6], [7]. The overall performance rivals the recently published results reported for CMOS distributed ampliers. IV. CONCLUSION A fully integrated CSSDA has been designed, fabricated and tested. This CMOS CSSDA demonstrated 9-dB gain and

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