Verilog Cheatsheet endcase
Prepared by: Garima jangid for (i = 0; i < 4; i = i + 1)
1.Basic structure statement;
module module_name (input1, output1, ...);
input input1; 7. Modules & Instantiation
output output1; // Define
reg r1; module adder(input [3:0] a, b, output [4:0] sum);
wire w1; assign sum = a + b;
// Design logic here endmodule
endmodule
// Instantiate
2. Data Types adder a1(.a(x), .b(y), .sum(out));
Type Description
wire Represents a connection 8. Initial & Testbench
(combinational) initial begin
reg Holds value (for procedural blocks) clk = 0;
integer, Used for simulations forever #5 clk = ~clk;
real end
initial begin
// stimulus
3. Always Block rst = 1; #10;
always @(posedge clk) begin rst = 0; #100;
// Sequential logic $finish;
end end
always @(*) begin
// Combinational logic 9. File I/O (for simulation)
end $readmemb("data.txt", mem);
$display("Value = %b", val);
4. Operators $monitor("At %t: val = %d", $time, val);
Type Symbols
10. Bit Selection & Concatenation
Arithmetic +, -, *, /, %
a[3] // Select bit 3
Logical &&, `
a[3:0] // Select bits 3 down to 0
Bitwise &, ` {a, b} // Concatenate a and b
Relational ==, !=, >, <
Shift <<, >> 11. Useful Directives
Ternary cond ? true : false
`timescale 1ns/1ps
`define WIDTH 8
`include "defs.v"
5. Timing Control (Simulation only)
#10; // wait for 10 time units
12. Blocking vs Non-blocking
@(posedge clk); // wait for clock rising edge
Type Symbol Usage
Blocking = Executes sequentially
6. Control Structures (combinational)
if (condition) Non- <= Executes in parallel
statement; blocking (sequential)
else // BAD EXAMPLE (in sequential logic)
statement; a = b;
b = a; // Wrong!
case (sel)
2'b00: out = a; // GOOD EXAMPLE
2'b01: out = b; a <= b;
default: out = 0; b <= a;
always @(posedge clk or posedge rst) begin
13. Parameters & localparam if (rst)
parameter WIDTH = 8; // Can be overridden at state <= IDLE;
instantiation else
localparam MAX = 255; // Constant, cannot be state <= next;
overridden end
reg [WIDTH-1:0] data; always @(*) begin
case (state)
IDLE: next = LOAD;
14. Generate Block (Parameterized Modules) LOAD: next = EXECUTE;
genvar i; EXECUTE: next = DONE;
generate DONE: next = IDLE;
for (i = 0; i < 4; i = i + 1) begin : gen_block endcase
and a1 (out[i], in1[i], in2[i]); end
end
endgenerate 18. Signed vs Unsigned Arithmetic
reg signed [7:0] a, b;
wire signed [8:0] result;
15. Memories (ROM, RAM)
reg [7:0] memory [0:255]; // 256 x 8-bit memory assign result = a + b;
// Write 19. System Tasks (Simulation Control)
always @(posedge clk) Task Purpose
memory[addr] <= data_in; $display(...) Print once
$monitor(...) Continuously print changes
// Read (combinational) $dumpfile(...) VCD file for waveform
assign data_out = memory[addr]; $dumpvars(...) Dump variable data
$finish End simulation
initial begin
16. Testbench Essentials $dumpfile("wave.vcd");
module tb; $dumpvars(0, tb);
reg clk, reset; end
wire [3:0] out;
20. Macros & Includes
counter uut (.clk(clk), .reset(reset), .out(out)); `define WIDTH 8
`include "my_defines.vh"
initial begin
clk = 0; reg [`WIDTH-1:0] data;
forever #5 clk = ~clk;
end 21. Conditional Compilation
`ifdef DEBUG
initial begin $display("Debug Info: value = %d", value);
reset = 1; #10; `endif
reset = 0;
#100; 22. Package-like include Files (optional)
$finish; In pure Verilog (not SystemVerilog), use include for
end constants/macros:
endmodule // file: constants.vh
`define CLK_PERIOD 10
17. State Machine Example
typedef enum logic [1:0] {IDLE, LOAD, EXECUTE, // file: design.v
DONE} state_t; `include "constants.vh"
state_t state, next;
