Module 2- 8086 Microprocessor

8086
Architecture

2
8086 Architecture
8086 Microprocessor is divided into two functional units,
 EU (Execution Unit) and
 BIU (Bus Interface Unit).
 Contains circuit for physical address calculation and a predecoding
instruction byte queue (6BYTES LONG)
 The Bus Interface Unit (BIU) generates the 20-bit physical memory
address and provides the interface with external memory (ROM/RAM).
 EU (Execution Unit)
 Execution unit gives instructions to BIU starting from where to fetch the
data and then decode and execute those instructions. Its function is to
control operations on data using the instruction decoder & ALU.
 EU has no direct connection with system buses as shown in the above figure,
it performs operations over data through BIU.
 Alu is a functional unit in EU. ALU handles all arithmetic and logical
operations, like +, −, ×, /, OR, AND, NOT operations.
3
8086 Architecture
BIU (Bus Interface Unit)
 BIU takes care of all data and addresses transfers on the buses for the EU
like sending addresses, fetching instructions from the memory, reading
data from the ports and the memory as well as writing data to the ports
and the memory.
 EU has no direction connection with System Buses so this is possible with
the BIU. EU and BIU are connected with the Internal Bus.
 It has the following functional parts −
 Instruction queue − BIU contains the instruction queue. BIU gets upto 6
bytes of next instructions and stores them in the instruction queue. When
EU executes instructions and is ready for its next instruction, then it
simply reads the instruction from this instruction queue resulting in
increased execution speed.
 Fetching the next instruction while the current instruction executes is
called pipelining.
4
 8086 Architecture
 The Bus Interface Unit (BIU) generates the 20-bit physical memory address
and provides the interface with external memory (ROM/RAM).
 8086 has a single memory interface. To speed up the execution, 6-bytes of
instruction are fetched in advance and kept in a 6-byte Instruction Queue
while other instructions are being executed in the Execution Unit (EU).
 Hence after the execution of an instruction, the next instruction is directly
fetched from the instruction queue without having to wait for the external
memory to send the instruction.
 This is called pipe-lining and is helpful for speeding up the overall
execution process.
 8086's BIU produces the 20-bit physical memory address by combining a 16-
bit segment address with a 16-bit offset address.

5
8086 Architecture- PSW- Flag Register

6
8086 Architecture- Flag Register
Flag Register
 It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status
according to the result stored in the accumulator.
 It has 9 flags and they are divided into 2 groups − Conditional Flags and Control
Flags.
Conditional Flags
 It represents the result of the last arithmetic or logical instruction executed.
Following is the list of conditional flags −
 Carry flag − This flag indicates an overflow condition for arithmetic operations.

7
 8086 Architecture- Flag Register
 Auxiliary flag − When an operation is performed at ALU, it results in
a carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e.
D4 – D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF
flag. The processor uses this flag to perform binary to BCD
conversion.
 Parity flag − This flag is used to indicate the parity of the result, i.e.
when the lower order 8-bits of the result contains even number of
1’s, then the Parity Flag is set. For odd number of 1’s, the Parity Flag
is reset.
 Zero flag − This flag is set to 1 when the result of arithmetic or
logical operation is zero else it is set to 0.
 Sign flag − This flag holds the sign of the result, i.e. when the result
of the operation is negative, then the sign flag is set to 1 else set to
0.
 Overflow flag − This flag represents the result when the system
capacity is exceeded. 8
 8086 Architecture- Flag Register
Control Flags
 Control flags controls the operations of the execution unit. Following is
the list of control flags −
 Trap flag − It is used for single step control and allows the user to
execute one instruction at a time for debugging. If it is set, then the
program can be run in a single step mode.
 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to
allow/prohibit the interruption of a program. It is set to 1 for interrupt
enabled condition and set to 0 for interrupt disabled condition.
 Direction flag − It is used in string operation. As the name suggests
when it is set then string bytes are accessed from the higher memory
address to the lower memory address and vice-a-versa.

9
8086 Architecture- Functional parts
Decoding Unit
 The decoding unit decodes opcode bytes issued from the instruction
byte queue.
Timing and Control Unit
 Timing and control unit derives the necessary control signals to
execute the instruction opcode received from the queue, depending
on information made available by decoding circuit.
 The execution unit passes the result to bus interface unit for storing
them in memory.

10
 Addressing modes
 The different ways in which a source operand is denoted in an instruction is known as
addressing modes.
 There are 8 different addressing modes in 8086 programming −
 Immediate addressing mode The addressing mode in which the data operand is a part of
the instruction itself is known as immediate addressing mode.
 Register addressing mode It means that the data is stored in a register and it is referred
using particular register. All registers except IP may be used in this mode

11
Addressing mode
Direct addressing mode
 The addressing mode in which the 16 bit memory address(offset) is directly
specified in the instruction.

 Data resides in data segment. Effective address computed by adding 1592h to

content if Data segment which is segment address -10HxDS +1592 h
Register indirect addressing mode
 This addressing mode allows data to be addressed at any memory location through
an offset address held in any of the following registers: BP, BX, DI & SI. The default
segment is DS or ES.
Eg: MOV AX,[BX] -Data is present in data segment whose offset address is in BX. The
effective address is 10H*DS+[BX]

12
Addressing mode
Indexed addressing mode
 In this addressing mode, OFFSET of the operand is stored in one of
the index registers. DS is default segment for SI and DI. Incase of
string instructions DS and ES are default segments of SI and DI
respectively.
Eg: MOV AX,[SI] Effective address is 10HxDS+[SI]
Register relative
 Data is available at an effective address formed by adding 8-bit/16-
bit displacement with the content of any of the registers BX, BP, SI, DI
in the default (DS or ES segment)
Eg: MOV AX, 50H[BX]- Effective address is 10HXDS+50H+[BX]

13
Addressing mode
Based-index addressing mode
 In this addressing mode, the offset address of the operand is computed by
summing the base register (BX or BP) to the contents of an Index register (SI or DI).
 Eg: MOV AX,[BX] [SI]- BX is base register, SI IS INDEX REGISTER. The effective
address is 10HxDS +[BX]+[SI]
Relative based indexed
 In this addressing mode, effective address is formed by adding 8 or 16 bit
displacement with sum of contents of any one of the base registers (BX or BP) and
any one of the index registers in a default segment.
 Eg: MOV AX,50H [BX][ SI]
 50H is displacement. BX is base register. SI is index register. Effective address is
10H*DS+{BX]+[SI]+50H

14
8086 register organization

Pointers and Indexing registers

15
 8086 register organization
 Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the
addresses of instructions and data in memory, which are used by the processor
to access memory locations. It also contains 1 pointer register IP, which holds
the address of the next instruction to executed by the EU.
 CS − It stands for Code Segment. It is used for addressing a memory location in
the code segment of the memory, where the executable program is stored.
 DS − It stands for Data Segment. It consists of data used by the program and is
accessed in the data segment by an offset address or the content of other
register that holds the offset address.
 SS − It stands for Stack Segment. It handles memory to store data and
addresses during execution.
 ES − It stands for Extra Segment. ES is additional data segment, which is used
by the string to hold the extra destination data.
 Instruction pointer (IP)− It is a 16-bit register used to hold the address of the
next instruction to be executed

16
 8086 General purpose registers
 There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL.
 These registers can be used individually to store 8-bit data and can be used in
pairs to store 16bit data. The valid register pairs are AH and AL, BH and BL, CH and
CL, and DH and DL.
 It is referred to the AX, BX, CX, and DX respectively.
 AX register − It is also known as accumulator register. It is used to store operands
for arithmetic operations.
 BX register − It is used as a base register. It is used as an offset storage to form
memory address in certain addressing modes.
 CX register − It is referred to as counter. It is used in loop instruction to store the
loop counter.
 DX register − This register is used as a general purpose register which may be used
as an implicit operand or destination in case of few instructions.

17
8086 Pointer and index registers
 IP-Instruction Pointer-offset with in code segment.
 BP-Base pointer-Offset within stack segment.
 SP-Stack pointer-Offset within stack segment
 SI-Source Index register
 DI-Destination Index
 The index registers are used as general purpose registers as well as for
offset storage in case of indexed ,base indexed and relative base indexed
addressing modes.
 SI is used to store offset of source data in data segment
 DI is used to store offset of destination data or extra segment.
 The index registers are particularly useful for string manipulations.

18
8086 Memory segmentation

19
8086 Memory segmentation
 The number of address lines in 8086 is 20, 8086 BIU will send
20bit address, so as to access one of the 1MB memory locations.
 8086 has a segmented memory.
 Complete physical memory may be divided into no : of logical
segments. Each segment is 64 Kbytes in Size and is addressed by
one of the segments.
 The 16 bit content of segment register actually point to starting
location of a particular segment.
 To address a specific memory location within a segment we need
an offset address. The offset address is also 16 bits long.
 Complete 1 MB memory can be divided into 16 segments each of
64KBytes.

20
 8086 Memory segmentation

Advantages of segmented memory scheme

 Allows the memory capacity to be 1 MB although the actual
address to be handled are of 16 bit size.
 Allows placing of code data and stack portions of same
program in different parts of memory for data and code
protection
 Permits a program and/or its data to be put to different
areas of memory each time program is executed. ie
provision for relocation is done

21
8086 Memory segmentation

 Each of these segments are addressed by an

address stored in corresponding segment
register.
 These registers are of 16-bit in size.
 Each register stores the base address (starting
address) of the corresponding segment.
 Because the segment registers cannot store 20
bits, they only store the upper 16 bits

22
 8086 Memory segmentation
 Rules of Segmentation
 Segmentation process follows some rules as follows:
 The starting address of a segment should be such that it can be evenly divided by 16.
 Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

23
8086 Creating physical address
Example

24
8086 Physical address calculation
 For Example:
 Code segment Register CS holds the segment address which is 4569 H
 Instruction pointer IP holds the offset address which is 10A0 H
 The physical 20-bit address is calculated as follows.
 Segment address: 45690 H
 Offset address :+ 10A0 H
 Physical address : 46730 H
45690
10A0
46730

25
8086 Segmentation

Non overlapping Overlapping

26