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B022414(022)
B. Tech. (Fourth Semester) Examination,
April-May 2023
(Scheme: AICTE)
(CSE Branch)
OBJECT ORIENTED PROGRAMMING (with Java)
Paper : (BT3020)
Time Allowed : Three hours

Maximum Marks: 100

MinimMm Pass Marks : 35

Note : Attempt all questions. Part (a) of each question

is compulsory carrying 4 marks. Attempt any
two parts from part (b), (c) and (d) carrying &
marks each.
UnitI

Java.
1. (a) Give any 4 differences between C++ and
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(b) Explain Constructors in Java with the help of (c) Explain following :
exampke. () Reader Class
(c) Explain static members in java with proper example. (ü) Writer Class

(d) What is mutable and immutable in Java. Also explain

(d) What is Java Machine? Explain its architecture.
string and string buffer class.
Unit-II
Unit-IV
2. (a) Write down any 4 differences between method
4. (a) Explain AWT in Java.
overloading and overriding.
(b) Explain the life cycle of Applets using example.
(b) Explain Exception-Handling in Java. Give one
example for user defined exception. (c) Explain JDBC drivers availabie in Java

(c) Explain Abstract Class and Interface with suitable (d) Explain Server Socket with the heip of example.
example.
UniV
(d) Discuss about Singleton Class in Java using example. Collection
5. (a) What do you understand by Java
Unit-III Framwork?

3. (a) What is mutithreading? (b) Explain following

() Aray List
(b) What is synchronization in Java? Fxplain using () Linked List
suitable examples.

NK22)
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 |4|
present in a Hash
(c) How do you get all the keys
Map?

(d) ExplainEvent Delegation Model (EDM).

1,970] B022414(022)
Printed Pages - 5 Roll No,
TUIE.O
cHNOLOGY
BO22412(022) LIBRARY
DIR JC.G.
B. Tech (Fourth Semester) Examination,
Apri-May 2023
(AICTE Scheme)

(CSE Branch)
COMPUTER SYSTEM ARCHITECTURE

Time Allowed : Three hours

Maximun Marks : 100

Minimum Pass Marks : 35

Note : Attempt all questions. Part (a) in each unit is

compulsory. Attempt any two from (b), (c)
and (d). Part (a) is of 4 marks and part (b).
(c) and (d) are of 8 marks each.
Unit-I

1. (a) What is difference between : 4

) MAR and MDR

register
(ü) General purpose register and instruction
PTO
B022412(022)
 |2 | |3|

(b) Consider the following possibiities for saving a retum (iü) Relative,
for subroutines : (iv) Register indirect
) In a processor register
Unit-II
(ü) In amemory location associated with the call,
so that a different location is used when the 2. (a) What is a Fast Adder? Design a 4 bit adder with
sub-routine is called from different places. carry-lookahead.

() On a stack (b) Define bit pair recoding. Explain Booths multiplication

Which of these possibilities supports subroutine alongwith for 2's complement number using flowchart
nesting and which supports subroutine recursion? and example.
Explain each. 8
(c) Design datapath for an n-bit two's complement
adder subtractor. 8
(c) Analyze various buses used in bus structure and
express the importance of all buses. 8
(d) Define guard bits. Describe the implementation 'of
(d) What is Addressing Mode? Explain any 3addressing binary parallel adder/subtractor circuit using ful!
adders.
mdoes. An instruction is stored at location 300 with
its address field at location 301. The address field
Unit-III
has the value 400, a processor register RI contain
the number 200. Evaluate the effective address if 3. (a) What is Virtual Memory? Write its advantages and
the addressing modes of instruton are : disadvantages. How is it different from main memory? 4
8

) Direct, (b)Draw and explain Memory Hierarchy. Explain each

() Immediate, level in brief.

BO22412(022)
BO22412(022)
 |4}
|51
çonsists of
(c) A biock set-associative cache memory ) Interrupt handikng mechanism
The main
12 blocks divided into 4 block set.
() Fault tolerance systems 8
memory consists of 16,3¬4 blocks and each block
contains 256eight bit words. Unit-V

() How many bits are required for addressing the 5. (a) Consider a pipeline having 4 phase with duration
main memory? 60, 50, 90 and 880 ns. Given latch delay is 10 ns.
(M) How many bits are needed to represent the Calculate:
TAG SET and WORD fields? 8
) Non-pipeline execution time
(d) Explain cache mepping. Explain thetypes of cache (ü) Speed-up ratio 4

mapping with example.

(b) What is Parallel Processing? Explain Flynn's classi
fications of parallel architecture. 8
Unit-IV

4. (a) Difierentiate between synchronous and asynchronous (c) What is Pipeling? Explain 4 segthent of instruction
data transfer. 4 pipeline.

(b) What is Address space? Explain Isolated VO and (d) What is Arithmetic Pipeline? Explain floating point
Memory Mapped O. addition using arithmetic pipeline. Also write its
8
applications.
(c) What is DMA transfer? Explain role of DMA
controller with diagram. 8

(d) Write short notes on:

BO22412(022)