Energy Efficient Compact Approximate Multipplier for

Error Resilient Applications

K Kavya1, D Omkar2, K Dhana Lakshmi3 , B Ajay Kumar4, G.Manoj5 ,V Madhurima6

1,2,3,4,5 UG Scholars, Dept of ECE, Sri Venkateswara Engineering College,Tirupati, India;

6.Professor, Dept of ECE, Sri Venkateswara College of Engineering,Tirupati, India;

Email : [email protected],[email protected]
Abstract
The primary goal of estimated computing is to increase the performance of the system, such as energy efficiency, speed and
form factor. Despite the increasing use of estimated qualities, the design of efficient estimated compressors is a fundamental
multiplier block is an important challenge. In this short, 8-transistors and 14-transistors 4: 2 compressors are proposed. Both
compressors exploit a constant and conditional intensity of CMOS technology and selected inputs, displaying less negative
errors. As a result, a resource-habitat error recovery module is abolished, the yield of better performance than the previous
art. The 14-Tranceist Architecture produces a lower error rate compared to the 8-Tranzister architecture, closing the lower
area for high accuracy. Compressor-Silavaya Circuit Architecture has also been proposed and evaluated using image
multiplication. The proposed multiplier displays 38% PDP growth compared to the exact multiplier to save 50% area and
93% less power-deeds, as well as high accuracy, and state-of-the-art.

Keywords: Approximate computing, compressor, multiplier, image multiplication

. approximations, particularly in multipliers, due to the high

power consumption and delays of traditional methods.
I. INTRODUCTION Conventional multiplication operations are complex and
increase power usage and latency. Approximate
Modern digital systems face challenges in energy efficiency, multiplication aims to mitigate these issues by allowing
power consumption, and processing speed, particularly in minor inaccuracies while maintaining acceptable output
image processing and machine learning where exact quality. Various techniques, including truncation, reduced
accuracy is less critical. Approximate computing allows for bit-widths, and approximate partial product generation, have
minor accuracy losses in exchange for significant hardware been proposed to optimize energy efficiency while trading
improvements, making it suitable for tasks like filtering and some accuracy for improved performance.
AI predictions.This work presents two majority-logic circuit
designs: an 8-transistor approximate compressor for 8-bit Energy-Efficient Compact Approximate Multipliers:
multipliers and a refined 14-transistor version for better
accuracy. These designs, supported by simulations and real-
world tests, enhance energy-efficient computing in error-
tolerant applications like computer vision and signal
processing.

II. LITERATURE SURVEY

Recent research has focused on creating energy-efficient
Approximate computing has gained attention as a technique and compact approximate multipliers that balance energy
to enhance energy efficiency and performance in error- consumption and computational accuracy. Techniques such
tolerant applications like image processing, deep learning, as hybrid approximate multipliers, adaptive error correction
and signal processing. The need for low-power, high- mechanisms, and machine learning-based models have been
performance computing has led to hardware-level developed to enhance efficiency. These designs aim to
maximize power savings while keeping error rates within
acceptable limits for error-tolerant applications.

Application Areas of Approximate Multipliers

Approximate computing has been widely adopted in error-
tolerant applications like image and video processing,
machine learning, and digital signal processing.
Applications such as JPEG compression and age detection
can tolerate minor errors, enabling energy-efficient
processing. Deep learning models use approximate multiplier in exhibits high error rates and increased area,
computation to reduce power consumption with minimal
while5 introduces an error recovery module (ERM) to
impact on accuracy. In DSP, approximate multipliers are
employed in low-power audio and communication systems enhance accuracy and reduce field consumption.
where perfect precision is unnecessary. Configurable multipliers in4 balance accurate and
approximate modes, achieving up to 50% output errors.
EXISITING SYSTEM Majority logic (ML) and CMOS-based circuits
significantly lower power and area at the cost of higher
error rates. Techniques like circuit stacking, algorithm-
Approximate 4:2 compressor based error control, and probability-based correction
demonstrate reduced errors but require larger areas.
Accurate 4:2 compressors use two full adders but are
hardware-intensive, especially with XOR gates consuming
more energy. To address this, designs using only AND and
OR gates have been proposed, reducing costs and delays.
Approximate 4:2 compressors prioritize efficiency over
accuracy, as seen in designs with configurable modes or
error recovery modules to balance error rates and power
consumption. Some designs show high error rates but
achieve significant area reduction, while others use error
correction modules for improved accuracy. These
compressors demonstrate promising applications in energy-
efficient multipliers for tasks like image processing and
machine learning. Fig. 1. Proposed design flow of 8-bit multiplier. 2. Schematics of the
compressor circuits (a): Exact. (b): ML-based, and (c): ACMLC and
CAC, respectively.

PROPOSED APPROXIMATE COMPRESSORS

Majority logic (ML) is a fault-tolerant design paradigm that
enhances reliability, simplicity, and efficiency in circuits by
using collective decision-making. An ML gate outputs true
or false based on whether the majority of its inputs are
correct or incorrect. ML-based designs require fewer gates,
making them ideal for reducing circuit area without
sacrificing accuracy. In the proposed 8-bit multiplier design,
PROPOSED SYSTEM
ML-based components generate approximate bits and
Recent studies have proposed various approximate 4:2 transfer them to simplified circuits with half adders and full
compressors prioritizing circuit efficiency and low delays. adders, ensuring a balance between efficiency and
Designs in3 and4 focus on reducing power consumption computational accuracy.
and area while maintaining acceptable error rates. The
4:2 Approximate Condition-Based ML Compressor error distance (ED) of 2 and 3 negative errors (compared
to 4 in [7]).
The ML Circuit Architecture described in [7] is used and Our approach simplifies Boolean functionality and
improved with a two-phase approach. Fig. The 2 circuit reduces circuit area. To further enhance accuracy, we
shows schimatics, including the exact compressor circuit introduce the CAC circuit architecture (Figure 2C), which
(C.F., Fig. 2 (A)), ML-based compressor (C.F., FIG. 2 (b), compensates for ACMLC errors. It employs a typical 4:2
[7]), and the proposed projected position-based projected compressor with a carry output, yielding fewer errors and
compressed and CACC (CACC) for the proposed position- negative errors, although it increases the number of
based position-based ML (ACMLC). Note that ML-Based transistors from 8 to 14.
Compressor [7] Consider only three of the four inputs
(input X2 is ignored) and a certain output (SUM = VDD). Despite having two more transistors than [7], the CAC
Carrie output is correct if at least two inputs are '1' (ie, X1 + offers significant reductions in negative errors, making it
X3 + X4 is equal to two or three), a total of four negative ideal for high-performance, accurate multipliers.
and four positive errors. In Section III-B, we present a skilled multiplier circuit
Recently the approximate circuit [14] has done using both ACMLC and CAC architectures, which
extensive research on the effects of negative and positive incorporates efficient components for accurate and high-
errors. In the approximate area of a multiplier, each performance operations. For the 8-bit multiplier, we focus
approximate compressor produces an error, thereby a on reducing errors by optimizing partial product
significant error distance in columns. It is important to calculations (PPS) using approximate components.

TABLE I : TRUTH TABLE FOR THE ACMLC COMPRESSOR

employ an error recovery module (ERM) based on

specific input patterns for individual estimated
compressors, reducing overall error distance and reducing
negative errors. As a result, the importance of ERM
circuit has been emphasized to mitigate negative errors
[5], [11], [12] Fig. 3. Proposed multiplier schematic using the proposed
ACMLC-based compressor and CAC.

In [13], continuous values have been assigned to many

We propose the ACMLC circuit architecture (Figure 2C)
LSB PP Bits. The possibilities of generating 0 or 1 for
to improve multiplier design by reducing negative errors
each circuit producing P0, P1, P2, P3, and P4 were
and circuit area. This architecture eliminates the need for
investigated by applying various inputs. According to the
ERM due to its low negative error rate and coherent error
comments, the correct four LSB bits are fixed on
production. It uses a typical majority-based adjacent
P0P1P2P3 = 0110. By fixing LSB bits at a constant price,
compressor where the carry output is 1 when two or more
the number of required gates decreases. In this case, ten
inputs are 1. The ACMLC 4:2 compressor has only 9
and gates are removed from the first four columns of the
errors (one more than [7]), with only one error having an
 proposed multiplier circuit (as shown with gray triangular bit multiplication by 15 out of 64, requiring only 49 gates.
shaded area in figs). Stage 2 includes two accurate FAS, with carry output from
CAC transferred to the final joint level. Stage 3 typically
TABLE II : PERFORMANCE OF 4:2 COMPRESSORS
uses ripple carry adders (RCAs), but with ACMLC and
CAC, the number of required adders is reduced. The final
stage uses a HA with two '1' inputs as an inverter and three
FAs applied via XOR and OR gates. Overall, the
simplicity of the architecture leads to significant savings in
power, area, and delay compared to accurate or ML-based
multipliers [7]. Experimental results show the proposed
786-transistor multiplier is 49% smaller than the 1530-
transistor accurate multiplier [15] and 12.6% smaller than
the 900-transistor ML-based multiplier [7].
The estimated component of the proposed multiplier
RESULTS
We check and compare our compressors and multiplies with
prior tasks reviewed in Section II. Please note that all circuit
performance results, including power consumption, delay
time and power-deer product (PDP), are reported based on
Xilinx simulation. When input and output signal reach 50%
of the supply voltage, it has been reported. The generalized
mean error distance (nMed) and the mean relative error
distance (mred) accuracy is reported on the basis of the
includes five ACMLC-based compressors, one CAC, two metrics xilinx simulation. The operation is set on the supply
accurate and one accurate FA. With the proposed 3-input voltage and 2GHz frequency of the operation. Finfet models
ACMLC-based compressor, one of the four PPs has been are based on parameters [7], except for the fin height and
effectively eliminated, resulting in the abolition of five length of the gate, which are set on 18Nm and 11Nm
respectively, both for both P-type and N-type transistors.
more gates within a single PP phase. At that stage, eight
unused (solid black circles) and gates are renovated to Fig.6.1.Image multiplication performance with
form a compressor-based chain in the second stage, approximate multipliers with respect to FoMs– (a): FoM1,
which reduces the overall area. The proposed CAC is (b): FoM2, (c): FoM3, (d): FoM4
used to move Carry = 1 to the exact component in the
final column of the approximate component, simplifying
the exact compressor circuit. Finally, simplified accurate
compressor [15] (with continuous input, cin = 1) is only
used in the entire multiplier. Note that the use of FA is
accurate and the proposed ACMLC-based compressor
and multiplication in the smaller area of CAC enhance
the accuracy in the multiplication accuracy. We describe
the revival of the function of the circuit below.
TABLE IV : APPROXIMATE MULTIPLIERS PSNR RESULTS
IN IMAGE MULTIPLICATION

Stage 2 of the proposed architecture incorporates CAC,

using more AND gates for higher compression accuracy.
Stage 1, based on ACMLC, adds four additional ACMLC
compressors, reducing the number of gates required for 8-
 Table III compares the proposed 786-transistor multiplier
with [16], showing it as the second smallest circuit, reducing
area by 49% compared to the accurate multiplier. It
outperforms in PDP (0.51 FJ) and PDAP (96%
improvement). This is due to the ACMLC-based
compressor, CAC, and the multiplier architecture. Although
the proposed multiplier doesn't match the accuracy of state-
of-the-art solutions, its error rate falls within the expected
. range for approximate qualities and is lower than the
baseline ML-based compressor in power, area, and delay
(Table II). Improved accuracy is due to fewer negative
errors and lower cumulative ED.

Conclusion
In this brief, we proposed an 8-transistor ACMLC
compres- sor, a 14-transistor CAC, and an approximate 8-bit
multiplier for accurate and efficient image multiplication.
The compres- sor has small footprint and low power
consumption at the expense of a relatively high error rate.
To compensate for the negative errors, we propose CAC,
exhibiting seven errors, with only one being negative. We
propose an ACMLC/CAC-based approximate multiplier to
exploit the proposed compressors’ unique characteristics.
Relative to an exact multiplier, the proposed multiplier
exhibits 50% area reduction and 93% power savings. The
proposed multiplier exhibits superior performance across
most evaluated metrics compared to state- of-the-art
approximate multipliers. The Pareto results revealthat
despite their lower accuracy, ML-based proposed cir- cuits
are promising for low-power and energy dissipation
applications..
Fig.6.2. Performance of the multipliers with respect to References
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