Behavioral Description

Learning Objectives
• Explain the significance of structured procedures always and initial in
behavioral modeling.
• Define blocking and nonblocking procedural assignments.
• Understand delay-based timing control mechanism in behavioral modeling.
Use regular delays, intra-assignment delays, and zero delays.
• Describe event-based timing control mechanism in behavioral modeling.
Use regular event control, named event control, and event OR control.
• Use level-sensitive timing control mechanism in behavioral modeling.
• Explain conditional statements using if and else.
• Describe multiway branching, using case, casex, and casez statements.
• Understand looping statements such as while, for, repeat, and forever.
• Define sequential and parallel blocks.
• Understand naming of blocks and disabling of named blocks.
• Use behavioral modeling statements in practical examples.
Structured Procedures
• There are two structured procedure statements in Verilog: always and
initial.
• These statements are the two most basic statements in behavioral
modeling.
• All other behavioral statements can appear only inside these
structured procedure statements.
• Activity flows in Verilog run in parallel rather than in sequence.
• Each always and initial statement represents a separate activity flow
in Verilog.
• Each activity flow starts at simulation time 0. The statements always
and initial cannot be nested.
initial Statement
• All statements inside an initial statement constitute an initial block.
• An initial block starts at time 0, executes exactly once during a
simulation, and then does not execute again. If there are multiple
initial blocks, each block starts to execute concurrently at time 0.
• Each block finishes execution independently of other blocks.
• Multiple behavioral statements must be grouped, typically using the
keywords begin and end.
• If there is only one behavioral statement, grouping is not necessary.
This is similar to the begin-end blocks in Pascal programming
language or the { } grouping in the C programming language
Combined Variable Declaration and
Initialization
Combined Port/Data Declaration and
Initialization
Combined ANSI C Style Port Declaration and
Initialization
always Statement
• All behavioral statements inside an always statement constitute an
always block.
• The always statement starts at time 0 and executes the statements in
the always block continuously in a looping fashion.
• This statement is used to model a block of activity that is repeated
continuously in a digital circuit.
• An example is a clock generator module that toggles the clock signal
every half cycle.
• In real circuits, the clock generator is active from time 0 to as long as
the circuit is powered on. Example 4-5 illustrates one method to
model a clock generator in Verilog.
Procedural Assignments
• Procedural assignments update values of reg, integer, real, or time
variables.
• The value placed on a variable will remain unchanged until another
procedural assignment updates the variable with a different value.
• The syntax for the simplest form of procedural assignment is shown below.
assignment ::= variable_lvalue = [ delay_or_event_control ] expression
The left-hand side of a procedural assignment can be one of the following:
• A reg, integer, real, or time register variable or a memory element
• A bit select of these variables (e.g., addr[0])
• A part select of these variables (e.g., addr[31:16])
• A concatenation of any of the above
The right-hand side can be any expression that evaluates to a value.
Blocking Assignments
• Blocking assignment statements are executed in the order they are
specified in a sequential block.
• A blocking assignment will not block execution of statements that
follow in a parallel block.
• The = operator is used to specify blocking assignments.
• A blocking assignment gets its name because a blocking assignment
must evaluate the RHS arguments and complete the assignment
without interruption from any other Verilog statement.
• The assignment is said to "block" other assignments until the current
assignment has completed.
Example 7-6 Blocking Statements
Nonblocking Assignments
• Nonblocking assignments allow scheduling of assignments without
blocking execution of the statements that follow in a sequential block.
• A <= operator is used to specify nonblocking assignments. Note that this
operator has the same symbol as a relational operator, less_than_equal_to.
• The operator <= is interpreted as a relational operator in an expression and
as an assignment operator in the context of a nonblocking assignment.
• To illustrate the behavior of nonblocking statements and its difference from
blocking statements, let us consider Example 7-7, where we convert some
blocking assignments to nonblocking assignments, and observe the
behavior.
Application of nonblocking assignments
• Having described the behavior of nonblocking assignments, it is
important to understand why they are used in digital design.
• They are used as a method to model several concurrent data transfers
that take place after a common event.
• Consider the following example where three concurrent data
transfers take place at the positive edge of clock.
Example 7-8 Nonblocking Statements to Eliminate
Race Conditions
//Illustration 1: Two concurrent always blocks with blocking
//statements
always @(posedge clock) a = b;
always @(posedge clock) b = a;
//Illustration 2: Two concurrent always blocks with nonblocking
//statements
always @(posedge clock) a <= b;
always @(posedge clock) b <= a;
Example 7-9 Implementing Nonblocking
Assignments using Blocking Assignments
//Emulate the behavior of nonblocking assignments by
//using temporary variables and blocking assignments
always @(posedge clock)
begin
//Read operation
//store values of right-hand-side expressions in temporary variables
temp_a = a; temp_b = b;
//Write operation
//Assign values of temporary variables to left-hand-side variables
a = temp_b; b = temp_a; end
Conditional Statements
• Conditional statements are used for making decisions based upon
certain conditions.
• These conditions are used to decide whether or not a statement
should be executed.
• Keywords if and else are used for conditional statements.
• There are three types of conditional statements.
Example 7-18 Conditional Statement
Examples
//Type 1 statements //Type 3 statements
if(!lock) //Execute statements based on ALU control
buffer = data; signal.
if(enable) if (alu_control == 0) y = x + z;
out = in; else if(alu_control == 1)
//Type 2 statements y = x - z;
if (number_queued < MAX_Q_DEPTH) else if(alu_control == 2)
Begin y = x * z;
data_queue = data; else
number_queued = number_queued + 1; $display("Invalid ALU control signal");
end
else $display("Queue Full. Try again");
Multiway Branching

case Statement
casex, casez Keywords
• There are two variations of the case
statement.
• They are denoted by keywords, casex
and casez.
• casez treats all z values in the case
alternatives or the case expression as don't
cares. All bit positions with z can also
represented by ? in that position.
• casex treats all x and z values in the case
item or the case expression as don't cares.

The use of casex and casez allows

comparison of only non-x or -z positions in
the case expression and the case
alternatives.
Loops
• There are four types of looping statements in Verilog: while, for,
repeat, and forever.
• The syntax of these loops is very similar to the syntax of loops in the C
programming language.
• All looping statements can appear only inside an initial or always
block. Loops may contain delay expressions.
While Loop
For Loop
• The keyword for is used to specify this loop.
• The for loop contains three parts:
• An initial condition
• A check to see if the terminating condition is true
• A procedural assignment to change value of the control variable
Repeat Loop
• The keyword repeat is used for this loop.
• The repeat construct executes the loop a fixed number of times.
• A repeat construct cannot be used to loop on a general logical
expression.
• A while loop is used for that purpose.
• A repeat construct must contain a number, which can be a constant, a
variable or a signal value.
• However, if the number is a variable or signal value, it is evaluated
only when the loop starts and not during the loop execution.
Forever loop
• The keyword forever is used to express this loop.
• The loop does not contain any expression and executes forever until the
$finish task is encountered.
• The loop is equivalent to a while loop with an expression that always
evaluates to true, e.g., while (1).
• A forever loop can be exited by use of the disable statement.
• A forever loop is typically used in conjunction with timing control
constructs.
• 7 If timing control constructs are not used, the Verilog simulator would
execute this statement infinitely without advancing simulation time and
the rest of the design would never be executed.
Sequential and Parallel Blocks
• Block statements are used to group multiple statements to act
together as one.
• In previous examples, we used keywords begin and end to group
multiple statements.
• Thus, we used sequential blocks where the statements in the block
execute one after another.
• In this section we discuss the block types: sequential blocks and
parallel blocks.
• We also discuss three special features of blocks: named blocks,
disabling named blocks, and nested blocks.
Block Types
• There are two types of blocks: sequential blocks and parallel blocks.
Sequential blocks
• The keywords begin and end are used to group statements into
sequential blocks.
• Sequential blocks have the following characteristics:
• The statements in a sequential block are processed in the order they are
specified. A statement is executed only after its preceding statement completes
execution (except for nonblocking assignments with intra-assignment timing
control).
• If delay or event control is specified, it is relative to the simulation time when
the previous statement in the block completed execution.
 Example 7-26 Sequential Blocks
//Illustration 1: Sequential block //Illustration 2: Sequential blocks with delay.
without delay reg x, y;
reg x, y; reg [1:0] z, w; reg [1:0] z, w;
initial initial
Begin begin
x = 1'b0; x = 1'b0; //completes at simulation time 0
y = 1'b1; #5 y = 1'b1; //completes at simulation time 5
z = {x, y}; #10 z = {x, y}; //completes at simulation time 15
w = {y, x}; #20 w = {y, x}; //completes at simulation time
end 35
end
Parallel blocks
• Parallel blocks, specified by keywords fork and join, provide interesting
simulation features. Parallel blocks have the following characteristics:
• Statements in a parallel block are executed concurrently.
• Ordering of statements is controlled by the delay or event control assigned
to each statement.
• If delay or event control is specified, it is relative to the time the block was
entered.
Notice the fundamental difference between sequential and parallel blocks.
All statements in a parallel block start at the time when the block was
entered.
Thus, the order in which the statements are written in the block is not
important.
Special Features of Blocks
• Nested blocks
• Blocks can be nested.
Sequential and parallel blocks
can be mixed, as shown in
Example 7-28
Named blocks
• Blocks can be given names.
• Local variables can be declared for the named block.
• Named blocks are a part of the design hierarchy. Variables in a
named block can be accessed by using hierarchical name referencing.
• Named blocks can be disabled, i.e., their execution can be
stopped.
Disabling named blocks