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4X1 Mux

The document describes a VHDL implementation of a multiplexer (MUX) and its corresponding testbench. The MUX selects one of four input signals (A, B, C, D) based on a 2-bit select signal (S) and outputs it to Z. The testbench initializes the inputs and applies different select signals to verify the functionality of the MUX.

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rishitha032613
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4 views2 pages

4X1 Mux

The document describes a VHDL implementation of a multiplexer (MUX) and its corresponding testbench. The MUX selects one of four input signals (A, B, C, D) based on a 2-bit select signal (S) and outputs it to Z. The testbench initializes the inputs and applies different select signals to verify the functionality of the MUX.

Uploaded by

rishitha032613
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX is
Port (
A,B,C,D:IN STD_LOGIC ;
S:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Z:OUT STD_LOGIC );
end MUX;

architecture Behavioral of MUX is


BEGIN
PROCESS (A,B,C,D,S)
BEGIN
CASE S IS
when "00"=>
Z<=A;
when "01"=>
Z<=B;
when "10"=>
Z<=C;
when "11"=>
Z<=D;
when OTHERS=>
Z<='0';
END CASE;
END PROCESS;
end Behavioral;

TESTBENCH:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX_TB is
end MUX_TB;

architecture Behavioral of MUX_TB is


SIGNAL S: STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS=>'0');
SIGNAL A,B,C,D:STD_LOGIC :='0';
SIGNAL Z:STD_LOGIC :='0';
COMPONENT MUX is
Port (
A,B,C,D:IN STD_LOGIC ;
S:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Z:OUT STD_LOGIC );
end COMPONENT MUX;
begin
DUT: MUX
port map(
A=>A,
B=>B,
C=>C,
D=>D,
S=>S,
Z=>Z);
STIMULUS:
process
BEGIN
A <= '1'; B <= '0'; C <= '1'; D <= '0';
S<="00";
WAIT FOR 100ns;
S<="01";
WAIT FOR 100ns;
S<="10";
WAIT FOR 100ns;
S<="11";
WAIT FOR 100ns;
WAIT;
end process;
end Behavioral;

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