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    Bridge Faults

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    Rambabu Thalluri
    Bridge faults occur when there is a short circuit between two nodes, modeled as a 0Ω resistance. There are four possible manifestations of a bridge fault depending on the signal strengths. Test generation targets all four cases by modifying the circuit to include four single stuck-at faults representing each case. The BART tool generates tests for bridge faults by first modifying the circuit model, then using ATPG to target the resulting four stuck-at faults to produce test vectors.

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    Bridge Faults

    Uploaded by

    Rambabu Thalluri
    159 views9 pages
    Bridge faults occur when there is a short circuit between two nodes, modeled as a 0Ω resistance. There are four possible manifestations of a bridge fault depending on the signal strengths. Test generation targets all four cases by modifying the circuit to include four single stuck-at faults representing each case. The BART tool generates tests for bridge faults by first modifying the circuit model, then using ATPG to target the resulting four stuck-at faults to produce test vectors.

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    Bridge faults occur when there is a short circuit between two nodes, modeled as a 0Ω resistance. There are four possible manifestations of a bridge fault depending on the signal strengths. Test generation targets all four cases by modifying the circuit to include four single stuck-at faults representing each case. The BART tool generates tests for bridge faults by first modifying the circuit model, then using ATPG to target the resulting four stuck-at faults to produce test vectors.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    159 views9 pages

    Bridge Faults

    Uploaded by

    Rambabu Thalluri
    Bridge faults occur when there is a short circuit between two nodes, modeled as a 0Ω resistance. There are four possible manifestations of a bridge fault depending on the signal strengths. Test generation targets all four cases by modifying the circuit to include four single stuck-at faults representing each case. The BART tool generates tests for bridge faults by first modifying the circuit model, then using ATPG to target the resulting four stuck-at faults to produce test vectors.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 9

    Outline

    l l l

    Bridge Fault Model Bridge Fault Simulation Test Generation for Bridge Fault

    ECE 1767

    University of Toronto

    Bridge Fault Model


    l l l

    After single stuck-at faults, bridge faults are the most important class of faults. Most commonly occurring type of fault. Simplified model assumes 0 resistance (short) between two lines (dotted line in the figure)
    x1 x x2

    y
    ECE 1767 University of Toronto

    Bridge Fault Model


    l

    Wired-AND y=0 --> x is s-a-0 Test for bridge fault: s Set y to 0 and test for x s-a-0 -ors Set x to 0 and test for y s-a-0 Wired-OR y=1 --> x is s-a-1 Test for bridge fault: s Set y to 1 and test for x s-a-1 -ors Set x to 1 and test for y s-a-1

    Dominant driver

    x always outdrives y y always outdrives x


    University of Toronto

    ECE 1767

    Bridge Fault Model


    x1 x Bridge Function y x2

    Assumes 0 resistance
    ECE 1767 University of Toronto

    Bridge Fault Model


    l

    Need to consider drive strengths of bridged nodes to determine voltage level.


    x 1

    ECE 1767

    University of Toronto

    Bridge Fault Model


    l

    Gates driven by the bridged nodes may interpret the voltage level differently, depending on their logic threshold voltages.

    Byzantine Generals Problem x1 x x2

    y
    ECE 1767 University of Toronto

    Feedback Bridge Faults


    l

    In a feedback bridge fault, there exists at least one path between the two bridged nodes.

    The back line b is the line closest to the PIs. The front line f is the line closest to the POs. b f

    AND:

    set b=0 and test for f s-a-0 (no logical feedback) set f=0 and test for b s-a-0, but not through f (i.e., f is not sensitive to b).
    University of Toronto

    ECE 1767

    Feedback Bridge Faults


    l

    If a feedback loop involves an odd number of inversions, the circuit may oscillate.

    AND-bridge b f

    OR-bridge b f

    ECE 1767

    University of Toronto

    Bridge Faults
    l

    Output-to-Output

    Between metal lines in routing channels Outputs of different gates. Between inputs of the same gate in polysilicon Between an input and output of the same gate Between source and drain of the same transistor in diffusion.

    Input-to-Input

    Input-to-Output

    Source-to-Drain

    BART [Patel et al., 1996]: Bridge Fault Test Generator


    University of Toronto

    ECE 1767

    Input-to-Output Short
    l

    In a simple CMOS gate, if the short causes an error, then input value is forced upon the output [Vierhaus, Meyer, Glaser, ITC93] This is also true for complex CMOS gates such as And-Or-Invert (AOI) and Or-AndInvert (OAI) gates

    [Cusey, M.S. Thesis, 1993]

    Test vectors for input and output stuck-at faults cover Input-to-output shorts. Input-to-Output shorts not targeted in BART

    ECE 1767

    University of Toronto

    Source-to-Drain Short
    l

    Also called transistor stuck-on fault.


    Not strictly a logic fault. However, any test vector that detects such a fault must always detect some structurally related logic stuck-at fault.

    Source-drain shorts not targeted in BART.

    ECE 1767

    University of Toronto

    Logic Model for a Bridge


    A B C D 0 G

    1 0 FAULT-FREE G,H = 0,1 G,H = 1,0

    H FAULTY G,H = 0,0 G,H = 1,1 G,H = 0,0 G,H = 1,1 MODEL H s-a-0 G s-a-1 G s-a-0 H s-a-1
    University of Toronto

    ECE 1767

    One of Four Possible Error Manifestations


    A B 1 1 s-a-1 X 1 1 0/1 1/0
    C D H

    0
    A B

    G
    G

    0 0 0

    C D

    1/0

    Modeled as Logic Fault F s-a-1


    ECE 1767 University of Toronto

    Circuit Modification for ATPG


    l

    All four possible manifestations of a bridge are simultaneously addressed in a single circuit modification

    Adds about 10 gates per bridge.

    Four single stuck-at faults in the modified circuit represent the four error manifestations. ATPG can be used to generate four possible test vectors Test generation complexity is the same as a stuck-at fault test generation.
    University of Toronto

    ECE 1767

    Strong and Weak Logic Values


    1 A B0 C 1 D 0 A 0 B 0 C 1 D
    ECE 1767

    weak 1

    G ?

    weak 0 strong 1

    H ?

    G 1

    weak 0 -> 1

    H 1 (error)
    University of Toronto

    Generalized Bridge Model


    A B G
    A B C D Bridge Function 0
    MUX

    H
    1
    MUX

    C D F
    s-a-1
    ECE 1767

    University of Toronto

    BART Test Generation


    l l

    l l

    Faults extracted by a randomly generated list Site of the target bridge modified according to the strength model. ATPG generates tests for the 4 stuck-at faults. If strength values cannot be justified, BART reverts to the normal logic value model. BART generates vectors for 10 target bridges before invoking a fault simulator

    ECE 1767

    University of Toronto

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