UNIT-1

UNIT-I INTRODUCTION & INSTRUCTION SET

Computer Organization is concerned with the way the hardware components
operate and the way they are connected together to form the computer system.
Computer Architecture is concerned with the structure and behavior of a
computer system as seen by the user. It includes the instruction formats, the
instruction set, the techniques for addressing the memory.

The 8 Great Ideas in Computer Architecture

 Design for Moore's Law
 Use Abstraction to Simplify Design
 Make the Common Case Fast
 Performance via Parallelism
 Performance via Pipelining
 Performance via Prediction
 Hierarchy of Memories
 Dependability via Redundancy
1. Design for Moore‘s Law
 Moore‘s Law principle states that since the number of transistors on a silicon
chip roughly doubles every two years, the performance and capabilities of
computers will continue to increase while the price of computers decreases. It is a
prediction made by American engineer Gordon Moore in 1965.

2. Use Abstraction to Simplify Design

 Abstraction allows multiple levels of a design, where the low-level details do not
always need to be a concern when interacting with high-level details. The
instruction set of a processor hides the details of the activites involved in
executing an instruction.

3. Make the Common Case Fast

Improvements to the common case (where the computer spends the most time
executing instructions) have resulted in the most significant improvements in
computer performance. Amdahl‘s law is used to calculate these improvements.

4. Performance via Parallelism

 Performing a tasks in parallel takes less time than performing them sequentially.
A computer becomes faster if it can run processes in parallel.

5. Performance via Pipelining

 This is an extension of parallelism, where instructions may be broken up into
stages and multiple instructions may be executing at the same time, but in their
different stages. This results in more instructions executed per unit time than what
would have been if the full instructions were executed from start to finish
sequentially.

6. Performance via Prediction

 Computer programs will almost always contain conditional branches. Branches
interfere with the smooth operation of a pipeline, where sometimes the pipeline
needs to be flushed out and restarted if the program jumps to a different section
of code. Performance is improved if the computer can guess if a branch is taken or
not and the penalty of wrong guesses is not severe (results in just a pipeline flush).

7. Hierarchy of Memories
 The principle of locality says that memory that has been accessed recently is
likely to be accessed again in the near future. To make the common case of re-
accessing recently used data faster, a cache is used. The cache will have a shorter
data fetch time than going all the way to the main storage (disk). Modern
processors use multiple levels of caching.

8. Dependability via Redundancy

 Redundancy is very important in data storage technologies. The most commonly
used idea is the Redundant Array of Inexpensive Disks (RAID). Using
redundancy protects data from being lost if one disk fails because the data can be
recovered from the other disks.

Boolean Logic:
Boolean Algebra is also sometimes referred to as Boolean Logic or just Logic. It
is a method of representing expressions using only two values (True and False
typically) and was first proposed by George Boole in 1847.
Boolean logic
Boolean logic is a type of algebra in which results are calculated as either TRUE
or FALSE (known as truth values or truth variables). Instead of using arithmetic
operators like addition, subtraction, and multiplication, Boolean logic utilizes
three basic logical operators: AND, OR, and NOT.

Rule in Boolean Algebra

Complement of a variable is represented by an overbar (-). Thus, complement
Following are the important rules used in Boolean algebra:
Variable used can have only two values. Binary 1 for HIGH and Binary 0 for
Low. Complement of a variable is represented by an overbar (-).
 OR-ing of the variables is represented by a plus (+) sign between them. ...
 Logical AND-ing of the two or more variables is represented by writing a dot
between them, such as A.B.C.
Logic gates
Binary information is represented in the digital computers by physical quantities
called signals. Each signals such as voltages exists throughout the computer either
in 0 or 1 states. The two states represent a binary variable 0 or 1.

o The logic gates are the main structural part of a digital system.
o Logic Gates are a block of hardware that produces signals of binary 1 or 0 when
input logic requirements are satisfied.
oEach gate has a distinct graphic symbol, and its operation can be described by
means of algebraic expressions.
oThe seven basic logic gates includes: AND, OR, XOR, NOT, NAND, NOR, and
XNOR.
o The relationship between the input-output binary variables for each gate can be
represented in tabular form by a truth table.
o Each gate has one or two binary input variables designated by A and B and one

binary output variable designated by x.

AND GATE:

The AND gate is an electronic circuit which gives a high output only if all its
inputs are high. The AND operation is represented by a dot (.) sign.

OR GATE:

The OR gate is an electronic circuit which gives a high output if one or more of its
inputs are high. The operation performed by an OR gate is represented by a plus
(+) sign
NOT GATE:

The NOT gate is an electronic circuit which produces an inverted version of the
input at its output. It is also known as an Inverter.

NAND GATE:

The NOT-AND (NAND) gate which is equal to an AND gate followed by a NOT
gate. The NAND gate gives a high output if any of the inputs are low. The NAND
gate is represented by a AND gate with a small circle on the output. The small
circle represents inversion

NOR GATE:

The NOT-OR (NOR) gate which is equal to an OR gate followed by a NOT gate.
The NOR gate gives a low output if any of the inputs are high. The NOR gate is
represented by an OR gate with a small circle on the output. The small circle
represents inversion

Exclusive-OR/ XOR GATE:

The 'Exclusive-OR' gate is a circuit which will give a high output if one of its
inputs is high but not both of them. The XOR operation is represented by an

encircled plus sign

Universal gates:

The NAND gate is a special type of logic gate in the digital logic circuit. The
NAND gate is the universal gate. It means all the basic gates such as AND, OR,
and NOT gate can be constructed using a NAND gate. The NAND gate is the
combination of the NOT-AND gate. The output state of the NAND gate will be
low only when all the inputs are high. Simply, this gate returns the complement
result of the AND gate.

The 2-input NAND Gate

This is the simple formation of the NAND gate. In this type of NAND gate, there
are only two input values and an output value. There are 2 2=4 possible
combinations of inputs. The truth table and logic design are given below.

NOR Gate

The NOR gate is also a universal gate. So, we can also form all the basic gates
using the NOR gate. The NOR gate is the combination of the NOT-OR gate. The
output state of the NOR gate will be high only when all of the inputs are low.
Simply, this gate returns the complement result of the OR gate.

The 2-input NOR gate

Just like other gates, it is also a simple form of the NOR gate. In this type of NOR
gate, there are only two input values and an output value. There are 2 2=4 possible
combinations of inputs. The truth table and logic design are given below:
De Morgan‘s Theorems

Two of the theorems were suggested by De Morgan that are extremely useful
for Boolean Algebra.

Theorem 1

Theorem 2
  The LHS of this theorem represents a NOR gate with
inputs A and B, whereas the RHS represents an AND
gate with inverted inputs.
 This AND gate is called as Bubbled AND.

How to Write a Boolean Expression to Simplify Circuits?

Our first step in simplification must be to write a Boolean
expression for this circuit.
This task is easily performed step by step if we start by writing
sub-expressions at the output of each gate, corresponding to the
respective input signals for each gate.
Remember that OR gates are equivalent to Boolean addition,
while AND gates are equivalent to Boolean multiplication.
For example, I’ll write sub-expressions at the outputs of the first
three gates:
. . . then another sub-expression for the next gate:

Finally, the output (“Q”) is seen to be equal to the expression AB

+ BC(B + C):
Generating Schematic Diagrams from
Boolean Expressions
Now, we must generate a schematic diagram from this Boolean
expression.
To do this, evaluate the expression, following proper
mathematical order of operations (multiplication before addition,
operations inside parentheses before anything else), and draw
gates for each step.
Remember again that OR gates are equivalent to Boolean
addition, while AND gates are equivalent to Boolean
multiplication.
In this case, we would begin with the sub-expression “A + C”,
which is an OR gate:

The next step in evaluating the expression “B(A + C)” is to

multiply (AND gate) the signal B by the output of the previous
gate (A + C):

Obviously, this circuit is much simpler than the original, having

only two logic gates instead of five.
Combinational and Sequential Circuits
Digital logic circuits can be classified into “combinational” and “sequential”. A
combinational logic circuit is one whose output solely depends on its current
inputs. sequential circuits, on the other hand, sequential circuits are built using
combinational circuits and memory elements called “flip-flops”. These circuits
generate output that depends on the current and previous states.
1. Combinational Circuits: These circuits are developed using AND, OR,
NOT, NAND, and NOR logic gates. These logic gates are building blocks of
combinational circuits. A combinational circuit consists of input variables and
output variables. Since these circuits are not dependent upon previous input to
generate any output, so are combinational logic circuits. A combinational circuit
can have an n number of inputs and m number of outputs. In combinational
circuits, the output at any time is a direct function of the applied external
inputs.

Half Adder

The half adder is a basic building block having two inputs and two outputs.
The adder is used to perform OR operation of two single bit
binary numbers. The carry and sum are two output states of the half
adder.

Full Adder

The half adder is used to add only two numbers. To overcome this problem,
the full adder was developed. The full adder is used to add three 1-bit binary
numbers A, B, and carry C. The full adder has three input states and two
output states i.e., sum and carry.
2. Sequential circuits: A sequential circuit is specified by a time sequence of
inputs, outputs, and internal states. The output of a sequential circuit depends
not only on the combination of present inputs but also on the previous outputs.
Unlike combinational circuits, sequential circuits include memory elements
with combinational circuits. Some examples are counters and shift registers.

 The memory elements are circuits capable of storing binary information.

 The binary information stored in these memory elements at any given
time defines the state of the sequential circuit at that time.
 The external output of a sequential circuit depends both on the present
input and the previous output state.
 The next state of the memory elements also depends on the external input
and the present state of the external output.
 Some sequential circuits may not contain combinational circuits, but only
memory elements.
 Generally, there are two types of storage elements used: Latches,
and Flip-Flops. Storage elements that operate with signal levels (rather
than signal transitions) are referred to as latches; those controlled by a
clock transition are flip-flops.
 Another major difference between the combinational and sequential
circuits is the feedback mechanism.

Types of Sequential Circuits:

There are two types of sequential circuits:

Type 1: Asynchronous sequential circuit: These circuits do not use a clock
signal but uses the pulses of the inputs. These circuits are faster than
synchronous sequential circuits because there is clock pulse and change their
state immediately when there is a change in the input signal. We use
asynchronous sequential circuits when speed of operation is important and
independent of internal clock pulse.

Type2: Synchronous sequential circuit: These circuits uses clock signal and
level inputs (or pulsed) (with restrictions on pulse width and circuit
propagation). The output pulse is the same duration as the clock pulse for
the clocked sequential circuits. Since they wait for the next clock pulse to
arrive to perform the next operation, so these circuits are bit slower compared
to asynchronous. Level output changes state at the start of an input pulse and
remains in that until the next input or clock pulse.

We use synchronous sequential circuit in synchronous counters, flip flops, and

in the design of MOORE-MEALY state management machines. We use
sequential circuits to design Counters, Registers, RAM, MOORE/MEALY
Machine and other state retaining machines.

Advantages of Sequential Circuits:

1. Memory: Sequential circuits have the ability to store binary values,
which makes them ideal for applications that require memory elements, such as
timers and counters.
2. Timing: Sequential circuits are commonly used to implement timing and
synchronization in digital systems, making them essential for real-time control
applications.
3. State machine implementation: Sequential circuits can be used to
implement state machines, which are useful for controlling complex digital
systems and ensuring that they operate as intended.
4. Error detection: Sequential circuits can be designed to detect errors in
digital systems and respond accordingly, improving the reliability of digital
systems.

Disadvantages of Sequential Circuits:

1. Complexity: Sequential circuits are typically more complex than

combinational circuits and require more components to implement.
2. Timing constraints: The design of sequential circuits can be challenging
due to the need to ensure that the timing of the inputs and outputs is correct.
Testing and debugging: Testing and debugging sequential circuits can be more
difficult compared to combinational circuits due to their complex structure
and state-dependant outputs.
Functional Components of a Computer
Computer: A computer is a combination of hardware and software resources
which integrate together and provides various functionalities to the user.
Hardware are the physical components of a computer like the processor,
memory devices, monitor, keyboard etc. while software is the set of programs or
instructions that are required by the hardware resources to function properly.
There are a few basic components that aids the working-cycle of a computer i.e.
the Input- Process- Output Cycle and these are called as the functional
components of a computer. It needs certain input, processes that input and
produces the desired output. The input unit takes the input, the central
processing unit does the processing of data and the output unit produces the
output. The memory unit holds the data and instructions during the processing.
Digital Computer: A digital computer can be defined as a programmable
machine which reads the binary data passed as instructions, processes this
binary data, and displays a calculated digital output. Therefore, Digital
computers are those that work on the digital data.
Details of Functional Components of a Digital Computer

 Input Unit: The input unit consists of input devices that are attached to
the computer. These devices take input and convert it into binary
language that the computer understands. Some of the common input
devices are keyboard, mouse, joystick, scanner etc.
 Central Processing Unit (CPU): Once the information is entered into
the computer by the input device, the processor processes it. The CPU is
called the brain of the computer because it is the control centre of the
computer. It first fetches instructions from memory and then interprets
them so as to know what is to be done. If required, data is fetched from
memory or input device. Thereafter CPU executes or performs the
required computation and then either stores the output or displays on the
output device. The CPU has three main components which are
responsible for different functions – Arithmetic Logic Unit (ALU),
Control Unit (CU) and Memory registers
 Arithmetic and Logic Unit (ALU): The ALU, as its name suggests
performs mathematical calculations and takes logical decisions.
Arithmetic calculations include addition, subtraction, multiplication and
division. Logical decisions involve comparison of two data items to see
which one is larger or smaller or equal.
  Control Unit: The Control unit coordinates and controls the data flow in
and out of CPU and also controls all the operations of ALU, memory
registers and also input/output units. It is also responsible for carrying out
all the instructions stored in the program. It decodes the fetched
instruction, interprets it and sends control signals to input/output devices
until the required operation is done properly by ALU and memory.

Types of central processing units:

CPUs are defined by the processor or microprocessor driving them:

 Single-core processor: A single-core processor is a microprocessor with one
CPU on its die (the silicon-based material to which chips and microchips are
attached). Single-core processors typically run slower than multi-core
processors, operate on a single thread and perform the instruction cycle
sequence only once at a time. They are best suited to general-purpose
computing.
 Multi-core processor: A multi-core processor is split into two or more sections
of activity, with each core carrying out instructions as if they were completely
distinct computers, although the sections are technically located together on a
single chip. For many computer programs, a multi-core processor provides
superior, high-performance output.
 Embedded processor: An embedded processor is a microprocessor expressly
engineered for use in embedded systems. Embedded systems are small and
designed to consume less power and be contained within the processor for
immediate access to data. Embedded processors include microprocessors and
microcontrollers.
 Dual-core processor: A dual-core processor is a multi-core processor
containing two microprocessors that act independently from each other.
 Quad-core processor: A quad-core processor is a multi-core processor that has
four microprocessors functioning independently.
 Octa-core: An octa-core processor is a multi-core processor that has eight
microprocessors functioning independently.
 Deca-core processor: A deca-core processor is an integrated circuit that has 10
cores on one die or per package.

 Memory Registers: A register is a temporary unit of memory in the

CPU. These are used to store the data which is directly used by the
processor. Registers can be of different sizes (16-bit, 32-bit, 64 bit and so
on) and each register inside the CPU has a specific function like storing
data, storing an instruction, storing address of a location in memory etc.
 The user registers can be used by an assembly language programmer for
storing operands, intermediate results etc. Accumulator (ACC) is the
main register in the ALU and contains one of the operands of an
operation to be performed in the ALU.
 Memory: Memory attached to the CPU is used for storage of data and
instructions and is called internal memory The internal memory is divided
into many storage locations, each of which can store data or instructions.
Each memory location is of the same size and has an address. With the
help of the address, the computer can read any memory location easily
without having to search the entire memory. when a program is executed,
it’s data is copied to the internal memory and is stored in the memory till
the end of the execution. The internal memory is also called the Primary
memory or Main memory. This memory is also called as RAM, i.e.
Random Access Memory. The time of access of data is independent of its
location in memory, therefore this memory is also called Random Access
memory (RAM). Read this for different types of RAMs
 Output Unit: The output unit consists of output devices that are attached
with the computer. It converts the binary data coming from CPU to
human understandable form. The common output devices are monitor,
printer, plotter etc.

Interconnection between Functional Components

A computer consists of input unit that takes input, a CPU that processes the
input and an output unit that produces output. All these devices communicate
with each other through a common bus. A bus is a transmission path, made of a
set of conducting wires over which data or information in the form of electric
signals, is passed from one component to another in a computer. The bus can be
of three types – Address bus, Data bus and Control Bus.
Following figure shows the connection of various functional components:
The address bus carries the address location of the data or instruction. The data
bus carries data from one component to another and the control bus carries the
control signals. The system bus is the common communication path that carries
signals to/from CPU, main memory and input/output devices. The input/output
devices communicate with the system bus through the controller circuit which
helps in managing various input/output devices attached to the computer.

o The Memory unit has a capacity of 4096 words, and each word contains
16 bits.
o The Data Register (DR) contains 16 bits which hold the
operand read from the memory location.
o The Memory Address Register (MAR) contains 12 bits which hold the
address for the memory location.
o The Program Counter (PC) also contains 12 bits which hold the address
of the next instruction to be read from memory after the current instruction is
executed.
o The Accumulator (AC) register is a general purpose processing register.
o The instruction read from memory is placed in the Instruction register
(IR).
o The Temporary Register (TR) is used for holding the temporary data
during the processing.
o The Input Registers (IR) holds the input characters given by the user.
o The Output Registers (OR) holds the output after processing the input
data

Instruction:
Instruction Cycle

A program residing in the memory unit of a computer consists of a sequence of

instructions. These instructions are executed by the processor by going through a
cycle for each instruction. In a basic computer, each instruction cycle consists of
the following phases:

1. Fetch instruction from memory.

2. Decode the instruction.
3. Read the effective address from memory.
4. Execute the instruction
Instruction Decoding Process

1. Fetch: The CPU retrieves an instruction from memory, typically from the instruction
cache or directly from main memory, based on the program counter (PC) which keeps track
of the address of the next instruction to be executed.

2. Decode: The fetched instruction is then decoded. During this phase, the CPU interprets the
binary instruction format to determine what operation needs to be performed and what
operands (data) are involved.

 Opcode Interpretation: The opcode (operation code) is extracted from the

instruction. The opcode specifies the operation to be performed (e.g., addition,
subtraction, load, store).
 Operand Extraction: The CPU extracts information about the operands from the
instruction. This might include register addresses, memory addresses, or immediate
values (constant values included in the instruction).
 Instruction Format: Different instructions have different formats. For example, R-
type instructions (register-based) might have fields for opcode, source registers,
destination registers, and function codes, while I-type instructions (immediate-based)
include an immediate value and a register address.

3. Execution: Once the instruction is decoded, the CPU executes it using the appropriate
execution units (e.g., arithmetic logic unit for arithmetic operations, floating-point unit for
floating-point operations).

4. Memory Access: If the instruction involves accessing memory (e.g., load or store), the
CPU performs the necessary memory operations.

5. Write-back: Finally, the results of the execution are written back to the appropriate
registers or memory locations.

Role of Microcode in Complex Instructions

Microcode plays a crucial role in the execution of complex instructions, particularly in CISC
(Complex Instruction Set Computer) architectures like x86. Here’s how it works:
1. Microcode Overview: Microcode is a layer of low-level instructions or firmware that
translates complex machine instructions into simpler, more fundamental operations that the
CPU's hardware can execute. It acts as an intermediary between the high-level machine
instructions and the CPU's internal execution units.

2. Complex Instructions: In CISC architectures, complex instructions can perform multiple

operations in a single instruction (e.g., string manipulation, complex arithmetic). The CPU
hardware may not be directly capable of executing these complex instructions in a single
step.

3. Micro-Operations: When a complex instruction is encountered, the CPU uses microcode

to break down this instruction into a sequence of simpler micro-operations. These micro-
operations are basic operations that the CPU can execute directly (e.g., read from memory,
perform an addition, write to a register).

4. Microcode Control Store: The microcode is stored in a special memory area known as
the microcode control store. This store contains the micro-operations required for each
complex instruction.

5. Execution Cycle: When the CPU decodes a complex instruction, it refers to the microcode
control store to retrieve the sequence of micro-operations needed. The CPU then executes
these micro-operations in sequence, effectively carrying out the complex instruction.

6. Flexibility and Upgrades: Microcode allows for flexibility and the ability to update or
enhance instruction execution without changing the hardware. This is useful for fixing bugs
or optimizing performance after the CPU has been manufactured.

Instruction Set Architecture (ISA)

The Instruction Set Architecture (ISA) is the part of the processor that is visible
to the programmer or compiler writer. The ISA serves as the boundary between
software and hardware. We will briefly describe the instruction sets found in
many of the microprocessors used today. The ISA of a processor can be
described using 5 categories:
Operand Storage in the CPU
Where are the operands kept other than in memory?
Number of explicit named operands
How many operands are named in a typical instruction.
Operand location
Can any ALU instruction operand be located in memory? Or must all operands
be kept internally in the CPU?
Operations
What operations are provided in the ISA.
Type and size of operands
What is the type and size of each operand and how is it specified?
Of all the above the most distinguishing factor is the first.
The 3 most common types of ISAs are:
1. Stack - The operands are implicitly on top of the stack.
2. Accumulator - One operand is implicitly the accumulator.
3. General Purpose Register (GPR) - All operands are explicitly
mentioned, they are either registers or memory locations.
Lets look at the assembly code of
C = A + B;
in all 3 architectures:

Stack Accumulator GPR

PUSH A LOAD A LOAD R1,A

PUSH B ADD B ADD R1,B

ADD STORE C STORE R1,C

POP C - -

Not all processors can be neatly tagged into one of the above categories. The
i8086 has many instructions that use implicit operands although it has a general
register set. The i8051 is another example, it has 4 banks of GPRs but most
instructions must have the A register as one of its operands.
Stack
Advantages: Simple Model of expression evaluation (reverse polish). Short
instructions.
Disadvantages: A stack can't be randomly accessed This makes it hard to
generate efficient code. The stack itself is accessed every operation and
becomes a bottleneck.
Accumulator
Advantages: Short instructions.
Disadvantages: The accumulator is only temporary storage so memory traffic
is the highest for this approach.
GPR
Advantages: Makes code generation easy. Data can be stored for long periods
in registers.
Disadvantages: All operands must be named leading to longer instructions.
Earlier CPUs were of the first 2 types but in the last 15 years all CPUs made are
GPR processors. The 2 major reasons are that registers are faster than memory,
the more data that can be kept internally in the CPU the faster the program will
run. The other reason is that registers are easier for a compiler to use.
Instruction and Instruction Sequencing
• A computer has a set of instructions that allows the user to formulate any data-
processing task. To carry out tasks, regardless of whether a computer has 100
instructions or 300 instructions, its instructions must be capable of performing
following basic operations:
• Data transfers between the memory and the processor registers.
• Arithmetic and logic operations on data.
• Program sequencing and control.
• I/O control.
Register Transfer Notation
• We have seen that in a computer system data transfer takes place between
processor registers and memory and between processor registers and I/O
system. These data transfers can be represented by standard notations given
below :
• Processor registers are represented by notations R0, R1, R2,... and so on.
The addresses of the memory locations are represented by names such as LOC,
PLACE, MEM, etc.
I/O registers are represented by names such as DATAIN, DATAOUT and so on.
• The contents of register or memory location are denoted by placing square
brackets around the name of the register or memory location.
• Let us see following examples for clear understanding.
Example: R2 ← [LOC]
• This expression states that the contents of memory location LOC are
transferred into the processor register R2.
Example: R3 ← [R1] + [R2]
• This expression states that the contents of processor registers R1and R2 are
added and the result is stored into the processor register R3.
Example: [LOC] ← [R1] - [R2]
• This expression states that the contents of the processor register R2 is
subtracted from processor register and the result is stored into the memory
location LOC.
• The notations explained above are commonly known as Register Transfer
Notations (RTN). In these notations, the data represented by the right-hand side
of the expression is transferred to the location specified by the left hand side of
the expression, overwriting the old contents of that location.
Assembly Language Notations
• Assembly language notations are the another type of notations used to
represent machine instructions and programs. These notations use assembly
language formats. However, register names, names of memory locations are
same as that of register notations.
• Let us see some examples.
Example: MOVE R2, R1
• This expression states that the contents of processor register R2 are transferred
to processor register R1. Thus the contents register R2 remain unchanged but
contents of register R1 are overwritten.
Example: ADD R1, R2, R3
• This expression states that the contents of processor registers R1 and R2 are
added and the result is stored in the register R3.
• It is important to note that the above expressions written in the assembly
language notations has three fields: Operation, source and destination having
their positions from left to right. This order is followed by many computer. But
there are many computers in which the order of source and destination operands
is reversed.
Basic Instruction Types
• Each instruction of the CPU contain specific information fields, which are
required to execute it. These information fields of instructions are called
elements of instruction. These are:
• Operation code : The operation code field in the instruction specifies the
operation to be performed. The operation is specified by binary code, hence the
name operation code or simply opcode.
Source / Destination operand: The source/destination operand field directly
specifies the source/destination operand for the instruction.
Source operand address: We know that the operation specified by the
instruction may require one or more operands. The source operand may be in
the CPU register or in the memory. Many times the instruction specifies the
address of the source operand so that operand(s) can be accessed and operated
by the CPU according to the instruction.
• Destination operand address: The operation executed by the CPU may
produce result. Most of the times the result is stored in one of the operand. Such
operand is known as destination operand. The instruction which produce result
specifies the destination operand address.
• Next instruction address: The next instruction address tells the CPU from
where to fetch the next instruction after completion of execution of current
instruction. For JUMP and BRANCH instructions the address of the next
instruction is specified within the instruction. However, for other instructions,
the next instruction to be fetched immediately follows the current instruction.
• Computers may have instructions of several different lengths containing
varying number of addresses. According to address reference there are three
address, two address, one address and zero address reference instructions. Let us
see examples of each of them.
Three address instructions : The three address instruction can be represented
symbolically as
ADD A, B, C
where A, B, C are the variables. These variable names are assigned to distinct
locations in the memory. In this instruction operands A and B are called source
operands and operand C is called destination operand and ADD is the operation
to be performed on the operands. Thus the general instruction format for three
address instruction is
Operation Source 1, Source 2, Destination
The number of bits required to represent such instruction include:
1. Bits required to specify the three memory addresses of the three operands. If
n-bits are required to specify one memory address, 3n bits are required to
specify three memory addresses.
2.Bits required to specify the operation.
Two address instructions : The two address instruction can be symbolically as
ADD A, B
This instruction adds the contents of variables A and B and stores the sum in
variable B destroying its previous contents. Here, operand A is source operand ;
however operand B serves as both source and destination operand. The general
instruction format for two address instruction is
Operation Source, Destination
To represent this instruction less number of bits are required as compared to
three address instruction. The number of bits required to represent two address
instruction include:
1. Bits required to specify the two memory addresses of the two operands, i.e.
2n bits.
2. Bits required to specify the operation.
One address instruction : The one address instruction can be represented
symbolicallyas
ADD B
This instruction adds the contents of variable A into the processor register called
accumulator and stores the sum back into the accumulator destroying the
previous contents of the accumulator. In this instruction the second operand is
assumed implicitly in a unique location accumulator. The general instruction
format for one address instruction is
Operation Source
Few more examples of one address instructions are :
LOAD A: This instruction copies the contents of memory location A into the
accumulator.
STORE B: This instruction copies the contents of accumulator into memory
location B.
In one address instruction, it is important to note that the operand specified in
the instruction can be either source operand or destination operand depending
on the instruction. For example, in LOAD A instruction, the operand specified
in the instruction is a source operand whereas the operand specified in the
STORE B instruction is a destination operand. Similarly, in one address
instruction the implied operand (accumulator) can be either source or
destination depending on the instruction.
Zero address instructions: In these instructions, the locations of all operands
are defined implicitly. Such instructions are found in machines that store
operands in a structure called a pushdown stack.
From above discussion we can easily understand that the instruction with only
one address will require less number of bits to represent it, and instruction with
three addresses will require more number of bits to represent it. Therefore, to
access entire instruction from the memory, the instruction with three addresses
requires more memory accesses while instruction with one address requires less
memory accesses. The speed of instruction execution is mainly depend on how
much memory accesses it requires for the execution. If memory accesses are
more, more time is required to execute the instruction. Therefore, the execution
time for three address instructions is more than the execution time for one
address instructions.
To have a less execution time we have to use instructions with minimum
memory accesses. For this instead of referring the operands from memory it is
advised to refer operands from processor registers. When machine level
language programs are generated by compilers from high-level languages, the
intelligent compilers see that the maximum references to the operands lie in the
processor registers.

Example : Write a program to evaluate the arithmetic statement Y = (A+B) *

(C+D) using three-address, two-address, one-address and zero-address
instructions. Solution :
Using three address instructions
ADD A, B,R1 ; R1←M[A] + M[B]
ADD C, D,R2 ; R2←M[C] + M[D]
MUL R1, R2,Y ; M[Y]← R1 * R2
Using two address instructions
MOV A, R1 ; R1←M[A]
ADD B, R1 ; R1←R1 + M[B]
MOV C, R2 ; R2←M[C]
ADD D, R2 ; R2←R2+ M[D]
MUL R2, R1 ; R1← R1 R2
MOV R1, Y ; [Y]← R1
Using one address instruction
LOAD A ; AC←M[A]
ADD B ; AC←AC+M[B]
STORE T ; M[T]←AC
LOAD C ; AC←M[C]
ADD D ; AC←AC+M[D]
MUL T ; AC←AC*M[T]
STORE Y ; M[Y]←AC
Using zero address instructions
PUSH A ; TOS←A
PUSH B ; TOS←B
ADD TOS←(A+B)
PUSH C ; TOS←C
PUSH D ; TOS←D
ADD ; TOS←(C+D)
MUL ; TOS←(C+D)*(A+B)
POP Y ; M[Y]←TOS

Example:Write the program to evaluate the expressionX =A [B+C(D+E)]/

F(G+H)using the zero address instructions and one address instructions.
Solution :Program using zero address instructions
PUSH D ; TOS←D
PUSH E ; TOS←E
ADD ; TOS←(D+E)
PUSH C ; TOS←C
MUL ; TOS←C×(D+E)
PUSH B ; TOS←B
ADD ; TOS←B+C×(D+E)
PUSH A ; TOS←A
MUL ; TOS←A[B+C×(D+E)]
PUSH G ; TOS←G
PUSH H ; TOS←H
ADD ; TOS←G+H
PUSHF ; TOS←F
MUL ; TOS←F× (G + H)
DIV ; TOS A[B+C× (D+ E)]/F× (G + H)
POPX ; M [X] ← TOS
Program using one address instructions
LOAD H ; AC← M[H]
ADD G ; AC←AC + M[G]
MUL F ; AC←AC*M[F]
STORE T ; M[T]←AC
LOAD D ; AC← M[D]
ADD E ; AC←AC + M[E]
ADD B ; AC←AC + M[B]
MUL A ; AC←AC* M[A]
DIV T ; AC←AC/M[T]
STORE Χ ; M[X] ← AC
Example : X = A×B+C×C
Explain how the above expression will be executed in one address, two address
and three address processors in an accumulator organization.
Solution :
Using one address instruction
LOAD A ; AC← M[A]
MUL B ; AC←AC* M[B]
STORE T ; M[T] ←AC
LOAD C ; AC← M[C]
MUL C ; AC←AC* M[C]
ADD T ; AC←AC + M[T]
STORE X ; M[X] ← AC
Using two address instructions
MOV A, R1 ; R1←M[A]
MUL B, R1 ; R1←R1*M[B]
MOV C, R2 ; R2←M[C]
MUL C, R2 ; R2←R2*M[C]
ADD R2, R1 ; R1←R1+R2
MOV R1, X ; M[T]←R1
Using three address instructions
MUL A, B, R1 ; R1←M[A]*M[B]
MUL C, C, R2 ; R2←M[C]+M[C]
Add R1, R1, X ; M[X]←R1*R2
Example : Give reasons to justify using, generally, i) Single address
instructions in 8-bit CPU's ii) Double address instruction in 16-bit CPU's iii)
Three address instructions in RISC systems. In each of these systems give
assembly language programs for performing the operation:
data at mem A + data at mem B→ mem C.
Show how the operation C = A + B can be implemented in a single accumulator
computer by i) Three-address instruction ii) Two-address instruction iii) One-
address instruction.
Solution: The instruction with only single address will require less number of
bits to represent it, and instruction with three address will require more number
of bits to represent it. That is, more address instruction requires more number of
bits to represent it. Generally, CPU should take less number of machine cycles
(preferably only one) to read the instruction. We know that, how many byte/s
CPU can access at a time depends on the data bus width. Therefore, to have less
number of machine cycles to read the instruction we generally use single
address instructions in 8-bit CPUs, double address instructions in 16-bit CPUs.
We know that, RISC systems use long instruction lengths therefore we generally
use three address instructions in RISC systems.
Operation:data at mem A + data at mem B → mem C
Assembly Language Programs for above operations are :

Single Address :
LOAD A ; Accumulator←[A]
ADD B ; Accumulator←Accumulator+[B]
STORE C ; C←Accumulator
Double Address :
MOVE B, C ; C←[B]
ADD A, C ; C←[A]+[C]
; i.e, C←[A]+[B]
Three Address :
ADD A, B, C ; C←[A]+[B]

Example : Write a program which evaluates the expression A×B+C×D in a

single accumulator processor. Assume that processor has load, store, multiply
and add instructions and all the values fit in the accumulator.
Solution :Program for single accumulator processor :
LOAD A ; AC←M[A]
MUL B ; AC←AC×M[B]
STORE X ; M[X]←AC
LOAD C ; AC←M[C]
MUL D ; AC←AC×M[D]
ADD X ; AC←AC+M[X]

Register Transfer Language (RTL)

In symbolic notation, it is used to describe the micro-operations transfer among
registers. It is a kind of intermediate representation (IR) that is very close to
assembly language, such as that which is used in a compiler. The term “Register
Transfer” can perform micro-operations and transfer the result of operation to
the same or other register.

Micro-operations:
The operation executed on the data store in registers are called micro-
operations. They are detailed low-level instructions used in some designs to
implement complex machine instructions.
Register Transfer :
The information transformed from one register to another register is represented
in symbolic form by replacement operator is called Register Transfer.
Replacement Operator :
In the statement, R2 <- R1, <- acts as a replacement operator. This statement
defines the transfer of content of register R1 into register R2.
There are various methods of RTL –

1. General way of representing a register is by the name of the register

enclosed in a rectangular box as shown in (a).
2. Register is numbered in a sequence of 0 to (n-1) as shown in (b).
3. The numbering of bits in a register can be marked on the top of the box as
shown in (c).
 4. A 16-bit register PC is divided into 2 parts- Bits (0 to 7) are assigned with
lower byte of 16-bit address and bits (8 to 15) are assigned with higher
bytes of 16-bit address as shown in (d).

Basic symbols of RTL :

Symbol Description Example

Letters and MAR, R1,

Denotes a Register
Numbers R2

R1(8-bit)
() Denotes a part of register
R1(0-7)

<- Denotes a transfer of information R2 <- R1

Specify two micro-operations of R1 <- R2

,
Register Transfer R2 <- R1

P : R2 <-
: Denotes conditional operations R1
if P=1
Symbol Description Example

Naming Denotes another name for an already

Ra := R1
Operator (:=) existing register/alias

Register Transfer Operations:

The operation performed on the data stored in the registers are referred to as
register transfer operations.
There are different types of register transfer operations:
1. Simple Transfer – R2 <- R1
The content of R1 are copied into R2 without affecting the content of R1. It is
an unconditional type of transfer operation.
2. Conditional Transfer –

It indicates that if P=1, then the content of R1 is transferred to R2. It is a

unidirectional operation.
3.Simultaneous Operations – If 2 or more operations are to occur
simultaneously then they are separated with comma (,).
If the control function P=1, then load the content of R1 into R2 and at the same
clock load the content of R2 into R1.
Addressing Modes
Addressing Modes– The term addressing modes refers to the way in which the
operand of an instruction is specified. The addressing mode specifies a rule for
interpreting or modifying the address field of the instruction before the operand
is actually executed.
Addressing modes for 8086 instructions are divided into two categories:
1) Addressing modes for data
2) Addressing modes for branch
The 8086 memory addressing modes provide flexible access to memory,
allowing you to easily access variables, arrays, records, pointers, and other
complex data types. The key to good assembly language programming is the
proper use of memory addressing modes.
An assembly language program instruction consists of two parts

The memory address of an operand consists of two components:

IMPORTANT TERMS
 Starting address of memory segment.
  Effective address or Offset: An offset is determined by adding any
combination of three address elements: displacement, base and index.
o Displacement: It is an 8 bit or 16-bit immediate value given in the
instruction.
o Base: Contents of base register, BX or BP.
o Index: Content of index register SI or DI.
According to different ways of specifying an operand by 8086 microprocessor,
different addressing modes are used by 8086.
Addressing modes used by 8086 microprocessors are discussed below:
 Implied mode: In implied addressing the operand is specified in the
instruction itself. In this mode the data is 8 bits or 16 bits long and data is
the part of instruction. Zero address instruction are designed with implied
addressing mode.

Example: CLC (used to reset Carry flag to 0)

 Immediate addressing mode (symbol #):In this mode data is present in
address field of instruction .Designed like one address instruction format.
Note:Limitation in the immediate mode is that the range of constants are
restricted by size of address field.

Example: MOV AL, 35H (move the data 35H into AL register)
 Register mode: In register addressing the operand is placed in one of 8
bit or 16 bit general purpose registers. The data is in the register that is
specified by the instruction.
Here one register reference is required to access the data.
Example: MOV AX,CX (move the contents of CX register to AX register)
 Register Indirect mode: In this addressing the operand’s offset is placed
in any one of the registers BX,BP,SI,DI as specified in the instruction.
The effective address of the data is in the base register or an index
register that is specified by the instruction.
Here two register reference is required to access the data.


The 8086 CPUs let you access memory indirectly through a register using
the register indirect addressing modes.
 MOV AX, [BX](move the contents of memory location s
addressed by the register BX to the register AX)
 Auto Indexed (increment mode): Effective address of the operand is the
contents of a register specified in the instruction. After accessing the
operand, the contents of this register are automatically incremented to
point to the next consecutive memory location.(R1)+.
Here one register reference, one memory reference and one ALU
operation is required to access the data.
Example:
 Add R1, (R2)+ // OR
 R1 = R1 +M[R2]
R2 = R2 + d
Useful for stepping through arrays in a loop. R2 – start of array d – size of an
element
 Auto indexed (decrement mode): Effective address of the operand is the
contents of a register specified in the instruction. Before accessing the
operand, the contents of this register are automatically decremented to
 point to the previous consecutive memory location. –(R1)
Here one register reference, one memory reference and one ALU
operation is required to access the data.
Example:
Add R1,-(R2) //OR
R2 = R2-d
R1 = R1 + M[R2]
Auto decrement mode is same as auto increment mode. Both can also be used
to implement a stack as push and pop . Auto increment and Auto decrement
modes are useful for implementing “Last-In-First-Out” data structures.
 Direct addressing/ Absolute addressing Mode (symbol [ ]): The
operand’s offset is given in the instruction as an 8 bit or 16 bit
displacement element. In this addressing mode the 16 bit effective
address of the data is the part of the instruction. Here only one memory
reference operation is required to access the data.

Example: ADD AL,[0301] //add the contents of offset address 0301 to AL

 Indirect addressing Mode (symbol @ or () ):In this mode address field
of instruction contains the address of effective address. Here two
references are required.1st reference to get effective address.2nd
reference to access the data.
Based on the availability of Effective address, Indirect mode is of two kind:
1. Register Indirect: In this mode effective address is in the register,
and corresponding register name will be maintained in the address
field of an instruction.
Here one register reference, one memory reference is required to
access the data.
2. Memory Indirect: In this mode effective address is in the memory,
and corresponding memory address will be maintained in the
address field of an instruction.
 Here two memory reference is required to access the data.
 Indexed addressing mode: The operand’s offset is the sum of the content
of an index register SI or DI and an 8 bit or 16-bit displacement.
Example: MOV AX, [SI +05]
 Based Indexed Addressing: The operand’s offset is sum of the content
of a base register BX or BP and an index register SI or DI.
Example: ADD AX, [BX+SI]
Based on Transfer of control, addressing modes are:
o PC relative addressing mode: PC relative addressing mode is
used to implement intra segment transfer of control, In this mode
effective address is obtained by adding displacement to PC.
o EA= PC + Address field value
PC= PC + Relative value.
o Base register addressing mode:Base register addressing mode is
used to implement inter segment transfer of control.In this mode
effective address is obtained by adding base register value to
address field value.
o EA= Base register + Address field value.
o PC= Base register + Relative value.
Note:
1. PC relative and based register both addressing modes are
suitable for program relocation at runtime.
2. Based register addressing mode is best suitable to write
position independent codes.
Advantages of Addressing Modes
 To give programmers to facilities such as Pointers, counters for
loop controls, indexing of data and program relocation.
 To reduce the number bits in the addressing field of the Instruction.

Instruction Set:
An instruction is a set of codes that the computer processor can understand. The
code is usually in 1s and 0s, or machine language. It contains instructions or
tasks that control the movement of bits and bytes within the processor.
Example of some instruction sets −
 ADD − Add two numbers together.
 JUMP − Jump to designated RAM address.
 LOAD − Load information from RAM to the CPU.
Types of Instruction Set
Generally, there are two types of instruction set used in computers.
Reduced Instruction set Computer (RISC)
A number of computer designers recommended that computers use fewer
instructions with simple constructs so that they can be executed much faster
within the CPU without having to use memory as often. This type of computer
is called a Reduced Instruction Set Computer.
The concept of RISC involves an attempt to reduce execution time by
simplifying the instruction set of computers.
Characteristics of RISC
The characteristics of RISC are as follows −
 Relatively few instructions.
 Relatively few addressing modes.
 Memory access limited to load and store instructions.
 All operations done within the register of the CPU.
 Single-cycle instruction execution.
 Fixed length, easily decoded instruction format.
 Hardwired rather than micro programmed control.
A characteristic of RISC processors’ ability is to execute one instruction per
clock cycle. This is done by overlapping the fetch, decode and execute phases of
two or three instructions by using a procedure referred as pipelining.
Complex Instruction Set Computer (CISC)
CISC is a computer where a single instruction can perform numerous low-level
operations like a load from memory and a store from memory, etc. The CISC
attempts to minimize the number of instructions per program but at the cost of
an increase in the number of cycles per instruction.
The design of an instruction set for a computer must take into consideration not
only machine language constructs but also the requirements imposed on the use
of high-level programming languages.
The goal of CISC is to attempt to provide a single machine instruction for each
statement that is written in a high-level language.
Characteristics of CISC
The characteristics of CISC are as follows −
 A large number of instructions typically from 100 to 250 instructions.
 Some instructions that perform specialized tasks and are used
infrequently.
 A large variety of addressing modes- typically from 5 to 20 different
modes.
 Variable length instruction formats.
 Instructions that manipulate operands in memory.
Example
For performing an ADD operation, CISC will execute a single ADD command
which will execute all the required load and store operations.
RISC will execute each operation for loading data from memory, adding values
and storing data back to memory using different low-level instructions.
Outlining instruction sets of some common CPUs.
Types of instruction set
Many popular and useful instruction sets are important and useful in computer
science. These sets of instructions have their advantages as well as usages. Here
are the types of instruction sets:
1. Reduced instruction set computer (RISC)
RISC has only a few cycles per instruction. It has a simpler form than a
complex set of instructions. RISC is also used in many supercomputers. For
example, it uses a summit, which is a supercomputer. It was the world’s fastest
supercomputer as per data in 2018.
2. Minimal instruction set computers (MISC)
A few codes and a set of instructions are basic for any processor. They also
include sub-codes. As a result, they are smaller and faster. A disadvantage of
MISC is that it has more sequential dependencies.
3. Complex instruction set computer (CISC)
CISC is a set of instructions with a few instructions per program. A CISC has
fewer instructions than RISC.
4. Explicitly parallel instruction computing (EPIC)
This is an instruction set that permits microprocessors that help to execute
instructions in parallel software. EPIC intends to give a simpler performance.
5. Very long instruction word (VLIW)
VLIW exploits parallelism at the instruction level. By this set of instructions,
instructions are processed in sequence only in the CPU. This set of instructions
improves the performance of the CPU.

6. Zero instruction set computer (ZISC)

The instructions that do not include microinstructions are known as ZISC. They
are based on the pattern matching and can be compared to networks of synapses
and neurons.
7. One instruction set computer (OISC)
The OISC set of instructions uses only one instruction for a machine language.
This set of instructions is used to teach computer architecture and to compute
structural computing research.
Stacks
A stack is a device used to store a set of instructions or information such that the
item stored at last is the first item to pick. A stack is a memory unit in digital
computers responsible for counting only. There are two types of stacks. These
two types are register stack and memory stack.
Register stacks are built using registers. A memory stack forms a logical part of
the memory kept under the stack. Stacks are used to evaluate as well as
backtrack algorithms.
An advantage of stacks is that they are short and simpler instructions used to
evaluate. However, they can not be accessed randomly. It is hard to access them,
resulting in difficulty generating their code.
Accumulator
A kind of register included in any CPU is known as an accumulator. It serves as
a location for temporary storage for intermediate values. These intermediate
values are a part of calculations done in mathematical and logical calculations.
The set of instructions is short in accumulators. It is just temporary storage,
which makes traffic memory high for its approach.
General-purpose register
General-purpose registers are used as temporary data storage. They are stored
temporarily in microprocessors. They are used to store 8-bit data and are
represented by six figures. These figures are B, C, D, H, and L. They can also
form 16-bit operations. This can be done by combining the pairs of general pair
registers such as HL, DE, and BC. They are short instructions. A disadvantage
of the general-purpose register is that all its operands should be named. This
results in a longer set of instructions. They are easy to use with computer
processors.

Conclusion
An instruction set holds all the commands and codes. These instructions are
understood by a CPU as they control the CPU. When any instruction set is
designed, the requirements of the processor are prioritised. Similarly, stack,
accumulations, and GPR are also types of simpler instructions.