Introduction to VHDL

 Hardware Description Language (HDL)

 High-level language to model, simulate, and synthesize digital
circuits and systems.

 History
 1980: US Department of Defense had launched Very High
Speed Integrated Circuit program (VHSIC) project
 1986: It was transferred to the IEEE for standardization
 1987: Institute of Electrical and Electronics Engineers approves
IEEE Standard 1076 (VHDL’87)
 1993: VHDL language was revised and updated

 Verilog is the other major HDL

 Syntax similar to C language

 VHDL is mostly used for FPGA design

 Many tools accept both Verilog and VHDL

 Architecture of Digital Systems
 A system is defined by its
behaviour
 relates inputs to outputs
 combinational
• function table (truth
digital table)
Inputs Outputs • Boolean expressions
 sequential
system • algorithmic rules
 Example
Library ieee; Library ieee;
Use ieee.std_logic_1164.all; Use ieee.std_logic_1164.all;
entity identifier is entity and2 is
port ( a, b : in std_logic;
port ( port_interface_list );
y : out std_logic);
end identifier ;
end and2;
architecture identifier of entity_name is
architecture basic of and2 is
[Architecture –item-declarations]
begin
begin
y <= a and b;
[statements];
end basic;
end identifier ;
 The library clause declares the design library IEEE.
 The use clause imports all the declarations within the package
std_logic_1164 into the entity declaration including the type
declarations for std_logic and std_logic_vector.
 Type std_logic has nine different values - ‘U’ – Uninitialized; ‘X’ – Forcing
unknown; ‘0’ – Forcing 0; ‘1’ – Forcing 1; ‘Z’ – High impedance; ‘W’ –
Weak unknown; ‘L’ – Weak 0; ‘H’ – Weak 1; ‘-’ – Don’t care
VHDL Entities and Architecture

Package

Generic Entity Ports

Architecture
Architecture Architecture
(structural)

Concurrent Concurrent Component

Process
statement statement instantiation

Sequential
statement
Modeling styles-Example
 Dataflow modeling:  Behavioral modeling:
library ieee; architecture behav of ha_df is
Use ieee.std_logic_1164.all; Begin
entity ha_df is Process (a,b)
port(a, b : in std_logic; c, s : out Begin
std_logic); If (a= ‘0’ and b= ’0’) then
end ha_df ; c<= ‘0’;
architecture df of ha_df is s<= ‘0’;
begin elsIf (a= ‘0’ and b= ’1’) then
c <= a and b; c<= ‘0’;
s <= a xor b ; s<= ‘1’;
end df; elsIf (a= ‘1’ and b= ’0’) then
c<= ‘0’;
s<= ‘1’;
else
c<= ‘1’;
s<= ‘0’;
end if;
End process;
End behave;
 Modeling styles-Example
 Structural Modeling AND_2:
architecture arch of ha_df is library ieee;
component xor_2 use ieee.std_logic_1164.all;
port(m,n : in std_logic; o : out std_logic); entity and_2 is
end component; port(x,y : in std_logic; z : out std_logic);
component and_2 end entity;
port(x,y : in std_logic; z : out std_logic); architecture arch_and2 of and_2 is
end component; begin
begin z <= x and y;
X1: xor_2 port map (a, b, s); end arch_and2;
A1: and_2 port map (a, b, c);
end arch;
XOR_2 :
library ieee;
use ieee.std_logic_1164.all;
entity xor_2 is
port(m,n : in std_logic; o : out std_logic);
end entity;
architecture arch_xor2 of xor_2 is
begin
o <= m xor n;
end arch_xor2;

7
Terminology
 Dataflow modeling
 Describes the functionality of a component/system as a set of
concurrent signal assignment statements
 Concurrent signal assignment statements are used to express
dataflow modeling
 Behavioral modeling
 Describes the functionality of a component/system as a set of
sequential statements
 Process statements are used to express sequential behavior
modeling.
 Structural modeling
 A component is described by the interconnection of lower level
components/primitives
 Component instantiations are used to express structural
modeling.
 Synthesis:
 Translating the HDL code into a circuit, which is then optimized
 Entity Declaration
 Provides complete interface for circuit
 It defines I/O for connection and verification
 Comments in a description must be preceded by two consecutive
hyphens (--). BLACK_BOX
syntax:
entity identifier is rst
q[7:0]
port ( port_interface_list ); d[7:0]
co
end identifier ; clk
-- eight bit comparator
Mode Entity name
entity compare is
port (A, B : in bit_vector ( 7 downto 0 );
EQ : out bit );
end compare;
A[7:0] EQ
List of inputs B[7:0]
compare
and outputs Port types

type bit is (‘0’, ‘1’); -- bit’left =‘0’

Basic VHDL Language Elements-Ports
 Used to define inputs and outputs of an entity
 The means by which information is fed into and out of the circuit
 Each port defined by:
 Name: specifies name of the ports

 Direction (mode): specifies whether information flows into or out

from the entity through the port
 Data type: specifies the kind of information that can be
communicated
 All these ports are signals and they are common to all the design
units those are associated with that entity declaration.

P P
O O
R ENTITY R
T T
S S
Port Modes
 Describes direction of data transfer
 Port in : Data flows only into circuit (never be on the left to the
signal assignment)
 Port out : Data flows only out of circuit (never be on the right to
the signal assignment)
 Port buffer : For internal feedback or driver. NOT bidirectional. It
is basically an external output but can be used as an internal
input.
 Port inout : Bidirectional signal. Can be used as external input or
external output.
In(A) (X)Out

(Y)Buffer
In(B)
(Z)Inout
In(C)
 Architecture Body
 Describes how circuit is implemented
 Describes the internal operation/view of the model
 Every entity must have at least one architecture body
syntax:
architecture identifier of entity_name is
[Architecture –item-declarations] A[7:0]
compare1 EQ
begin
[statements]; B[7:0]
Declaration Entity
end identifier ; name
--eight bit comparator name
architecture compare1 of compare is
begin
Functional EQ  ‘1’ when ( A = B ) else ‘0’;
description end compare1; Assignment
operator
The ports or generics declared in the entity declarations are available for use
within the architecture body due to association of the entity with the architecture
body.
Data Objects
 They hold values of a specific type.
 They must be declared before they are used.
 They belong to one of four classes:
 Constants : hold values that cannot be changed within the design
description.
 Signals: can represent wires, can interconnect components.
 Variables: used only in processes and subprograms (functions and
procedures) and therefore be declared in the declarative region of a
process or sub program.
 An object declaration is used to declare an object, its type, and its
class, and optionally assign it a value.
 e.g. signal cout: bit_vector (3 downto 0);
variable result: std_logic := ‘0’;
constant width : integer := 8;
 Implementation of function

f(A,B,C) = AB’C+ABC’+ABC

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY function IS
PORT (A, B, C: IN STD_LOGIC;F: OUT STD_LOGIC);
END function;
ARCHITECTURE Dataflow OF function IS
SIGNAL term_1, term_2, term_3: STD_LOGIC;
BEGIN
term_1 <= A AND (NOT B) AND C;
term_2 <= A AND B AND (NOT C);
term_3 <= A AND B AND C;
F <= term_1 OR term_2 OR term_3;
END Dataflow;
 VHDL Data Types
Every data object in VHDL can hold a value that belongs to a set
of values. This set of values is specified by using a type declaration. A type
is a name that has associated with it a set of values and a set of
operations.
VHDL is a strongly typed language (you cannot assign a signal of one type
to the signal of another type)

Values belonging to these types

appear in a sequential order.
 Enumerated type
 Defines a type that has a set of user-defined values consisting of identifiers
and character literals.
 The values are called enumeration literals.
 Examples:
Type MVL is ('U','0','1','Z’);
type MICRO_OP is (LOAD, STORE, ADD, SUB, MUL, DIV);

 Some object declarations using these types are

signal CONTROL_A: MVL;
signal CLOCK: MVL range '0' to '1'; -- Implicit subtype declaration.
variable IC: MICRO_OP := STORE; -- STORE is the initial value for IC.

16
Predefined enumeration types
 CHARACTER: 191 characters of the ISO 8-bit coded character set
Examples: 'A', '_', '" (the single quote character itself), '3' (the
character literal 3). These values are called character literals and
are always written between two single quotes (' ').

 BIT: It has the literals '0' and ‘1‘.

 BOOLEAN: It has the literals FALSE and TRUE.

17
Integer type
 It defines a type whose set of values fall within a specified integer
range.
 It must at least cover the range -(2^ 31 - 1) to +(2^31 - 1).
 Examples:
type INDEX is range 0 to 15;
type MY_WORD is range 4 to 6;

 Some object declarations using these types are

constant MUX_ADDRESS: INDEX := 5;

signal DATA_BUS: MY_WORD;

 Integer literals
56349, 6E2, 0, 98_71_28

18
Real/Floating point type
 It has a set of values in a given range of real numbers.
 It must at least cover the range -1.OE38 to +1.OE38 and it must
allow for at least six decimal digits of precision.
 Examples:
type REAL_DATA is range 0.0 to 31.9;

 An example of an object declaration is

type REAL_DATA is range 0.0 to 31.9;
variable LENGTH: REAL_DATA range 0.0 to 15.9;
variable LI, L2, L3: REAL_DATA range 0.0 to 15.9;
 Floating point literals:
16.26, 0.0, 0.002, 3_1.4_2, 62.3E-2,5.0E+2

19
Physical type
 It contains values that represent measurement of some physical
quantity, like time, length, voltage, and current.
 Values of this type are expressed as integer multiples of a base
unit.
 Predefined physical type is TIME; predefined physical subtype is
delay_length.
 Physical literals are written as an integer literal followed by the unit
name.
 Example:
type CURRENT is range 0 to 1E-9
units
nA; -- (base unit) nano-ampere
uA = 1000 nA; -- micro-ampere
mA = 1000 μA; --milli-ampere
Amp = 1000 mA; -- ampere
end units;

20
Composite type: Array type
 It represents collection of values all belonging to a single type
 An element of a composite type could have a value belonging to
either a scalar type, a composite type, or an access type.

 Examples:
type ADDRESS_WORD is array (0 to 63) of BIT;
type DATA_WORD is array (7 downto 0) of MVL; --Type MVL is
('U','0','1','Z’);
type ROM is array (0 to 125) of DATA_WORD;
Examples of object declarations using these types are
signal ADDRESS_BUS: ADDRESS_WORD;
variable DECODER: ROM
 DECODER(5,2) refers to the value of the element at the 2nd
column and 5th row of the two-dimensional object.

21
Record type
 It represents a collection of values that may belong to same or different
types.
Example:
type PIN_TYPE is range 0 to 10;
type MODULE is
record
SIZE: INTEGER range 20 to 200;
CRITICAL_DLY: TIME;
NO_INPUTS: PIN_TYPE:
NO_OUTPUTS: PIN_TYPE;
end record;

Object declaration:
variable NAND_COMP: MODULE;
NAND_COMP := (50, 20 ns, 3,2);
NAND_COMP.NO_INPUTS := 2:

22
VHDL Operators
 Logical: For BIT and BOOLEAN or 1-D array of BIT and Boolean
 AND, NAND
 OR, NOR
 XOR, XNOR
 NOT
The result of a logical operation has the same type as its
operands.
 Relational: Result is always of type BOOLEAN
 = (equal to)
 /= (not equal to)
 < (less than)
 <= (less than or equal to)
 > (greater than)
 >= (greater than or equal to)
The = and /= operators are predefined on any type. <, <=, > and
>= operators are predefined on any scalar type or the bit_vector
type. 23
Semantics: Sequential & Concurrent Statements
 There are two types of statements
 Sequential

• Statements within a process

• Evaluated sequentially during simulation
 Concurrent

• Statements outside of a process

• Processes are evaluated concurrently
Concurrent and Sequential Statements
 Concurrent statements include:
 Concurrent signal assignment statement
x <= (a AND (NOT sel1)) OR (b AND sel1);
g <= NOT (y AND sel2);
 Sequential-statements are ->
wait-statement
if-statement
case-statement
loop-statement
null-statement
exit-statement
next-statement
assertion-statement
procedure-call-statement
return-statement.
 Syntax: [process-label: ] process [( sensitivity-list ) ]
[process-item-declarations]
begin
sequential-statements;
end process [ process-label];
 Items declared in the item declarations part are available for use only
within the process.
• VHDL code for Half Adder
entity ha_df is
port(a, b : in bit; c, s : out Bit);
end ha_df ;
architecture df of ha_df is
begin
c <= a and b;
s <= a xor b ;
end df;
• VHDL code for Full Adder
entity fa is
port( x,y,z :in bit; s,c : out bit);
end fa;
architecture df of fa is
begin
s <= x xor y xor z;
c <= (x and y) or (y and z) or (z and x);
end df;
REFERENCES

(i) Bhasker, J. A. (1999) VHDL primer. 3rd edn. New

Delhi: Pearson Ed.
(ii) Sjoholm, S. and Lindh, L. (2008) VHDL for
Designers. 3rd edn. Morgan Kaufmann
(iii) Perry, D. L. (2002) VHDL programming by
examples. 4th Edn. New Delhi: Tata McGraw Hill.