A Reconfigurable Dual-Mode Tracking SAR ADC

without Analog Subtraction

Mehdi Safarpour∗ , Reza Inanlou † , Olli Silvén ∗ , Timo Rahkonen∗ and Omid Shoaei †
∗ Faculty of Electrical Engineering and Computer Science, University of Oulu, Oulu, Finland
† School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran

Abstract—In this contribution, it is proposes to limit the be reconfigured to various digitization schemes.
quantization search space of a successive approximation analog- Previous designs generally attempt to reduce conversion cy-
arXiv:1905.08895v2 [eess.SP] 28 May 2019

to-digital converter through an analytic derivation of maximum cles by quantizing only sample-to-sample variation which
possible sample-to-sample variation. The presented example
design of the proposed ADC is an 8-bit 1MS/s ADC with necessitate some form of analog subtraction, e.g. authors of
SAR logic customized to incorporate this priori information [6] propose a modification to the Digital-to-Analog-Convertor
while no modification has been required to the analog circuitry. (DAC) in order to derive sample-to-sample variations, but this
In comparison to conventional SAR conversion, the proposed modification prevents employment of bottom plate sampling
tracking approach yields significant reduction in total power (and consequently facing charge injection problem). The pro-
consumption in oversampling mode. The power savings are due
to the reduced number of SAR cycles, and voltage variation posed method in this work uses prior knowledge to limit
minimization across DAC capacitors. The design is reconfigurable quantization search space, hence reducing number of cycles
both to conventional SAR sampling and the proposed tracking required to resolve each sample. In this contribution, contrary
scheme. The approach is attractive for SAR ADCs embedded in to previous works, e.g. Noise Shaping SAR, the idea is not
very low power micro-controllers. to use the ADC to digitize the difference between the current
Index Terms—Analog-to-digital converter, SAR ADC, Over-
sampling. sample and previous converted value, but instead track the
signal through adjust DAC value. In other words. the current
conversion is held and is used to resolved the next sample,
I. I NTRODUCTION
through minor modifications.
Most Micro-Controller Units (MCU) incorporate an
Analog-to-Digital Converter (ADC) [1]. Thanks to their high II. T HEORETICAL C ONCEPT
power efficiency and flexible sampling rate, Successive-
The purpose of the following is to derive an analytic
Approximation-Register (SAR) ADCs are popular with low
expression for determining the maximum change between two
power MCUs, but their bit precision tends to be limited
consecutive samples, when the input signal has been low
to 12 bits due to linearity issues. Consequently, the MCU
pass filtered and is oversampled by a factor of M . ADCs
vendors provide developers, ADCs with oversampling option
typically have a front-end anti-aliasing filter before quantiza-
to improve the resolution [2]. In its simplest form, the res-
tion and it guarantees the input signal to be low-passed. The
olution enhancement is achieved through oversampling the
fastest changing band-limited signal would be a sinusoid with
signal by factor M (over Nyquist-rate), followed by, e.g.
maximum frequency and full dynamic range. Let us assume
Hogenauer structure and simple FIR filters [3]. However, the
the Nyquist-rate sampling frequency to be fs , oversampling
flip-side can be a substantial increase of power dissipation
factor M , and oversampling frequency fos . When the highest
[4]. Moreover, in sensor readout interfaces, reconfigurable
frequency component in the signal is fmax , the sampling rate
ADCs that provide different sampling and resolution options,
fs must be more than 2fmax , but for our purpose in the
are especially useful, where the ADC is time-multiplexed to
calculations, one can safely be assume fs = 2fmax , leading
digitize different types of input signal with different bandwidth
to over-sampling rate of fos = 2M fmax . The signal to be
and resolution requirements [5].
sampled can therefore be expressed as,
A modified oversampling scheme that reduces the power
dissipation of the quantization process through cutting num- x(t) = Acos(2πfmax t + φ) (1)
ber of cycles for each conversion during oversampling, is
proposed. The method is based on the observation that in where A is the amplitude, t is time and φ is the phase. The
oversampling mode, maximum sample-to-sample variation is oversampled signal is
constant and deterministic. In an attempt to take advantage πn
of this observation, a tracking ADC is introduced to save x[n] = Acos( + φ) (2)
M
power through constraining quantization levels that need to be
resolved. The scheme can be an alternative for the commonly and the difference between two adjacent samples is defined
used oversampling techniques in conventional ADCs. Our by,
design also supports regular Nyquist-rate sampling and can D[n] = x[n] − x[n − 1] (3)
To find the maximum value for the difference (3) in the
oversampled signal, the first derivative of the difference is set
equal to zero, then using backward differentiation one can
solve for n:
∂D (D[n] − D[n − 1])
= (4)
∂n 1
∂D πn π(n − 1) π(n − 2)
= Acos( ) − 2Acos( ) + Acos( )
∂n M M M
(5)
Setting the above equal to zero ( ∂D
∂n = 0) gives,
πn π(n − 1) π(n − 2)
Acos( +φ)−2Acos( +φ)+Acos( +φ) = 0
M M M
(6)
To simplify the notation, let x = πn
M and b = π
M , and using
angle sum and difference identities, we get
Acos(x + φ) − 2Acos(x + φ)cos(b) − 2Asin(x + φ)(b)
+Acos(x + φ)(2b) + Asin(x + φ)(2b) = 0
(7) Fig. 1. Digital logic for realization of the proposed dual-mode SAR ADC.

Let assume M  π (which regularly is the case, in our

experiments M > 16), b ≈ 0 and using Small Angle circuit. The details and considerations of the unit capacitor in
Approximation the following is resulted, the DAC capacitor array as well as the comparator are similar
Acos(x + φ) − 2Acos(x + φ)(1 − b2 /2) − 2Asin(x + φ)(b) to [7]; but the unit capacitor is 15fF in this design. Also, the
arithmetic unit is composed of an 8-bit adder/subtract, an 8-
+Acos(x + φ)(1 − 2b2 ) + Asin(x + φ)(2b) = 0
bit delay cell and few digital logic gates for control and mode
(8)
selection. Based on the mode pin status, the ADC operates in
Most of the terms in the above expression cancel out each regular mode or oversampling mode. The functionality of the
other, leaving proposed ADC is described in the next subsection.
− (b2 )Acos(x + φ) = 0 (9)
B. Sampling Modes
from which solving for x yields
As explained earlier, the proposed ADC digitizes the analog
kπ M φ value in successive approximation manner, but instead of
x= − ,k ∈ Z (10)
2 π conventional logic, its range and steps are adjusted based on
Therefore, Dmax for n = kπ
− Mφ
becomes mode of operation. Algorithm 1 and Algorithm 2, present
2 π
detailed procedural description of each mode.
Dmax = ±Asin(π/M ) (11) In regular SAR mode similar to conventional logic, the DAC
Small angle approximation can be applied again and hence the value is set to zero at the end of each conversion but in tracking
maximum range is approximated as ± Aπ mode the DAC value is maintained. For regular SAR mode
M . Having the current
sample x(nTs ) and its quantized equivalent, the next sample the user must set the initial value of the shift registers to
would be in the range limited to ± Aπ “1000000” (for 8-bit ADC). For proposed tracking mode the
M ,
initial value depends on the calculated maximum sample to
Aπ sample variation:
x[(n + 1)Ts ] = x[nTs ] ± (12)
M
Dmax (DynamicRange)
Hence, the search space of the ADC can safely be limited IntitialV alue ≥ d e
to the range of ± Aπ (2N − 1)
M . This can be exploited to reduce power π
(13)
consumption of ADCs embedded in MCUs. 2Asin( M ) N π
=d (2 − 1)e = dsin( )(2N − 1)e
2A M
III. P ROPOSED ADC
Where N is number of bits. For example, in case of an 8-
A. General Description bit ADC operating with oversampling rate of 64 the shift
Figure 1 shows the conceptual diagram of the proposed register initialization value is “00001000”. This means, in this
ADC. As shown, the main building blocks of the ADC example, only five cycles are required for conversion of each
consist of an 8-bit shift register, Z1 and Z2 delay generation sample. The use of fewer cycles results in saving of energy
unit, arithmetic unit and a successive approximation converter required for each conversion. In addition, for most of code
(ADC core). The ADC core itself is implemented by a binary transitions the DAC does not need to be reset, which results in
weighted capacitor array that perform digital to analog con- avoiding the discharge of MSB capacitors. This leads to extra
version (DAC), a comparator and a passive sample-and-hold power savings at DAC. Operation of the scheme is illustrated
in Fig. 1 where the ADC is configured to function in regular Algorithm 2: Tracking mode algorithm
SAR mode or in the proposed tracking SAR mode via setting Result: Digital version, B, of the input analog sample
the Mode bit ‘1’ or ‘0’, respectively. In Fig. 1, Algorithm 1 Initialization step is as described in Algorithm 1 but for
and Algorithm 2, B represents digital output, B(i−1) denotes tracking mode, IR ← dsin(π/M )(2N − 1)e
digital output from previous cycle, the Mode bit is set by user Step 1. Take sample, S/H ← V(in)
while RESET, Z1 and Z2 are generated within the circuit. StepRegister ← IR
The RESET signal is used to initialize the step shift register (note that the DAC value and the output, B, are held
in both regular mode and in tracking mode, the signal from from previous conversion)
Z2 (multiplexed to RESET) is used to delay the initialization B ← B(i-1)+StepRegister
of the shift register by an additional clock cycle to let the Step 2. if StepRegister 6= 0 then
comparator to compare the current analog sample with the if V(in)>DAC(B) then
quantized version of the previous sample. The design enables B ← B(i-1)+ StepRegister;
exploitation of sample to sample adjacency in oversampling else
mode, while maintaining the option to use the ADC also as a B ← B(i-1)-StepRegister;
regular SAR. In both operation modes the delay flip-flop Z1 end
is used to indicate end of conversion. jump to Step.2;
end
Algorithm 1: SAR ADC regular mode algorithm if not(V(in)>DAC(B)) then
Result: Digital version, B, of the input analog sample B ← B(i-1)-1;
Initialization Register (IR) is set by user; Mode is end
selected by user; B is binary output; DAC(B) is analog
equivalent of B; IR ← “10000000”
TABLE I
Step 1. Take sample, S/H ← V(in) P ROPERTIES SUMMARY OF THE SAMPLE SAR ADC.
Step 2. StepRegister ← IR
B(i-1)← “00000000” Specification Value
Technology 90nm CMOS
B ← B(i-1)+StepRegister Resolution 8
Step 3. if StepRegister 6= 0 then ENOB* 7.4
StepRegister ← StepRegister  1; Supply Voltage 1V
Max. Sampling Rate 1 MS/s
if V(in)>DAC(B) then Power Consumption 12.9 µW
B ← B(i-1)+ StepRegister; *Regualar mode, Nyquist rate.
else
B ← B(i-1)-StepRegister;
end IV. R ESULTS AND D ISCUSSION
jump to Step.3;
end Initially, a behavioral simulation using MATLAB was car-
if not(V(in)>DAC(B)) then ried out to verify the functionality of the proposed ADC.
B ← B(i-1)-1; Subsequently, a transistor level circuit simulation in 90 nm
end CMOS process with an HSPICE model was carried out to
investigate the power consumption in both regular and pro-
posed oversampling mode with different oversampling ratios.
In the regular mode the quantized value of a previous sample Specifications of the design is presented in Table I. The power
is ignored, while in the tracking mode the previous value consumption for different oversampling ratios were estimated
on the DAC is held. In Fig. 1 blocks AND1, NOT1 and through simulations. The summaries of the findings are in
AND2 are used for this selection. The control signals are Table II which shows energy consumption per sample reduces
automatically generated using data in the shift register. At each proportionally to the oversampling ratio. Figure 2 shows the
clock cycle, data in the shift register is moved one bit to the power spectral density of the proposed ADC architecture in
right, generating a step value to be added or subtracted. An tracking mode for OSR = 64.
8-bit asynchronous ripple-carry adder–subtracter is connected The proposed architecture serves as an example on ex-
to the output of shift register (A1 being the MSB), and one ploiting sample-to-sample variation without having to carry
clock cycle delayed version of quantized output, B(i−1). The out analog subtraction. Although similar ideas have been
comparator’s output controls the addition/subtraction mode investigated before [6][8], to the best knowledge of authors,
selection of the adder-subtracter. In addition, since in the last general approach of the previous works was to quantize the
cycle all bits in the shift register have already been shifted out, analog difference of two consecutive samples while in this
Z1 is used as LSB (AND3 and OR1). Note, for applications work the search space is adjusted digitally. Analog subtrac-
that only require implementation of the tracking mode the tion requires extra analog circuitry, which introduces more
circuit can significantly be simplified. design constraints. In addition, the proposed approach can
 TABLE III
C OMPARISON WITH THE RELATED WORKS

Ref. [9] Ref. [10] Ref. [3] This Work

(Sim.) (Chip) (Chip) (Sim.)
Bandwidth 60 KHz 20 MHz 11 MHz 2-500 KHz
ENOB 9.55 9.8 10 7.4
Power 2.97 µW 1.8mW 806 µW 13 µW
Technology 180 nm 180 nm 65 nm 90 nm
FoM 36.9 f 70.2 f 35.8 f 76.9 f
Architecture SAR Reconfigurable NS-SAR Tracking SAR
P ower
FOM B.W ×2EN OB

supports both regular SAR and proposed tracking mode of

operations. The method is useful in multi-channel ADCs used
in embedded micro-controllers.
ACKNOWLEDGMENT
Fig. 2. Power Spectrum of the ADC in proposed oversampling mode with
oversampling ratio of 64 (SFDR=46.3dB) The support of Academy of Finland for project ICONICAL
(grant 313467) and 6Genesis Flagship (grant 318927) is grate-
TABLE II fully acknowledged.
E STIMATED P OWER C ONSUMPTION W ITH R ESPECT T O OSR S
R EFERENCES
OS Mode OSR* Variation Initial Cycles pW/S
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V. C ONCLUSION
Taking advantage of how sample-to-sample variation is
limited can provide for substantial energy efficiency improve-
ments for SAR ADCs. Our contribution shows how this can
be accomplished by modifying only the digital parts of the
conversion logic, and minimum restriction is imposed on
analog circuits. The digital section can enjoy power reduc-
tion techniques such as voltage scaling without having to
compromise circuit functionality. The presented digital logic