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VLSI

The document outlines a 12-month roadmap for BTech Electrical Engineering students focusing on VLSI and embedded systems after their first year. It details a structured learning path, including fundamental topics, projects, and tools for each quarter, culminating in integration and resume-level work. Additional bonus activities encourage participation in workshops and contributions to open-source projects.

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krishnapatil12.k4
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1 views3 pages

VLSI

The document outlines a 12-month roadmap for BTech Electrical Engineering students focusing on VLSI and embedded systems after their first year. It details a structured learning path, including fundamental topics, projects, and tools for each quarter, culminating in integration and resume-level work. Additional bonus activities encourage participation in workshops and contributions to open-source projects.

Uploaded by

krishnapatil12.k4
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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12-Month Roadmap: VLSI + Embedded

Systems
For a BTech EE Student (Post-1st Year)

Overview
This roadmap is designed for a BTech Electrical Engineering student who has completed
the first year and has:

• Exposure to Verilog and digital systems

• Experience with Python, C, AVR-GCC, and assembly programming

• Interest in VLSI and embedded systems

• A desire to grow into light coding without a software-heavy focus

1 Months 1–3: Strengthen Fundamentals


Topics to Learn
• CMOS Logic (inverters, delays)

• FSM Design in Verilog

• Python scripting basics (file I/O, plotting)

• AVR basics: GPIO, UART, C and Assembly

Projects
• 8-bit ALU in Verilog with Python-based testbench

• FSM-based Traffic Light Controller (Verilog + GTKWave)

• AVR UART and GPIO control

• Python script to generate Verilog test vectors and parse outputs

Tools
ModelSim / Vivado, GTKWave, Python (matplotlib), AVR-GCC / PlatformIO

1
2 Months 4–6: RTL to FPGA + Embedded Com-
munication
Topics to Learn
• FPGA flow: RTL to Bitstream
• UART protocol
• Memory-mapped I/O
• TCL and basic scripting

Projects
• Stopwatch or Calculator on FPGA
• Python GUI to control Verilog module via UART
• AVR → Verilog peripheral communication
• Automate build/simulations using scripts

Tools
Vivado/Quartus, PySerial, TCL, FTDI/USB-UART

3 Months 7–9: SoC + Layout Foundations


Topics to Learn
• RISC-V + Pipelining concepts
• Static Timing Analysis
• Standard cell layout: Inverter, NAND
• Python for timing report parsing

Projects
• RISC-V CPU (3–5 stage) in Verilog
• Run C program using RISC-V GCC
• Layout a CMOS gate (Magic VLSI / OpenLane)
• Timing report analysis script

Tools
RISC-V Toolchain, Magic VLSI, OpenLane, Python CLI

2
4 Months 10–12: Integration + Resume-Level Work
Topics to Learn
• Embedded–RTL co-design

• SoC architecture (AXI-lite, AHB-lite basics)

• Floorplanning and constraints

• SystemVerilog (basic constructs)

Projects
• RISC-V SoC with UART, timer, memory

• Firmware in C/ASM to test hardware blocks

• Python CLI to control modules

• Layout one SoC block using open tools

Tools
Vivado, GitHub, SystemVerilog, Python, GitBook/Notion

Bonus Activities
• Participate in VSDOpen workshops

• Contribute to OpenCores

• Engage with FOSSi Foundation

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