Abstract

There is an immense necessity of several kB of embedded memory for biomedical

systems which typically operate in the sub-threshold domain with perfect efficiency.
SRAM dominates the total power consumption and the overall silicon area, as 70% of the
die has been occupied by them. This brief proposes the design of a Transmission gate based
SRAM cell for biomedical applications eliminating the use of peripheral circuitry during
the read operation. This topology offers smaller area, reduced delay, low power
consumption and improved data stability in the read operation. The cell is implemented in
45nm CMOS technology operated at 0.45 V.

Keywords— SRAM, Biomedical Systems, Sub-threshold, Transmission Gate, Stability, 45-

nm Technology.
 CHAPTER-1

INTRODUCTION

A low power Static Random Access Memory (SRAM) design is a main concern of
implantable devices and wireless applications in which the input power or battery life is of
a key concern, , whose operational frequency ranges between few hundreds of Kilohertz to
tens of Megahertz . This is because of the major contribution of the SRAMs on the System
on Chips (SoC) as they occupy about 70% of the die area, which could be further increased
in the future. The proliferation of the transistors count in SRAMs and the corresponding
leaking current of these transistors in the scaled down technologies has made these devices
more power hungry.

Static Random Access Memories mostly contribute to the performance, area and power
dissipation of the digital integrated systems. The mentioned implantable and wireless
applications require low power circuits operating for a long time, occupying less area
without degrading the performance, as it provides inconvenience and may even be risky
specially while considering the implantable devices. One of the most straight forward and a
worthwhile method of achieving power efficiency is of reducing the supply voltage since
the leakage power and the active power has an exponential and quadratic relation
respectively with the supply voltage. However, lowering the supply voltage would diminish
the robustness of the circuit and can also cause the system to perform malfunction.
Therefore, reducing the supply voltage and at the same time maintaining the robustness of
the circuit is most important for the power constrained systems, as data stability is one of
the main concern of the SRAM cells.

At the near and sub threshold region, the Conventional 6T cell decline to operate
because of the deterioration of write ability and the read stability. To have a triumphant
write operation, it is desirable to use a wide access transistor which in turn could affect
the read stability. This represents a tradeoff issue for the data stability during the write
and read operations. Researchers proposed several cells basing on removal of the tradeoff
between the read and write stability issues. These proposals such as cells rely on
decoupling the read port from the write port by separating the read as well as write paths
allowing each of the operation to be enhanced independently. However, they are either
prone to leakage current, take a large area or utilize a single ended read scheme that
degrades the read sensitivity. To conquer the complication of single ended read scheme,
various techniques were implemented enhancing differential read port by including extra
transistors but with a penalty of extra area. One more technique designed was using the
transmission gates to improve the stability.

This brief proposes a new Transmission gate based 8T SRAM cell specifically
designed for Read operation which efficiently improves the Read Noise Margin with
reduced power and reduced delay. It particularly minimizes the area by using less number
of transistors by eliminating the peripheral circuitry that is required to carry out the read
process. The rest of this brief is structured as given below: Section-II provides the basic
Architecture of Static Random Access Memory, Section-III projects the operation of a
Conventional 6T, 8T and other Existing 10T SRAM cells, Section-IV presents the
proposed 8T SRAM cell performance with detailed explanation, Section-V gives the
comparative results of the proposed cell with the existing ones and Section-VI winds up
the brief with a conclusion.
 CHAPTER-2
LITERATURE SURVEY

2.1 Next Generation Micro-power Systems

Emerging microsystems such as portable and implantable medical electronics,

wireless micro sensors and next-generation portable multimedia devices demand a dramatic
reduction in energy consumption. The ultimate goal is to power these devices using energy
harvesting techniques such as vibration-to-electric conversion or through wireless power
transmission. A major opportunity to reduce the energy consumption of digital circuits is to
scale supply voltages to 0.5V and below. These include variation-aware design for logic and
SRAM circuits, efficient DC-DC converters for ultra-low-voltage delivery, and algorithm
structuring to support extreme parallelism. This project also addresses micro-power analog
and RF circuits, which require the use of application specific structures and highly digital
variation-aware architectures. The design of micro-power electronics requires a system-level
design approach involving variation-tolerant architectures, ultra-low voltage circuits, and
highly digital RF circuits. Such self-powered electronics will be a key enabler of exciting
new applications such as implantable medical devices.

2.2 Bit-Interleaving-Enabled 8T SRAM with Shared Data-Aware-Write and Reference-

Based Sense Amplifier

The design of a low-voltage SRAM for biomedical chip applications. The SRAM is designed
using a standard 8T bit-cell, featuring shared data-aware write scheme and differential
reference-based sense amplifier. The proposed techniques make the 8T SRAM possible to
use bit-interleaving architecture and address the half-select problem, achieving area-
efficiency and power reduction. A 96kb 8T SRAM test chip is implemented in a 65nm
CMOS process to verify the proposed schemes, which operates functionality at a VDD min
of 0.36V and has a power consumption of 5.1μW. An area-efficient sub-threshold SRAM
where the cell array employs the conventional SE-8T SRAM cell with our proposed bit-
interleaving architecture, and the read scheme exploits the proposed reference-based SA to
read data out. It exhibits 15.4% array area overhead with ample noise margins compared the
SE-8T SRAM. Measured results of a 96kb SRAM embedded in an EEG processor using a
65nm CMOS process shows that the SRAM can operates functionality at a voltage down to
0.36V, and has a power consumption of 5.1μW with a frequency of 125KHz.

2.3 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read
Port for Low Switching Power and Ultralow RBL Leakage.
In this paper, a new 10T static random access memory cell having single ended
decoupled read-bit line (RBL) with a 4T read port for low power operation and leakage
reduction. The RBL is precharged at half the cell’s supply voltage, and is allowed to charge
and discharge according to the stored data bit. An inverter, driven by the complementary data
node (QB), connects the RBL to the virtual power rails through a transmission gate during the
read operation. RBL increases toward the VDD level for a read-1, and discharges toward the
ground level for a read-0. Virtual power rails have the same value of the RBL precharging
level during the write and the hold mode, and are connected to true supply levels only during
the read operation. Dynamic control of virtual rails substantially reduces the RBL leakage.
The proposed 10T cell in a commercial 65 nm technology is 2.47× the size of 6T with β = 2,
provides 2.3× read static noise margin, and reduces the read power dissipation by 50% than
that of 6T. The value of RBL leakage is reduced by more than 3 orders of magnitude and
(ION/IOFF) is greatly improved compared with the 6T BL leakage. The overall leakage
characteristics of 6T and 10T are similar, and competitive performance is achieved. In this
paper, we have presented our 10T SRAM cell that uses a 4T read port and SE RBL. RBL is
precharged at half the supply voltage and, during the read operation, is charged or discharged
according to the bit stored. For a read-0 operation, RBL discharges through TG and nMOS
transistor, and for the next precharge, RBL is supplied current by VP. For a read-1 operation,
RBL is charged from vdd/2 to vdd by virtual read port. For the next precharge, RBL level is
decreased and current flows from RBL to VP. By precharging through VP (which is half vdd)
and charge recycling mechanism, LP10T only dissipates half the average read dynamic
power compared with 6T. In 65 nm, performance figure (mV/μW) of 1.83× of 6T is achieved
at 1 V, and 1.84× on average at different supply levels. Due to decoupling of internal nodes,
RSNM is increased by 2.3× compared with 6T. Overall leakage power of LP10T is similar to
6T, however, RBL leakage is reduced by more than 3 orders of magnitude, and thus a higher
number of cell could be integrated on a single column.
2.4 Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

The Schmitt-Trigger (ST)-based differential- sensing static random-access memory

(SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the
fundamental conflicting design requirement of the read versus write operation of a
conventional 6T bitcell. The ST operation gives better read-stability as well as better write-
ability compared to the standard 6T bitcell. The proposed ST bitcells incorporate a built-in
feedback mechanism, achieving process variation tolerance— a must for future nano-scaled
technology nodes. A detailed comparison of different bitcells under iso-area condition shows
that the ST-2 bitcell can operate at lower supply voltages. Measurement results on ten test-
chips fabricated in 130-nm CMOS technology show that the proposed ST-2 bitcell gives 1.6x
higher read static noise margin, 2xhigher write-trip-point and 120-mV lower read-Vmin
compared to the iso-area 6T bitcell.

2.5 A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm

CMOS
In modern ICs, the trend of integrating more on-chip memories on a die has led
SRAMs to account for a large fraction of total area and energy of a chip. Therefore, designing
memories with dynamic voltage scaling (DVS) capability is important since significant active
as well as leakage power savings can be achieved by voltage scaling. However, optimizing
circuit operation over a large voltage range is not trivial due to conflicting trade-offs of low-
voltage (moderate and weak inversion) and high-voltage (strong inversion) transistor
characteristics. Specifically, low-voltage operation requires various assist circuits for
functionality which might severely impact high-voltage performance. Reconfigurable assist
circuits provide the necessary adaptability for circuits to adjust themselves to the
requirements of the voltage range that they are operating in. A 64 kb reconfigurable SRAM
fabricated in 65 nm low-power CMOS process operating from 250 mV to 1.2 V. This wide
supply range was enabled by a combination of circuits optimized for both sub threshold and
above-threshold regimes and by employing hardware reconfigurability. Three different write-
assist schemes can be selectively enabled to provide write functionality down to very low
voltage levels while preventing excessive power overhead. Two different sense-amplifiers are
implemented to minimize sensing delay over a large voltage range. A prototype test chip is
tested to be operational at 20 kHz with 250 mV supply and 200 MHz with 1.2 V supply. Over
this range leakage power scales by more than 50 X and a minimum energy point is achieved
at 0.4 V with less than 0.1 pJ/bit/access. Ultra-dynamic voltage scaling is an important
technique to reduce energy consumption of circuits under time-varying performance
constrained scenarios. SRAMs occupy an important portion of total area and energy in
modern ICs and hence it is especially important to design voltage scalable memories. To
enable highest possible energy savings and a wide performance range, it is crucial to design
memory circuits that can do voltage scaling from deep subthreshold region to full- levels.
However optimizing circuits for a large voltage range is challenging because of the
conflicting nature of functionality problems at low voltages and performance concerns at high
voltages. In this work, we address this problem by employing reconfigurable peripheral assist
circuits and 8T bit-cells. 64 kbit SRAM module fabricated in 65 nm CMOS process achieves
four orders of magnitude performance scaling from 200 MHz down to 20 kHz at 1.2 V and
0.25 V respectively. Minimum energy point occurs at 0.4 V with 11 pJ/access where 128-bit
words are read from or written to the memory.

2.6 Low-Power Embedded SRAM Modules with Expanded Margins for Writing

Many SoCs embed SRAM modules which consume a large proportion of the total
power and impacts battery life in mobile Embedded SRAM modules are developed which
feature expanded writing margins for low-voltage operation, write replica circuits to
accommodate process variation and low leakage current. Together these techniques achieve
both low active and standby power. This SRAM as 32kb and 512kb modules is manufactured
in a 90nm process. Shmoo plots are given in Fig. 26.4.6. The 32kb module with a Vsamp-Vss
connection operates at 750MHz. The 512kb module with a Vsamp-Vssm connection operates
at 450 MHz and its leakage current is 48.4μA in the active mode

2.7 A 256 kb 65 nm 8T Sub threshold SRAM Employing Sense-Amplifier Redundancy

Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and
leakage power, a dominating portion of the total power in modern ICs. Hence, energy
constrained applications, where performance requirements are secondary, benefit
significantly from an SRAM that offers read and write functionality at the lowest possible
voltage. However, bit-cells and architectures achieving very high density conventionally fail
to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that
uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used
to ensure read stability, and peripheral control of both the bit-cell supply voltage and the
read-buffer’s foot voltage enable sub- write and read without degrading the bit-cell’s density.
The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy,
which reduces read errors by a factor of five compared to device up-sizing. At its lowest
operating voltage, the entire 256 kb SRAM consumes 2.2 W in leakage power. Voltage
scaling is an effective strategy for minimizing the power consumption of SRAMs. Further, as
SRAMs continue to occupy a dominating portion of the total area and power in modern ICs,
the resulting total power savings are significant. Unfortunately, however, conventional
SRAMs, based on the 6T bit-cell, fail to operate at voltages below approximately 700 mV
both because of reduced signal levels and because of increased variation. In sub- , in
particular, threshold voltage variation has an exponential effect on the drive current, resulting
in increased cell instability and a severely degraded read-current. To address these
limitations, an 8T bit-cell is incorporated into a 65 nm 256 kb SRAM, and it achieves full
read and write functionality deep into the sub- regime at 350 mV. At this voltage, the total
leakage power is 2.2 W, and the operating speed is 25 kHz. The significantly reduced speed
is expected in suband is acceptable for low throughput, energy-constrained applications. At
350 mV, the leakage power represents almost 85% of the total power consumption, so,
leakage reduction is a critical consideration. Additionally, the tradeoff between the size of a
sense-amp and its statistical offset is emerging as a primary limitation to SRAM scaling in
advanced technologies. In this design, enabling sub- write requires the use of circuit assists
that result in a layout where sense-amp multiplexing between adjacent columns is
impractical. Accordingly, the sense-amp scaling limitation is stressed, necessitating a
different approach to managing the offset–area tradeoff. The concept of sense-amp
redundancy is introduced, and it is demonstrated that, for a given area constraint, errors in the
sensing network due to offsets can be reduced by over an order of magnitude. In this design,
a factor of five improvement is expected with the implemented scheme, which incorporates a
simple start-up control loop.

2.8 A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and
Deep Sleep Mode

A voltage scalable 0.26 V, 64 kb 8T SRAM with 512cells per bitline is implemented in a 130
nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design
improves cell write margin and read performance without the aid of peripheral circuits. A
marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage
current which becomes comparable to a read current at subthreshold supply voltages. The
MBLC allows us to lower􀀀􀀀__ to 0.26 V and also eliminates the need for precharged read
bitlines. A floating read bitline and write bitline scheme reduces the leakage power
onsumption. A deep sleep mode minimizes the standby leakage power consumption without
compromising the hold mode cell stability. Finally, an automatic wordline pulse width
control circuit tracks PVT variations and shuts off the bitline leakage current upon
completion of a read operation. Lowering and reducing leakage become more important in
applications where energy dissipation is the primary design constraint. This paper proposes
circuit techniques for lowering and minimizing leakage. Utilizing RSCE in the read and write
ports of the SRAM cell improves write margin and read performance. The MBLC scheme
lowers by compensating bitline leakage and improving bitline sensing margin. The proposed
floating bitline scheme and deep sleep mode improve the leakage current reduction during a
normal operation and a standby mode. An automatic read word line pulse width control
scheme improves readability and reduces wasted read power by tracking the PVT variations.
A 64 kb SRAM fabricated in a 130 nm CMOS technology with 512 cells per bit line verifies
the lowering and leakage reduction achieved by the proposed circuit techniques. These
techniques facilitate a superior minimum energy solution through improved leakage reduction
and the enhanced SRAM performance.
2.8 A Large σVTH/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled
Differential Sensing and Fast Write-Back Scheme

Nanometer SRAM cannot achieve lower VDDmin due to read-disturb, half-select

disturb and write failure. This paper demonstrates quantitative performance advantages of a
zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T)
with write-back schemes, which was previously recognized as the most area-efficient cell
under large σVTH/VDD conditions. Since Z8T uses only 1T for each decoupled read-port,
faster 2T differential sensing (D_S) can be implemented within the same area as the single-
ended DS8T. Thanks to D_S, Z8T cell enables much faster R/W speed at VDDmin than
DS8T. For the same VDDmin/speed, Z8T reduces the cell area by 15%. The Z8T 32 Kb macro
is 14% smaller area and 53% faster than DS8T cells. Three macros were fabricated using
foundry provided 65 nm low-power and 90 nm generic processes. The measured V DDmin for
a 65 nm 256-row 32 Kb and a 32-row 4 Kb macro are 430 mV and 250 mV respectively. The
measured VDDmin for a 90 nm 256-row 64 Kb macro is 230 mV. a Z8T SRAM, which
comprises an area efficient 2T differential decoupled read port with a pseudo RWL
for cell stability during read operations. The proposed Z8T cell is realized using a zigzag
shape layout to achieve compact area and fully symmetric device placement for litho-friendly
layout. For the macro implementation, this work uses zigzag placed DRWB-SA to achieve
fast read and write-back speed. The fabricated macros confirm that the 8T can achieve a
VDDmin thatis 430 mV lower than the VDDmin of a conventional 6T SRAM cell.

2.9 A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array

A read-disturb-free, 1-read/1-write port, 8-transistor (8T) bitcell utilizing differential

sensing. The conflicting design requirement of read versus write operation in a conventional
6T SRAM bitcell is eliminated using separate read/write access transistors. A distributed
read-access transistor shared across the bitcells of every row enables read disturb- free
differential sensing operation with eight transistors per bitcell. Write-access transistors are
upsized to form a diffusion-notch-free layout which would result in improved
manufacturability. 1R/1W port nature of the proposed 8T bitcell makes it an attractive choice
for the high speed, dense register file (RF) designs. Bitcell failure measurements on 20 test
chips fabricated in 90-nm CMOS technology demonstrate that the proposed differential 8T
bitcell shows 220 mV lower read- , 40 mV lower hold- , 25 mV higher weak-write voltage
compared to the iso-area 6T bitcell at iso-performance. At 600 mV, the proposed 8T bitcell
array operates up to 67.2 MHz. Read-disturb-free, differential sensing, 1R/1W port, 8T bitcell
is proposed. The conflicting design requirement of read versus write operation in a
conventional 6T SRAM bitcell is eliminated using separate read/write access transistors. A
distributed read-access transistor shared across the bitcells of every row enables read-disturb-
free differential sensing operation while consuming 8 transistors per bitcell. Due to its read-
disturb-free and dual port functionality it can also be used in Register File designs requiring
phase based back-to-back read/write operations. Measurement results on a 90-nm CMOS
test-chip with the proposed 8T bitcell demonstrated lower read/hold V minbetter write ability
and lower leakage compared to the iso-area 6T bitcell at iso-performance.

2.10 Single-Ended Sub threshold SRAM With Asymmetrical Write/Read-Assist

In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and
positive feedback sensing keeper schemes are proposed to improve the read static noise
margin (RSNM), write margin (WM), and operation speed of a single-ended read/write 8 T
SRAM cell. A 4 Kbit SRAM test chip is implemented in 90 nm CMOS technology. The test
chip measurement results show that at 0.2 V V DD, an operation frequency of 6.0 MHz can be
achieved with power consumption of 10.4 W. a 256 16 bits subthreshold SRAM, based on a
single-ended 8 T cell with asymmetrical Write-assist virtual ground biasing scheme and
positive feedback sensing keeper, was described. The asymmetrical Write-assist virtual
ground biasing scheme improved the Write Margin (35% of supply voltage) and enhanced
the Write performance. The isolated Read buffer with positive feedback sensing keeper
enhanced the RSNM to 50% of the supply voltage, enabled the elimination of BL precharge
operation and full-rail BL swing to minimize the power dissipation of BL sensing circuit. The
post layout simulation results showed the chip achieves 234 MHz and 6 MHz operation
frequency at 600 mV and 200 mV supply voltage. The measured results verified that the chip
achieved 6 MHz operation frequency at 200 mV with power consumption of 10.4 W.
 CHAPTER-3

INTRODUCTION TO EDA TOOL

3.1 TECHNOLOGIES USED (EDM)

Tanner EDA is a suite of tools for the design of integrated circuits. These tools allow you to
enter schematics, perform SPICE simulations, do physical design (i.e., chip layout), and
perform design rule checks (DRC) and layout versus schematic (LVS) checks. There are 3
tools that are used for this process: S-edit – a schematic capture tool T-SPICE – the SPICE
simulation engine integrated with S-edit L-edit – the physical design tool Using S-Edit
(Schematic Entry Tool) & T-SPICE (Analog Simulation Tool).Curves of an NMOS
Transistor S-edit are a schematic entry tool that is used to document circuits that can be
driven forward into a layout of an integrated circuit. It also provides the ability to perform
SPICE simulations of the circuits using a simulation engine called T-SPICE. T-SPICE can
be setup and invoked from within S-edit.
Initially Setup your Directory Structure & download Libraries a) Log onto a computer
on 6th floor Cob Leigh. B) You want to create a directory for all of your Tanner EDA
projects. You also will need to download and unzip a set of library & model files from the
course website that will be used for your simulations. – Create a directory structure named
“EELE414_VLSI_Fall2011\Tanner Projects c) Go to the course website and download the
zip file called “Tanner_Libraries.zip”. Unzip it into your Tanner Projects directory. These
groups of files contain the necessary information to enter components into S-edit (circuit
symbols), perform SPICE simulations (models), and do physical layout (layer definitions,
DRC, LVS).

3.2 START NEW DESIGN & SETUP LIBRARIES

a) Start S-Edit: -
Start – All Programs – Tanner EDA – Tanner Tools v12.6 – S-Edit v12.6.
b) Start a New Design: -
Using the pull-down menus, create a new design: - File – New – New Design A dialog will
appear asking for a design name and location. When you give the name, S-edit will create a
folder of that name in the directory that you provide that will contain all of the design files.
You should give a descriptive name that represents each simulation you
will be running. – Enter the name “HW03_NMOS_IV_Part1” and browse to your
“EELE414_VLSI_Fall2011\Tanner Projects” directory – Click “OK”.
c) Create a new Cell: -
A “cell” is a design element. A cell can contain multiple views such as schematics and
symbols. Cells can be instantiated in other cells. When performing a simulation, we will
typically call the cell “TOP”. When we are testing a circuit, for example an inverter, the
inverter will have its own cell that contains a schematic of the devices and a symbol. The
inverter cell is instantiated in the TOP cell that contains ideal elements such as voltage
sources and probes that are only used for simulation. This allows us to separate the cells that
are actually going to be implemented on the die versus cells that are only used for simulation.
Using the pull-down menus, create a new cell view: - Cell – New View: - enter the cell name
“TOP”. Ensure the design name is “HW03_NMOS_IV_Part1” and click OK. You can leave
the interface and view names “view0”. A blank schematic page will appear. It is a good idea
to save this right now.
D) Enter the symbol libraries: -
First, you need to include a library which contains the symbols for all basic circuit elements
such as resistors, NMOS, capacitors, etc.… The libraries for all the basic symbols are in the
Tanner_Libraries.zip file you downloaded and unzipped. – On the left side of the S-edit
screen you’ll see a Libraries window, click on the “Add” button. – Browse to “Libraries\All\
All. Tanner” and click “OK” You should see a set of libraries a appear:
3.3 SETUP THE SPICE MODELS FOR THE GENERIC_025 KIT
The libraries that you just added have symbols for NMOS and PMOS transistors.
However, all non-linear components such as MOS transistors require a model to describe
their behavior. If you simply enter an NMOS symbol in your schematic, SPICE will not
know what to do since each NMOS transistor fabricated in a different technology behave
differently. In this example, we will use a transistor technology called “Generic_025”, which
represents a standard, 0.25um CMOS process. You will need to setup the SPICE models for
this process in S-edit. Once you do that, when you enter an NMOS or PMOS transistor, you
can then associate the 0.25um model to that symbol. Using the pull-down menus, setup the
SPICE models: - Setup – SPICE Simulation – In the dialog that appears, you should highlight
“General” on the left. – On the right, click in the “Library Files” field. This is where you will
specify any SPICE models you will be using in your simulations. Browse & select
“Generic_025_Kit\ Generic_025_SPICE_Models_Level1.lib” – On the right, click in the
“SPICE File Name” field. This is where you specify the name and location of the SPICE Net
list output. Browse to your design directory “EELE414_VLSI_Fall2011\Tanner Projects\
HW03_NMOS_IV_Part1” and enter the filename “Top’s”. – On the right, click in the
“Simulations Results File Name” field. This is where the results of the simulation will be
written. This file is what the waveform viewer will look for when you go to plot your results.

Figure 3.2: Setup of SPICE models

Browse to your design directory “EELE414_VLSI_Fall2011\Tanner Projects\
HW03_NMOS_IV_Part1” and enter the filename “TOP. Out”.
Before you can exit this window, you will need to select an analysis type. We will setup the
details of the analysis later, but for now, just check the “DC Sweep Analysis” and click “OK”
to close the setup window.

Figure 3.3: Selecting DC sweep analysis

3.4 ENTER THE SCHEMATIC TO SIMULATE THE IV BEHAVIOR OF AN

NMOS TRANSISTOR
A) We will be entering the following circuit:
Enter the NMOS transistor – On the left, click on “Devices” in the upper window.
This will display all of the symbols available in this group. You should see all of the
components that you can implement on a CMOS integrated circuit. – On the bottom left
window, click once on “NMOS”. You should see the symbol of the NMOS transistor show
up in the symbol viewer window at the bottom. – To place the NMOS, you will insert-
“Instance” button. Two things happen when you click on this button. First, a dialog will
appear that will allow you to setup the parameters for the NMOS. Second, the symbol will
attach to your mouse. We will place the NMOS in the schematic first and then set its
properties later. This is an easier way to enter the device.
Click in the schematic window to drop an instance of the NMOS. Hit the “Esc” button to end
the insert-mode.

Figure 3.4: Setup properties of transistor

Figure 3.5: Schematic diagram of the transistor

The NMOS is now in the schematic. A note on zooming: - [Home] = zoom fit – [-] = zoom
out – [=] = zoom in – the scroll wheel also zooms in/out. – To setup the
NMOS, click on the NMOS symbol. You will see the properties of the device on the left. We
want to setup the following: - Model: enter “NMOS”. This model is found in the
Generic_025 library you added – Name: M1. The SPICE designation for MOS transistors is
to have the name start with an “M”. S-edit automatically appends an M to the name is the
final name will be “MM1” in the Top’s file. But it is good practice to name all MOS
transistors with M’s. – W Set to 2.5u. This is the default. – L Set to 0.25u. This is the default.

B) Enter a DC source for VGS:

Using the same process, you used for the NMOS symbol, enter a “SPICE Elements:
Voltage Source”. This is a generic voltage source symbol that is configured as a DC, TRAN,
PWL, etc. In its properties dialog, – Click on the voltage source and enter the following: -
Master Interface: DC (this is the default but this is how you would change it to something
else. – Name: VGS_Source (it is a good idea to use descriptive names) – V. This is where
you will set the DC voltage (i.e., 4v, 5v). However, for this example we will use a parameter
instead of a hardcoded value. We will enter a parameter name here and then set up the
parameter later. Enter “VGS_param” for the value of V. When performing a DC sweep, you
must use parameters for the sweep.

C) Enter a DC source for VDS:

Using the same process as above, enter a DC source for VGS with the following: - Master
Interface: DC (this is the default but this is how you would change it to something else. –
Name: VDS_Source – V “VDS_param” Position the sources as in the following figure:
Enter wires by clicking on a symbol node and then dragging. Enter corners by
clicking once where you want to turn. – You can label nets using the “Net Label” icon at the
top.

D) ENTER GROUNDS:
Using the same process as above enter 3 grounds from MISC-GND.
The source is connected to the ground.
 Figure 3.6: Connect power supply and set the properties

Figure 3.7: Connect the ground

E) Enter wire:
You can enter wires by clicking on the “wire “icon at the top.
Enter a Current Probe to monitor IDS.
Enter the SPICE Commands: Print Current component. This doesn’t connect to anything.
You just place it anywhere and then tell it what current to monitor in its properties dialog. –
In its properties dialog, setup:
Terminal: D (this is the Drain of the NMOS)
Device: MM1 (this is the name of the device. Notice that we called it M1, but S-edit
automatically appends another M to the name. You will only see this once you run the
Netlist.
Analysis: DC (VERY IMPORTANT TO SELECT THIS!!!!)

3.5 SETUP THE PARAMETERS THAT WILL BE USED DURING THE DC

SWEEP ANALYSIS
When we entered the VGS and VDS sources, we set their values to “VGS param” and “VDS
param”.
We now need to setup these parameters.
Using the pull-down menus: -
Setup – SPICE Simulations
On the left, click on “Parameters”.
DC analysis is done in the settings.
In the Figure 3.9 Adding parameters folder on the right, click on the “Add Parameters” button
(it is in the upper right corner next to the red X)
Enter: Name: VGS_param
Value: 1v – On the right, click on the “Add Parameters” button
Enter: Name: VDS_param
 Figure 3.8: DC analysis

Figure 3.9: Adding parameters folder

Value: 2.5v
We will overwrite these values during our sweep, but the parameters need to exist first. Part
5: Setup the SPICE DC Sweep Analysis.
Using the pull-down menus:
Setup – SPICE Simulations
On the left, click on “DC Sweep Analysis”
On the right, enter the following for Source (this is what will be swept)
Source or Parameter Name: VDS_param
Start Value: 0
Stop Value: 2.5 Step: 0.1
Sweep Type: Lin
On the right, enter the following for Source (this is what will be swept)
Source or Parameter Name: VGS_param
Start Value: 1
Stop Value: 1.5 Step: 0.5
Sweep Type: Lin
NOTE: The first parameter you setup in this dialog will be plotted on the independent axis.
Part 6: Simulate the Design

Figure 3.10: Graph of VDS VS Current

First, check you design using the pull-down menus:

Tools – Design Checks (any warnings or errors will be shown at the bottom)
Simulate your design:
Clock on the Green Arrow to start the simulator:
The T-Spice window will appear. If everything is OK, the waveform viewer will also appear.
If everything worked, your waveforms should look like this:
a) View the Netlist:
In the T-spice window, right click on the file at the bottom and select “Show Netlist”. This
will bring up the top’s Netlist that was created and used by the spice engine. This is a
good place to look when you get errors. This is the text-based description of what you
entered in S-edit.
 Figure 3.11: Spice engine to check errors
View the Waveform: - If the windows viewer did NOT automatically appear, you can click
on the file in the T spice window and select “Show Waveform”.

3.6 TRANSIENT ANALYSIS OF A CMOS INVERTER & SYMBOL

CREATION

Part 1: Start a New Design, Setup Libraries & Setup Simulation

In this we will create a CMOS inverter and simulate its transient response. We
will create an inverter design that contains a symbol and then instantiate it in another
schematic to stimulate the circuit.
Symbols are handled by adding another view to a design. We will start by creating a
design called “Inverter” and then create a schematic view. This schematic will contain an
NMOS and PMOS wired as an inverter. We will add “Ports” for the Input, Output, VDD, and
VSS. We will then add a symbol view to this design. The symbol will contain the inverter
shape and the corresponding pins for Input, Output, VDD, and VSS.
We will then create a separate schematic called TOP that will be used to test the
inverter. We will instantiate the inverter symbol in TOP. We only want to put items into the
inverter design that can be fabricated. TOP will contain the ideal voltage sources to provide
the input waveform, the power supplies, and a mock load. In this way, when we go into
physical design (i.e., layout), we only drive forward the isolated circuits.
-Start S-Edit
-Create a new design called:
“EELE414_VLSI_Fall2011\Tanner Projects\HW04_INV_Transient_Part1”
-Add the Tanner Projects\Libraries\All\All. Tanner library to the library list on the left
-Create a new Cell called “TOP” using the Pull-down Menus
-Cell – New View
Name = TOP
View Type = schematic
-Setup the simulation using the Pull-down Menus:
-Setup – SPICE Simulation
-Highlight the General Tab of the Setup SPICE window and set the following:
SPICE File Name: \HW04_INV_Transient_Part1\top’s
Library Files: ..\Generic_025_Kit\Generic_025_SPICE_Models_Level1.lib
Simulation Results File Name: File Name: \HW04_INV_Transient_Part1\TOP. Out
-Check the “Transient/Fourier Analysis” box on the left and set the following:
Stop Time = 2ns Maximum Time Step = 10ps
-Click “OK”
Part 2: Create the Inverter:
a) Create a new schematic view using the pull-down menus:
-Cell – New View
Name = Inverter
View Type = schematic
b) Enter the inverter schematic:
Entering the NMOS:
Name = M1
L = 0.25u
W = 2.5u
Model =NMOS
-Entering the PMOS:
Name = M2
L = 0.25u
W = 5.0u
Model =PMOS
-Entering the Ports:
Ports are entered using the icons on the top of the S-edit window. Enter the following:
In Port: Name it “IN”
Out Port: Name it “OUT”
In/Out Port: Name it “VDD”
In/Out Port: Name it “VSS”
-Wire up the Inverter
Enter wire connections as shown in the previous figure.
a) Export a SPICE Netlist
Exporting a SPICE Net list is a good idea in order to verify that you have entered the
schematic correctly. Also, this Netlist will be used later when performing a “Layout versus
Schematic (LVS)” check. We want to export a Netlist at the Inverter schematic cell level so
that a Netlist of just the inverter exists for LVS. When we conduct the simulation of this
inverter, we will create a TOP level schematic that will have a Netlist containing ideal
voltage sources. This Netlist can’t be used for LVS since it contains components that won’t
be fabricated.
With the schematic open, use the pull-down menus to perform:
-File – Export – Export SPICE.
-Browse to your design directory and give the file name “Inverter.spc”.
-Click “OK”
If you open the Inverter.spc with a text editor, you will see the following:
A note on drawing:
The “Path” icon will put you into a mode where you can draw lines that are not wires.
The “Circle” icon will allow you to enter the inversion bubble.
The ports can be moved by holding down “alt-m”
The ports can be rotated by selecting and pressing the “r” button
Remember to save.
 Figure 3.12: Export SPICE net list
Part 3: Create the TOP schematic to test the Inverter
a) Instantiate the Inverter in the TOP schematic
Open the TOP schematic view using the pull-down menus:
Cell – Open View:
Cell Name: TOP
View Type: schematic
In the library windows on the left of the window, highlight your
“HW04_INV_Transient_Part1” library. In the lower left window, you will see your two Cells
“TOP” and “Inverter”.
-Click on “Inverter” and you will see your symbol show up in the symbol viewer.
-Click on the “Instance” button and place your symbol in the TOP schematic.
a) Enter the following circuit in order to power and stimulate your inverter:
A note on drawing:
The “Path” icon will put you into a mode where you can draw lines that are not wires.
 Figure 3.13: Symbol of inverter

The “Circle” icon will allow you to enter the inversion bubble.
The ports can be moved by holding down “alt-m”
The ports can be rotated by selecting and pressing the “r” button Remember to save.
Part 3: Create the TOP schematic to test the Inverter
a) Instantiate the Inverter in the TOP schematic

Open the TOP schematic view using the pull-down menus:

-Cell – Open View:
Cell Name: TOP
View Type: schematic
In the library windows on the left of the window, highlight your
“HW04_INV_Transient_Part1” library. In the lower left window, you will see your two Cells
“TOP” and “Inverter”.
-Click on “Inverter” and you will see your symbol show up in the symbol viewer.
-Click on the “Instance” button and place your symbol in the TOP schematic.
a) Enter the following circuit in order to power and stimulate your inverter:
Enter the Pulse Voltage Source. All voltage sources are the same component in the SPICE
Elements library. The default is DC, but this can be changed to any other type
of source in the properties dialog.
Name = Vin Source
 Figure 3.14: Symbolic view of inverter

Master Interface = Pulse

Period = 1ns Pulse
Width = 0.5ns
V High = 2.5v
V Low = 0v
Rise Time = 10ps
Fall Time = 10ps
-Enter a Load capacitor from the Devices library.
Name = Cloud
C =50 fF
-Enter a DC Source for VDD
Name = VDD_Source
Master Interface = DC
V = 2.5v
-Enter the grounds from the Misc. library
-Enter wire connections and name them Vin and Vout
-Enter a voltage probe for both Vin and Vout
Part 4: Simulate the Design
a) First, check you design using the pull-down menus:
-Tools – Design Checks (any warnings or errors will be shown at the bottom)
b) Simulate your design:
-Clock on the Green Arrow to start the simulator:
The T-Spice window will appear. If everything is OK, the waveform viewer will also appear.
If everything worked, your waveforms should look like this:

Figure 3.15: Output waveforms of inverter

 CHAPTER – 4
EXISTING METHOD

4.1 SRAM ARCHITECTURE

The following Fig.1 displays the block diagram of a typical architecture of SRAM .
The SRAM chip chiefly consists of a Memory Array, a Row Decoder, a Column
Decoder, a Precharge circuit and a Sense Amplifier.
The memory array consists of number of cells in which the data is to be stored or read.
Each of the cell is capable of holding one bit of information. A row decoder and a column
decoder are used to select a particular cell from the array. The precharge circuit activates
the precharging of Bit Lines. A Sense amplifier particularly performs the read
functionality. It detects the content of a cell in the form of a small voltage variation
obtained between the cell's Bit Lines and produces the corresponding data that is stored
in that particular cell.

Fig 4.1 SRAM Architecture

 4.2 8T SRAM cell: The cell comprises of a decoupled read path with two extra nmos transistors to
eradicate the read disturb issue. But, it suffers with the leakage problem due to the added transistors relying
on the information stored in the cell.

Fig 4.2: 8T SRAM Cell

Fig 4.2: Schematic Diagram of 8T SRAM Cell

4.2.1 Simulation results:

Fig 4.3: Simulation results

4.2.2 Power Analysis:
At a given voltage, the consummate power of the SRAM cell should be less enough as
possible. It is examined from the Table-1 that read power of the proposed design (8T-P)
consumes the least power when compared to the other five cells. This is because since
the peripheral circuits that are generally used by the remaining cells are excluded in this
proposed work. Therefore the power consumed by those circuits can be eliminated
thereby providing less power consumption for the proposed cell.

Fig 4.4 Power Analysis

4.2.3: Average Power Supply

Fig 4.5 Average Power Supply

4.2.4: Delay:
The Access time of the cell should also be given priority as it represents the time taken
by the cell to perform a particular action. Table-1 provides the comparison of access
time of the six cells, which generally represents the delay generated between the input
and the output obtained. It can be explored that, the delay generated by this proposed
cell (P8T) is lesser than the other five cells. This is for the reason that instead of
precharging the two Bit Lines and then feeding them to the sense amplifier and finally
the sense amplifier producing the stored data of the cell as done in the existing
techniques, the proposed design directly produces the stored data which subsequently
reduces the access time.

Fig 4.6 Delay

 CHAPTER-5
PROPOSED METHODOLOGY
5.1 Introduction:
A transmission gate-based 9T (TG9T) SRAM cell is given in fig 5.1.The simplified
architecture of the proposed design is given in Fig. 5.1. The proposed TG9T SRAM cell has
some disadvantages in terms of dynamic power consumption compared to low power devices
working in the subthreshold region, but as has been aforementioned and studied extensively
in the forthcoming sections, TG9T offers great advantages in terms of read stability and write
ability, layout area, hold power/leakage current and variability during read, write and hold
operations, thus making it ideal for applications in modern IoT devices. Furthermore, as
CMOS reaches the scaling limits, the need for alternative technologies is necessary. Fin FET
is one of the strong contenders to replace the conventional metal oxide semiconductor field
effect transistor (MOSFET).

Fig 5.1: Proposed TG9T SRAM cell

Fig: 5.2 Simplified array architecture of the proposed design

5.2 Proposed TG9T SRAM cell:
The proposed TG9T is shown in Fig.5.1. Table 1 gives the different control signals
for different operations. During the read operation,one of the bitlines is discharged depending
on the data in the storage nodes, Q and QB. During the write operation, due to the removal of
the feedback path, the cell is able to write the desired data successfully (see Fig. 5.3). In the
hold mode, all the access transistors are maintained in OFF condition while bitline bar (BLB)
and bitline (BL) are set at VDD.

Table2: Operation table of the proposed TG9T SRAM Cell

Fig: 5.3 Variation of voltages at various of TG9T during write

operation where the data written at node ‘Q’ =1

5.3 Simulation results

5.3.1 Simulation setup:
International Technology Roadmap for Semiconductors (ITRS) forecasts the fundamental
technical requirements and lays down near and long-term goals for the semiconductor
industry. ITRS predicts variations in device parameters such as channel width (W), channel
length (L), channel doping concentration (NDEP), threshold voltage (Vt), oxide thickness
(tOX), and supply voltage (VDD) at least up to a range of ±10%. For higher accuracy of
results, we have performed Monte–Carlo simulations (with 5000 samples) by varying the
aforementioned device/process and environmental parameters and generating different SPICE
model files at 16-nm technology for each set of parameters utilising the predictive technology
model (PTM) .The varied device/ process parameters including W, L, NDEP, Vt, and tOX are
assumed to have independent Gaussian distributions with a 3σ variation of 10%, for
evaluation of salient design metrics such as read current (IREAD), leakage current (ILEAK),
read access time (TRA or read delay), write access time (TWA or write delay), RSNM,
WSNM and hold power (HPOWER). To establish the superiority of the proposed cell, it is
compared with 7T [23], fully differential 8T (FD8T) and single-ended disturb free 9T
(SEDF9T) cells.

5.3.2 Read current and its variability:

Read current (IREAD) in our proposed TG9T is the summation of the currents flowing
through both MN4 and MP4 of the TG1 as in Fig. 5.1 when node Q stores ‘0’ (QB stores ‘1’).
The averaging effect of the two parallel transistors in the transmission gate (TG) helps nullify
the variations in read current as has been explained in great detail in the following paragraph.
IREAD variability is decreased due to the use of the TGs in the proposed cell. The reason for
this is the averaging effects of the two parallel transistors in the TG. This can be easily
explained by using the inherent characteristics of TG (see Figs. 5.4–5.6). The effective
resistance (RE = RN||RP) of TG is best illustrated in Fig. 5.6. As Vout (VQB in our case)
increases, RN [resistance of N-type metal oxide semiconductor (NMOS)] increases, hence
current assing through it decreases, whereas RP [resistance of P-type metal oxide
semiconductor (PMOS)] decreases, hence current passing through it increases. As can be
seen from Fig. 6, the effective resistance of TG remains almost constant irrespective of the
voltage across it and hence current through TG (parallel combination of NMOS and PMOS)
also remains constant. This phenomenon helps in averaging/stabilising the net current passing
through the TG. From this, it can be inferred that IREAD through TG is more stable than
IREAD through NMOS. This is proved in simulation results which tell that TG9T offers
1.13× tighter spread than 7T in IREAD distribution (see Figs. 5.7 and 5.8) at nominal VDD of
0.7 V. TG9T offers improvement in IREAD variability at all respective voltages compared to
all the cells, compared here, as shown in Fig.5.9. This improvement is achieved at the
expense of 1.2× and 1.24× penalty in IREAD when compared to 7T and FD8T, respectively,
@ nominal VDD of 0.7 V (see Fig. 5.10). 7T shows higher IREAD than TG9T because the
drive current of NMOS is higher than PMOS. Even though the sum of the widths of MN4 (32
nm) and MP4 (32 nm) of TG1 in TG9T is equal to the width of access NMOS (64 nm) in 7T,
it does not make their drive strength equal. However, TG9T achieves lower spread in IREAD
which indicates improved variability than 7T due to the averaging (stabilising) effect of TG.

Fig5.4: Read current path during read operation

Fig5.5: Read current path during read operation where TG is replaced with the
resistance of the respective MOSFETs

Fig 5.6 Resistance of the respective MOSFETs and the effective resistance of the TG
 Fig 5.7: Distribution curve of read current (IREAD) for 7T VDD of 0.7V

Fig 5.8: Distribution curve of Iread for TG9T VDD of 0.7V

Fig 5.9 comparison of the variability of read current (IREAD) versus VDD for 7T, TG9T
(fig 5.1) FD8T and SEDF9T
 Fig 5.10 Comparison of read current (IREAD) versus VDD for 7T, TG9T and FD8T

5.3.3 Leakage current and hold power:

Leakage current is measured while the cell is operated in hold mode. The leakage
current of the proposed cell, TG9T, is lower than that of 7T even though access TG1/TG2 in
TG9T occupies the same area as of access NMOS in 7T (see Fig. 5.11). The results illustrated
in Fig. 11 can be explained by considering the hot carrier injection mechanism. The progress
in semiconductor integrated circuit technology is mostly the result of the device dimension
scaling. However, the supply voltage has not been scaled down with the same proportion
as the device dimensions. Consequently, the longitudinal electric field in the pinch-off region,
as well as the transverse electric field across the gate oxide has increased with increase in
MOSFET scaling. When an electron travels from the source to the drain along the channel of
a MOSFET, it becomes energetic and hot. Some of the hot electrons can cross over the
barrier of SiO2, giving rise to the gate leakage current (IG) (see Fig.5.12). Other hot
electrons, travel towards the drain and collide with Si atoms, creating secondary electron–
hole pairs by impact ionisation. The electrons are collected by the positive drain bias,
whereas the holes are collected by the negative body bias, giving rise to the substrate
current (IB) (see Fig.5.12). A slightly lower leakage in TG9T is due to a greater number of
PMOS devices in it. Why this happens can be perceived by considering the hot-carrier
injection mechanism in short-channel devices. The crossing of electrons from Si to
polysilicon (gate material) through SiO2 is more likely than the crossing of holes, as
electrons possess lower effective mass than that of holes. Moreover, the barrier height for
holes is 4.5 eV whereas that ofn lectrons is 3.1 eV. Thus, a greater number of PMOS devices
in TG9T slightly reduces leakage current as compared to the 7T SRAM cell. The lower
leakage current of TG9T compared to 7T at all corresponding voltages gives rise to higher
IREAD/ILEAK (Fig.5.13). For easier comparison, simulated data at 0.7 V are plotted in
Fig. 14. From the figure, it can be observed that the maximum value of HPOWER in TG9T is
lower than that of 7T. Furthermore, the distribution curves of TG9T and 7T crosses at 1 μW
HPOWER. Based on the available data from the distribution plot, we found that 14.74% of
statistical samples of 7T have more than 1 μW HPOWER whereas in the case of TG9T it is
only 10.3%. It signifies that the mean value of HPOWER is lower in TG9T than 7T.
HPOWER of the cells at different VDD are plotted in Fig. 5.15. From the figure, it can be
observed that the HPOWER of TG9T is lower than that of 7T at all respective supply
voltages.

Fig 5.11 Leakage current (ILEAK) versus supply voltage(VDD)

Fig 5.12 Effects of hot carrier injection in the subthreshold region leading to substrate current
 Fig 5.13: Read current (IREAD)/Leakage current (ILEAK) versus VDD

Fig 5.14: Comparison of hold power distribution of TG9T and 7T VDD=0.7V

Fig 5.15: Hold power Versus supply voltage VDD=0.7V

5.3.4 Read access time and its variability:

The proposed cell, 7T, and FD8T contain differential architecture in read mode.
Therefore, a sense amplifier is used to sense the data present in the SRAM cell. Read access
time (TRA) or read delay of a differential cell is defined as time estimated from the point
when WL starts increasing (for 7T and TG9T)/decreasing (for FD8T) from its initial low
level/high level to the point when BL or BLB is discharged by 50 mV from its initial pre-
charged level For the sense amplifier, the 50-mV difference in voltage between bitlines (BL
and BLB) is good enough to read data, presently stored in the SRAM cell [25, 32]. For the
proposed cell, because of the asymmetric discharge paths, we get slightly different TRA
values and we have plotted here the worst-case data for read time as shown in Fig. 5.16.

Fig 5.16: Variation of read time/delay versus supply voltage (VDD)

5.4 SIMULATION RESULTS:

Fig 5.17: Schematic Diagram Of Proposed System

 Fig 5.18: Simulation results of proposed system

5.4.1 Power Analysis:

Fig 5.18: Power Analysis of proposed system

5.4.2 Average Power:

 Fig 5.19: Average Power of proposed system

5.4.3 Delay:

Fig 5.20: Delay of proposed system

Table 3: COMPRASION TABLE

S.N Method No of Average Static Dynamic Delay

o Transistors Power power Power
1 8TSRAM 8 60.32uw 245uw 50uw 126ps
2 9TSRAM 9 35mw 2.23uw 72.12mw 147Ps