FORM NO. F/ EVAL / 006 Rev.00 Date 20.03.

2020 Page 1 of 17

Answer Key (PRE UNIVERSITY EXAM– B.Tech)-Part Time

SUB. CODE: EBEC22ID2 SUB.NAME: Microprocessors
& Microcontrollers
DEGREE :B.Tech BRANCH: CSE
YEAR/SEMESTER: I/II SECTIONS: ALL
MAX.MARKS:100 DURATION: 3 hours
DATE: 19-07-2024 PORTION: 5 units
Q. Contents of the Answer * Allocat
N ion of
o Marks
1 A 1
2 C 1
3 B 1
4 C 1
5 A 1
6 A 1
7 D 1
8 A 1
9 D 1
10 B 1
11 Flag Register is a 16-bit register, but there are only 9 flags available in the 8086
microprocessor. The rest 7 bits are hence left idle.

Types of Flags of Flag Register in 8086 Microprocessor

There are two types of flags of flag register in 8086 Microprocessor:

1. Condition Flags
2. Control Flags

1. Condition Flags
The conditional flags are set or reset after any arithmetic or logical operation is performed on
an 8 bit or 16-bit number. This category consists of the following 6 flags:
i. Carry Flag (CF): The carry flag will be set only if a carry is generated from the MSB
of the result after doing any operation in 8086 Microprocessor.
ii. Parity Flag (PF): Parity is related to the number of 1’s contained in the binary data.
There exist two types of parity:
6
o Even Parity: When the number of 1’s in the binary data are even.

o Odd Parity: When the number of 1’s in the binary data are odd.

For the flag, the PF is set if there exists an even parity in data after the execution of the
instruction. Else the flag is reset.

iii. Auxiliary-Carry Flag (AF): This flag is set if there is a generation of carrying from a
nibble, i.e. 4 bits of data.
iv. Zero Flag (ZF): If the result after performing the required operation (Arithmetic or
Logical) on the instructions is zero, in that case, the zero flags are set to 1. Else, it
remains reset.

v. Sign Flag (SF): If the result after performing any arithmetic or logic operation in the
given instruction is negative, then the sign flag is set to 1. Else, for a positive result,
the sign flag remains reset.

vi. Overflow Flag (OF): This Flag will be set if the register gets overflowed with data
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after any arithmetic or logic operation. This happens in cases when the carry is getting
in in MSB, but there is no space in the register to store the carried out bit.

2. Control Flags
The control flags are used to navigate the microprocessor for certain operations. There are 3
types of control flags:
i. Trap Flag (TF): This flag is used of we need single-step debugging in our code. If the
TF is set, then the execution will be done step by step. Otherwise, the free-running
operation will be done.
ii. Interrupt Flag (IF): This flag is used to enable the Interrupt. The microprocessor is
capable of handling interrupts only if this flag is in the set mode. Otherwise, any
interrupt raised while the execution of the instructions will not be handled by the
microprocessor.

iii. Direction Flag (DF): This flag is used for string operations. If this flag is set, the
string will be read from higher-order bits to lower order bits and vice versa.
12 3
ALP FOR LOGICAL OR OPERATION

ALP FOR LOGICAL AND OPERATION

3
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13 6

Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its
operation.

Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and
10MHz.

Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit
address and after that it carries 16-bit data.

Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it
carries 4-bit address and later it carries status signals.

S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the
transfer of data using data bus D8-D15. This signal is low during the first clock cycle,
thereafter it is active.

Read
It is available at pin 32 and is used to read signal for Read operation.

Ready
It is available at pin 32. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is
ready to transfer data. When it is low, it indicates wait state.

RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.

INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the
last clock cycle of each instruction to determine if the processor considered this as an
interrupt or not.
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NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered
input, which causes an interrupt request to the microprocessor.

TEST
This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.

MN/MAX
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processor is to operate in; when it is high, it works in the minimum mode and vice-a-
versa.

INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.

ALE
It stands for address enable latch and is available at pin 25. A positive pulse is
generated each time the processor begins any operation. This signal indicates the
availability of a valid address on the address/data lines.

DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver
8286. The transreceiver is a device used to separate data from the address/data bus.

DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the
direction of data flow through the transreceiver. When it is high, data is transmitted out
and vice-a-versa.

M/IO
This signal is used to distinguish between memory and I/O operations. When it is high,
it indicates I/O operation and when it is low indicates the memory operation. It is
available at pin 28.

WR
It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.

HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.

HOLD
This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.

QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals provide
the status of instruction queue.

S0, S1, S2
These are the status signals that provide the status of operation, which is used by the
Bus Controller 8288 to generate memory & I/O control signals. These are available at
pin 26, 27, and 28. '

LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to
leave the system bus. It is activated using the LOCK prefix on any instruction and is
available at pin 29.
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RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors requesting the CPU to
release the system bus. When the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
14 6

15 PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its 6
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor. It consists of three 8-bit bidirectional
I/O ports i.e. PORT A, PORT B and PORT C. We can assign different ports as input or output
functions. Block diagram –

It consists of 40 pins
and operates in +5V regulated power supply. Port C is further divided into two 4-bit ports i.e.
port C lower and port C upper and port C can work in either BSR (bit set rest) mode or in mode
0 of input-output mode of 8255. Port B can work in either mode 0 or in mode 1 of input-output
mode. Port A can work either in mode 0, mode 1 or mode 2 of input-output mode. It has two
control groups, control group A and control group B. Control group A consist of port A and
port C upper. Control group B consists of port C lower and port B. Depending upon the value if
CS’, A1 and A0 we can select different ports in different modes as input-output function or
BSR. This is done by writing a suitable word in control register (control word D0-D7).
16 The digital to analog converters convert binary numbers into their analog equivalent voltages. 6
The DAC find applications in areas like digitally controlled gains, motor speed controls,
programmable gain amplifiers, etc. (3)
Explain any one IC in detail .(9)
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17 6
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18 Square Wave Generation using DAC 6

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19

Block Explanation
20 8086 Register Addressing Modes  12
8086 Memory Addressing Modes
o The Displacement Only Addressing Mode
o The Register Indirect Addressing Modes
o Indexed Addressing Modes
o Based Indexed Addressing Modes
o Based Indexed Plus Displacement Addressing Mode
. 8086 Register Addressing Modes
mov destination, source
This instruction copies the data from the source operand to the destination operand. The eight
and 16 bit registers are certainly valid operands for this instruction.
mov ax, bx ;Copies the value from BX into AX
mov dl, al ;Copies the value from AL into DL
The Displacement Only Addressing Mode
The displacement-only addressing mode consists of a 16 bit constant that specifies the address
of the target location. The instruction mov al,ds:[8088h] loads the al register with a copy of the
byte at memory location 8088h
The Register Indirect Addressing Modes
The 80x86 CPUs let you access memory indirectly through a register using the register indirect
addressing modes. There are four forms of this addressing mode on the 8086, best demonstrated
by the following instructions:
mov al, [bx] mov al, [bp] mov al, [si] mov al, [di]
The indexed addressing mode
The indexed addressing modes use the following syntax:
mov al, disp[bx] mov al, disp[bp] mov al, disp[si] mov al, disp[di]
If bx contains 1000h, then the instruction mov cl,20h[bx] will load cl from memory location
ds:1020h. Likewise, if bp contains 2020h, mov dh,1000h[bp]
will load dh from locationss:3020.
Based Indexed Addressing Modes
The based indexed addressing modes are simply combinations of the register indirect
addressing modes. These addressing modes form the offset by adding together a base register
(bx or bp) and an index register (si or di). The allowable forms for these addressing modes are
mov al, [bx][si] mov al, [bx][di]
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Based Indexed Plus Displacement Addressing Mode

These addressing modes are a slight modification of the base/indexed addressing modes with
the addition of an eight bit or sixteen bit constant. The following are some examples of these
addressing modes:
mov al, disp[bx][si]
mov al, disp[bx+di]

21 12
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22 Loosely Coupled Configuration: In this type of configuration, there are several complete 12
computer systems with their own memory, I/O devices, CPU and operating system.

Symmetric Configuration

Advantages –
 It is more reliable than loosely coupled configuration.
 It uses the resources effectively.
 It well manages the load of jobs.
 It can degrade gracefully at the time of failure.
Disadvantages –
 Whenever a process is interrupted, it’s processor updates the corresponding
entry in the process list and finds another process to run. This means that not
only all the processors are kept busy, but also other processors may also be
executing that job (like I/O request) at the same time. This increases the chances
of conflict between processors.
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 It is the most difficult configuration to implement, as the system must be well

synchronized as to avoid any type of races or deadlocks.

23 12

PIN DIAGRAM

Explanation
24 Direct memory access(DMA) :- It is a method that allows an input/output (I/O) device 12
to send or receive data directly to or from the main memory, by passing the CPU to
speed up memory operations. The process is managed by a chip known as a DMA
controller (DMAC).
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DMA Controller: The DMA controller needs the usual circuits of an interface to communicate
with the CPU and I/O device. The DMA controller has three registers:
i.Address Register :- Address Register contains an address to specify the desired location in
memory.
ii. Word Count Register :- WC holds the number of words to be transferred. The register is
incre/decre by one after each word transfer and internally tested for zero.
iii. Control Register :- Control Register specifies the mode of transfer
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25 12

8051: 16 bit Microcontroller

on chip ROM( 8KB) and On chip RAM (128 bytes)
two 16 bit timer/counter.
four 8-bit ports for input/output
fully duplex serial receiver/transmitter.
no prefetching of instruction.
16 address pins
8086: 16 bit Microprocessor
No on chip memory.
memory is divided into two banks to increase the processing speed.
prefetching of 6 bytes of instruction in a queue.
20 address pins
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26 12

27 STEPPER MOTOR 12

A stepper motor is a brushless, synchronous electric motor that converts digital pulses into
mechanical shaft rotation. Every revolution of the stepper motor is divided into a discrete number of
steps, and the motor must be sent a separate pulse for each step.

Stepper motors can be used in various areas of your microcontroller projects such as making
robots, robotic arm, and automatic door lock system.

Fig. shows how to interface the Stepper Motor to microcontroller. As you can see the stepper
motor is connected with Microcontroller output port pins through a ULN2803A array. So when the
microcontroller is giving pulses with particular frequency to ls293A, the motor is rotated in clockwise or
anticlockwise.

Step Angle
Step angle of the stepper motor is defined as the angle traversed by the motor in one step.

 To calculate step angle, simply divide 360 by number of steps a motor takes to complete one
revolution.

 Motor rotating in full mode takes 4 steps to complete a revolution ,so step angle can be
calculated as step angle θ = 360° / 4 =90.
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MOV A, #66H Load step sequence

BACK: MOV P1, A Issue sequence
motor
RR A Rotate right
clockwise
ACALL DELAY Wait
SJMP BACK Keep going
…………….
DELAY
MOV R2, #100H
H1: MOV R3, #255H H1:
H2: DJNZ R3, H2 H2:
DJNZ R2, H1
RET
28 8 +4

ORG 00H
MOV P1,#11111111B // initiates P1 as the input port
MAIN: CLR P3.7 // makes CS=0
SETB P3.6 // makes RD high
CLR P3.5 // makes WR low
SETB P3.5 // low to high pulse to WR for starting conversion
WAIT: JB P3.4,WAIT // polls until INTR=0
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CLR P3.7 // ensures CS=0

CLR P3.6 // high to low pulse to RD for reading the data from ADC
MOV A,P1 // moves the digital data to accumulator
CPL A // complements the digital data (*see the notes)
MOV P0,A // outputs the data to P0 for the LEDs
SJMP MAIN // jumps back to the MAIN program
END

Prepared by
Reviewed and Approved by HOD:
Subject In charge: R.G.Balaji

*Key words / Formula / Diagram / Definitions etc., - as appropriate