MODULE 3

CMOS PROCESSING THECNOLOGY

Wafer Processing:

• Silicon wafers are thin, round disks used as the foundation for making electronic
chips.
• The size of these wafers can vary from 75 mm to 300 mm in diameter, and they are
extremely thin (less than 1 mm thick).
• Wafers come from ingots (large cylindrical blocks of silicon).
• These ingots are made using the Czochralski process, where pure silicon is melted
and then slowly solidified into a single crystal.
• The ingots are then sliced into thin wafers.
• The Czochralski (CZ) method is the most widely used process for making pure
silicon crystals.
• It ensures that the silicon forms a single, continuous crystal structure, which is
essential for high-performance electronic devices.
• The crucible (container that holds the molten silicon) is made of quartz.
• Quartz is used because it can withstand high temperatures without contaminating
the silicon.
• A seed crystal (a small, pure silicon piece) is dipped into the molten silicon.
• The seed is slowly pulled up while rotating, which helps in forming a uniform and
defect-free crystal.
• After the silicon ingot is fully formed, it is shaped using grinding machines.
• This ensures that the ingot has a uniform diameter before slicing.
• The ingot is cut into thin wafers using a special saw.
• The wafers are then polished until they have a smooth, mirror-like surface.
• This smoothness is necessary for making precise electronic circuits.
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Oxidation:
• The silicon oxidation process involves exposing silicon wafers to oxygen or water
vapor at high temperatures to form a silicon dioxide (SiO₂) layer.
• There are two primary methods for oxidizing silicon:
• Wet oxidation:
• Wet oxidation involves using water vapor (H₂O) as the oxidizing agent.
• This process operates at high temperatures.
• Wet oxidation grows the oxide layer faster than dry oxidation.
• Dry oxidation:
• Dry oxidation uses O₂ gas without water vapor.
• This method requires higher temperatures than wet oxidation to form an oxide layer at
a reasonable rate.
• When silicon is oxidized, a part of the silicon reacts with oxygen to form SiO₂,
reducing the thickness of the silicon substrate.
• Silicon dioxide takes up more space than the original silicon, causing the oxide layer
to extend above the silicon surface while also penetrating into the silicon.
• The field oxide extends both upwards and into the silicon, demonstrating the
volumetric expansion of SiO₂.
• The gate oxide is thinner than the field oxide, showing its role in MOS transistor
functionality.
• The source and drain regions are separated by the field oxide and controlled by the
poly gate.
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Selective Diffusion:

Selective Diffusion and Photolithography Process Explanation

1. Purpose of Selective Diffusion

Selective diffusion is used in semiconductor fabrication to create different types of silicon with
precise placement of dopant atoms. This process involves the use of SiO₂ as a barrier to control
where dopants enter the silicon wafer.

2. Steps Involved in Selective Diffusion

1. Growth of SiO₂ Layer

o A thin layer of silicon dioxide (SiO₂) is grown on the silicon wafer surface.
o This SiO₂ layer prevents dopants from entering the silicon except in selected areas.
2. Patterning SiO₂ Using Photolithography
o A photoresist (PR) layer is applied on top of the SiO₂.
o A glass mask with a pattern is placed over the wafer.
o UV light is shined onto the wafer.
o The areas of PR exposed to UV light undergo a chemical reaction, either hardening
(negative PR) or becoming removable (positive PR).
3. Etching of SiO₂
o The developed photoresist is used as a mask, allowing selective etching of SiO₂.
o The exposed SiO₂ areas are removed, creating windows where diffusion will occur.
4. Doping the Exposed Silicon
o Dopant atoms are introduced into the exposed silicon through diffusion or ion
implantation.
o The presence or absence of SiO₂ determines where the dopants enter.
5. Photoresist Removal
o The remaining photoresist is removed, leaving the patterned SiO₂ on the wafer.
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o The silicon now has precisely doped regions, forming the basis for transistors and
other semiconductor devices.

Advantages of Electron Beam Lithography (EBL) Over Traditional

Photolithography

Recent advancements consider electron beam lithography (EBL) as a more precise alternative:

1. No Need for Physical Masks

o Unlike traditional photolithography, EBL does not require masks or reticles.
o The pattern is generated directly using an electron beam.
2. Flexibility in Patterning
o Different patterns can be applied in different sections of the wafer without the need
for multiple masks.
3. Rapid Design Changes
o Since patterns are generated digitally, modifications can be made quickly without
creating new physical masks.

Disadvantages of Electron Beam Lithography (EBL)

Despite its advantages, EBL is not widely used in commercial semiconductor production due to:

1. High Equipment Costs

o EBL machines are significantly more expensive than traditional photolithography
equipment.
2. Slow Processing Time
o EBL exposes patterns point by point (serially), making it much slower than
photolithography, which processes an entire wafer at once using a mask.
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Fabrication Steps for a Silicon Gate nMOS Transistor:

The fabrication of an nMOS transistor involves several key steps in semiconductor

processing. Each step is crucial in defining the structure and electrical properties of the
transistor. Here is a detailed explanation of each step shown in above Figure:

1. Patterning SiO₂ Layer (Field Oxidation)

• The process starts with a p-type silicon substrate.

• A layer of silicon dioxide (SiO₂) is grown on the surface to act as a protective mask.
• Using photolithography, parts of this oxide layer are selectively etched away to
define the regions where the transistor's active components will be formed.

2. Gate Oxidation

• A thin oxide layer (~200–400 Å thick) is grown in the areas where the gate of the
transistor will be placed.
• This oxide layer forms the gate dielectric (insulator) that separates the transistor's
gate from the silicon substrate.
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3. Patterning Polysilicon (Gate Formation)

• A polysilicon layer (~1μm–2μm thick) is deposited over the entire wafer.

• Using photolithography and etching, the polysilicon is patterned to form the gate
electrode of the transistor.
• This polysilicon gate will later help define the source and drain regions.

4. Diffusion or Implantation of Dopants (Source & Drain Formation)

• The thin oxide layer acts as a mask, ensuring that doping only occurs where needed.
• N-type dopants (such as phosphorus or arsenic) are introduced into the silicon
substrate in the exposed regions (areas not covered by polysilicon).
• This forms the source and drain regions of the nMOS transistor.
• The doping depth is about 1 μm.

5. Contact Cuts (Etching for Metal Contacts)

• Openings are made in the SiO₂ layer to allow metallic contacts to connect the
transistor terminals (source, drain, and gate).
• This is done using another photolithography and etching step.

6. Patterning Aluminum (Metal Connections)

• A thin layer of aluminum is deposited over the wafer.

• Using photolithography and etching, the aluminum is patterned to form metal
interconnections that link different transistors and complete the circuit.
• The remaining structure is then coated with a final protective SiO₂ layer.
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CMOS Technologies
The p-Well Process:
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Step 1: Formation of the P-Well

• The process begins with an n-type silicon substrate.

• A p-well mask is used to define the region where the p-well will be formed.
• Boron ions (p-type dopant) are implanted into the defined area to create a p-well,
which will house n-channel transistors (NMOS).

Step 2: Field Oxide (FOX) Growth

• A thick layer of silicon dioxide (SiO₂) is grown over the wafer using thermal
oxidation.
• This oxide layer acts as an insulator, preventing unwanted electrical connections.
• Etching is performed to remove SiO₂ from areas where transistors will be placed.

Step 3: Thin Oxide (Gate Oxide) Formation

• A very thin layer (~500 Å) of SiO₂ (thin oxide) is grown in transistor regions.
• This thin oxide layer serves as the gate oxide for transistors.
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Step 4: Polysilicon Gate Formation

• A layer of polysilicon is deposited over the entire wafer.

• Using a polysilicon mask, photolithography and etching define polysilicon gate
structures.
• These gates control the transistor’s operation.

Step 5: Source and Drain Diffusion

• A p+ or n+ mask is used to define source and drain regions.

• If in the p-well, n+ doping (phosphorus or arsenic) is applied to create NMOS
transistors.
• If in the n-substrate, p+ doping (boron) is applied to create PMOS transistors.

Step 6: Contact Cut Definition

• Openings (contact cuts) are made in the oxide layer where metal connections will be
placed.

Step 7: Metallization (Interconnections)

• A layer of aluminum metal is deposited to create interconnections between

transistors.
• A metal mask is used to etch the metal layer, forming the circuit layout.

Step 8: Final Passivation Layer

• A protective passivation layer (SiO₂ or Si₃N₄) is added to protect the circuit from
contaminants.
• Openings are made for bonding pads to connect the chip to external circuits.

This process enables the creation of CMOS circuits, combining NMOS and PMOS
transistors for efficient digital logic operations.