7/2/25, 4:47 PM Untitled1.

ipynb - Colab

United International University

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QUESTION 1: 8086 Timing Diagram for I/O Write Operation
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The I/O write operation uses multiplexed address/data pins and control signals over 4 clock cycles (T1-T4).

Key Activities:
- T1:
• 20-bit I/O address output (A19-A16/S6-S3: high nibble, AD15-AD0: low 16 bits)
• ALE pulses high to latch address
• M/IO=0 (I/O mode), DT/R=1 (transmit)
- T2-T3:
• AD15-AD0 carries write data
• WR=0 (write active), DEN=0 (enable data bus)
- T4:
• Signals return idle (WR=1, DEN=1)

Timing Diagram...

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7/2/25, 4:47 PM Untitled1.ipynb - Colab

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QUESTION 2: BIU and EU Cycles (Case a (2nd=JUMP to 5th, 4th=JUMP to 7th, 6th=MOV))
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+---------+---------------+---------------+------------------+---------------------+
| Cycle | BIU Fetches | EU Executes | Prefetch Queue | Notes |
+=========+===============+===============+==================+=====================+
| 1 | Inst1 (Addr1) | Idle | [1] | Initial fetch |
+---------+---------------+---------------+------------------+---------------------+
| 2 | Inst2 (Addr2) | Inst1 | [1,2] | |
+---------+---------------+---------------+------------------+---------------------+
| 3 | Inst3 | JUMP (Inst2) | [1,2,3] | Queue flushed! |
+---------+---------------+---------------+------------------+---------------------+
| 4 | Inst5 (Addr5) | Idle | [5] | BIU redirected to 5 |
+---------+---------------+---------------+------------------+---------------------+
| 5 | Inst6 (Addr6) | Inst5 | [5,6] | |
+---------+---------------+---------------+------------------+---------------------+
| 6 | Inst7 (Addr7) | MOV (Inst6) | [5,6,7] | |
+---------+---------------+---------------+------------------+---------------------+
| 7 | Inst8 | Inst7 | [5,6,7,8] | Inst8 unused |
+---------+---------------+---------------+------------------+---------------------+

Key Observations:
- Cycle 3: JUMP flushes queue (Inst3 discarded)
- Cycle 4: EU idle during redirection
- Inst4 never executed
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7/2/25, 4:47 PM Untitled1.ipynb - Colab

================================================================================
QUESTION 2: BIU and EU Cycles (Case b (2nd=MOV, 4th=JUMP to 7th, 6th=JUMP to 3rd))
================================================================================
+---------+---------------+---------------+------------------+---------------------+
| Cycle | BIU Fetches | EU Executes | Prefetch Queue | Notes |
+=========+===============+===============+==================+=====================+
| 1 | Inst1 (Addr1) | Idle | [1] | |
+---------+---------------+---------------+------------------+---------------------+
| 2 | Inst2 (Addr2) | Inst1 | [1,2] | |
+---------+---------------+---------------+------------------+---------------------+
| 3 | Inst3 (Addr3) | MOV (Inst2) | [1,2,3] | |
+---------+---------------+---------------+------------------+---------------------+
| 4 | Inst4 (Addr4) | Inst3 | [2,3,4] | |
+---------+---------------+---------------+------------------+---------------------+
| 5 | Inst5 | JUMP (Inst4) | [2,3,4,5] | Queue flushed! |
+---------+---------------+---------------+------------------+---------------------+
| 6 | Inst7 (Addr7) | Idle | [7] | BIU redirected to 7 |
+---------+---------------+---------------+------------------+---------------------+
| 7 | Inst8 | Inst7 | [7,8] | Inst6 never fetched |
+---------+---------------+---------------+------------------+---------------------+

Key Observations:
- Cycle 5: JUMP flushes queue (Inst5 discarded)
- Cycle 6: EU idle during redirection
- Inst6 JUMP never executed
- Backward jump to 3rd never occurs due to prior flush

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ANALYSIS
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1. Pipeline Behavior:
- Jumps cause pipeline bubbles (EU idle cycles)
- Queue flushing leads to wasted fetches

2. Jump Handling:
- Forward jumps execute correctly after redirection
- Backward jumps may be missed if queue was flushed

3. BIU-EU Synchronization:
- EU stalls when queue is empty
- BIU continuously fetches unless redirected

4. Timing Diagram Insights:

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