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Digital Code

The document contains various Verilog modules and their corresponding test benches for digital circuits, including a four-bit adder, a 32-bit ALU, a multiplier, a Mod-N counter, and different types of flip-flops (D, JK, SR). Each module is defined with its inputs, outputs, and functionality, while the test benches provide a framework for simulating and verifying the behavior of these modules. The document serves as a comprehensive resource for understanding and testing basic digital circuit designs.

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puneeth04aiet
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4 views8 pages

Digital Code

The document contains various Verilog modules and their corresponding test benches for digital circuits, including a four-bit adder, a 32-bit ALU, a multiplier, a Mod-N counter, and different types of flip-flops (D, JK, SR). Each module is defined with its inputs, outputs, and functionality, while the test benches provide a framework for simulating and verifying the behavior of these modules. The document serves as a comprehensive resource for understanding and testing basic digital circuit designs.

Uploaded by

puneeth04aiet
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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1.

Four Bit Adder:


Source Code:
module four_bit_adder (a,b,c0,s,c4);
input [3:0]a,b;
input c0;
output[3:0]s;
output c4;
wire c1,c2,c3;
full_adder f0(a[0],b[0],c0,s[0],c1);
full_adder f1(a[1],b[1],c1,s[1],c2);
full_adder f2(a[2],b[2],c2,s[2],c3);
full_adder f3(a[3],b[3],c3,s[3],c4);
endmodule
module full_adder(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
assign s=a^b^cin;
assign cout = (a&b)|(b&cin)|(a&cin);
endmodule

Test Bench:
module four_tb;
reg[3:0]a,b;
reg c0;
wire [3:0]s;
wire c4;
four_bit_adder dut(a,b,c0,s,c4);
initial begin
a=4'b0011;
b=4'b0011;
c0=1'b0;
#10;
a=4'b1011;
b=4'b1011;
c0=1'b1;
#10;
a=4'b1111;
b=4'b1111;
c0=1'b1;
#10;
end initial
#50 $finish;
endmodule

2. 32-ALU:
Source Code:
module alu_32bit_case(y,a,b,f);
input[31:0]a;
input[31:0]b;
input[2:0]f;
output reg[31:0]y;
always@(*)
begin
case(f)
3'b000:y=a&b;
3'b001:y=a|b;
3'b010:y=~(a&b);
3'b011:y=~(a|b);
3'b010:y=a+b;
3'b011:y=a-b;
3'b100:y=a*b;
default:y=32'bx;
endcase
end
endmodule

Test Bench:
module alu_32bit_tb_case;
reg[31:0]a;
reg[31:0]b;
reg[2:0]f;
wire[31:0]y;
alu_32bit_case uut(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10f=3'b000;
#10f=3'b001;
#10f=3'b010;
#10f=3'b100;
end
initial
#50 $finish;
Endmodule

3. Multiplier:
Source Code:
module multiplier(clk,rst,a,b,c);
parameter m=4,n=4;
integer i;
input clk,rst;
input [m-1:0] a;
input [n-1:0] b;
output reg [m1:0]c;
reg [m1:0]a1;
reg [n-1:0]b1;
always@(posedge clk or posedge rst )
begin
if (rst)
begin
c=0;
end
else
begin
c=0;
a1[m-1:0]=a;
a1[m1:m]=0;
b1=b;
for(i=0;i<n;i=i)
begin
if(b1[i]==1'b0)
begin
c=c;
end
else if(b1[i]==1'b1)
begin
c=c(a1<<i);
end
end
end
end
endmodule

Test Bench:
module multiplier_tb;
parameter m=4,n=4;
reg clk,rst;
reg [m-1:0]a;
reg[n-1:0]b;
wire[m+n-1:0]c;
multiplier uut(clk, rst ,a,b,c);
initial
begin
clk = 1'b1;
forever #4 clk =~clk;
end
initial
begin
rst =1;
#2 rst=0;
a=4'b1111;
b=4'b1111;
#20 rst=1;
#2 rst=0;
a=4'b0011;
b=4'b0011;
#20 rst=1;
#2 rst=0;
a=4'b1100;
b=4'b0010;
#20;
end
initial
begin #100 $finish;
end
endmodule

4. Mod-N Counter:
Source Code:
module modn_ctr
# (parameter n =10,
parameter width = 4)
(input clk,
input rstn,
output reg[width-1:0] out);
always @(posedge clk) begin
if(!rstn)begin
out <=0;
end else begin
if(out ==n-1)
out <=0;
else
out<=out+1;
end
end
endmodule

Test Bench:
module tb;
parameter n=10;
parameter width=4;
reg clk;
reg rstn;
wire [width-1:0]out;
modn_ctr u0 ( .clk(clk),.rstn(rstn),.out(out));
always #10 clk=~clk;
initial begin
{clk,rstn}<=0;
$monitor("T=%0t rstn=%0b out=0x%0h",$time,rstn,out);
repeat(2) @(posedge clk);
rstn <=1;
repeat(2) @(posedge clk);
$finish;
end
endmodule
5. Flip-Flops:
1. D Flip-flop
Source Code:
module dff (d, clk, reset, q, qbar);
output reg q;
output reg qbar;
input d, clk, reset;
always @(posedge clk or reset)
begin
if(!reset)
assign q=d;
else
assign q=0;
assign qbar=~q;
end
endmodule

Test Bench:
module dff tb;
reg d, clk, reset;
wire q, qbar;
dff uut(.d(d),.clk(clk),.reset (reset),.q(q),.qbar (qbar));
initial begin
d=0；
clk=0;
reset=0;
#100；
d=1;
clk=1;
reset=1;
#100；
d=0；
clk=1;
reset=0;
#100；
d=1;
clk=1;
reset=0;
#100；
end
endmodule

2. JK Flip-Flop
Source Code:
module jk_ff(input reset,input clk,input j,input k,output reg q,output reg qbar);
always@(posedge clk or posedge reset)begin
if(reset) begin
q <=0;
qbar<=1;
end else begin
case({j,k})
2'b00: begin
q<=q;
qbar<=qbar;
end
2'b01: begin
q<=0;
qbar<=1;
end
2'b10: begin
q<=1;
qbar<=0;
end
2'b11: begin
q<=~q;
qbar<=~qbar;
end
endcase
end
end
endmodule
Test Bench:
module jk_ff_tb;
reg clk,j,k,reset;
wire q,qbar;
jk_ff uut(.reset(reset),.clk(clk),.j(j),.k(k),.q(q),.qbar(qbar));
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;j=0;k=0;#10;
reset=0;
j=0;k=0;#10;
j=0;k=1;#10;
j=1;k=0;#10;
j=1;k=1;#10;
j=1;k=1;#10;
$finish;
end
endmodule

3. SR Flip-Flop:
Source Code:
module SR(q,q1,S,R,clk);
output q,q1;
input R,S,clk;
reg q,q1;
initial
begin
q=1'b0;q1=1'b1;
end
always@(posedge clk)
begin
case({S,R})
{1'b0,1'b0}:begin q=q;q=q1;end
{1'b0,1'b1}:begin q=1'b0;q1=1'b1;end
{1'b1,1'b0}:begin q=1'b1;q1=1'b0;end
{1'b1,1'b1}:begin q=1'bx;q1=1'bx;end
endcase
end
endmodule

Test Bench:
module SR_tb;
reg clk=0;
reg S=0;
reg R=0;
wire q,qnot;
SR dut(q,qnot,S,R,clk);
initial
begin
S=1'b1;
R=1'b1;
#25 $finish;
end
always#1 clk=~clk;
endmodule

csh
source /home/install/cshrc
mkdir ece
cd ece
gedit gate.v
gedit gate_tb.v
nclaunch

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