COS 212 Computer Architecture and Organization (2 Units C: LH 15; PH 45)

Course Contents

Principles of computer hardware and instruction set architecture. Internal CPU organization and implementation.
Instruction format and types, memory, and I/O instructions. Dataflow, arithmetic, and flow control instructions,
addressing modes, stack operations, and interrupts. Data path and control unit design. RTL, microprogramming and
hardwired control. The practice of assembly language programming. Memory hierarchy. Cache memory, Virtual
memory. Cache performance. Compiler support for cache performance. I/O organisations. Lab work: Practical
demonstration of the architecture of a typical computer. Illustration of different types of instructions and how they
are executed. Simple Assembly Language programming. Demonstration of interrupts. Programming assignments to
practice MS-DOS batch programming, Assembly Process, Debugging, Procedures, Keyboard input, Video Output,
File and Disk I/O, and Data Structure. Demonstration of Reduced Instruction Set Computers. Illustration of parallel
architectures and interconnection networks.

Computer Architecture:
Computer Architecture deals with giving operational attributes of the computer or Processor to be specific.
It deals with details like physical memory, ISA (Instruction Set Architecture) of the processor, the number
of bits used to represent the data types, Input Output mechanism and technique for addressing memories.
Computer Organization:
Computer Organization is realization of what is specified by the computer architecture .It deals with how
operational attributes are linked together to meet the requirements specified by computer architecture. Some
organizational attributes are hardware details, control signals, peripherals.

FUNDAMENTALS OF COMPUTER ARCHITECTURE

The Basic Computer Architectures Computer is an electronic machine that performs any task very easily.
In computer, the Central Processing Unit (CPU) executes each instruction provided to it, in a series of steps,
this series of steps is called Machine Cycle, and is repeated for each instruction. One machine cycle involves
fetching of instruction, decoding the instruction, transferring the data, executing the instruction.
The main components in a typical computer system are the Processor, Memory, Input/Output Devices and
the communication channels that connect them.
• The Processor: It is the workhorse of the system; it is the component that executes a program by
performing Arithmetic and Logical operations on data. It is the only component that creates new
information by combining or modifying current information. In a typical system there will be only one
processor, known as the Central Processing Unit (CPU). Modern high performance systems such as vector
processors and parallel processors often have more than one processor. Systems with only one processor
are serial processors especially among computational scientists, scalar processors.
• Memory: It is a passive component that simply stores information until it is requested by another part of
the system. During normal operations it feeds instructions and data to the processor and at other times. It is
the source or destination of data transferred by I/O devices. Information in a memory is accessed by its
address. In programming language terms, one can view memory as a one-dimensional array M. A
processor's request to the memory might be ``send the instruction at location M [1000]'' or a disk controller's
request might be ``store the following block of data in locations M[0] through M[255].

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• Input/Output (I/O) Devices: This transfer information without altering it between the external world and
one or more internal components. I/O devices can be secondary memories, for example disks and tapes, or
devices used to communicate directly with users, such as video displays, keyboards, and mouse.
• The Communication Channels: This ties the system together which can either be simple links that connect
two devices or more complex switches that interconnect several components. This allows them to
communicate at a given point in time. When a switch is configured to allow two devices to exchange
information, all other devices that rely on the switch are blocked, i.e. they must wait until the switch can be
reconfigured.

Figure 1: Block Diagram of a Computer System

Instruction Set Architecture

Overview - An Instruction Set Architecture (ISA) defines the interface between software and hardware.
Software is converted to machine instructions using software (compiler/interpreter). Then the instructions
are executed using hardware.
Instruction set architecture is the structure of a computer that a machine language programmer (or a
compiler) must understand to write a correct (timing independent) program for that machine.
Class ISA types: Stack, Accumulator, and General General-purpose register
- An ISA contains
• the functional definition of storage locations (registers, memory) & operations (add, multiply, branch,
load, store, etc)
• precise description of how to invoke & access them - ISA does not contain: non-functional aspects • How
operations are implemented
• Which operations are fast and which are slow
• Which operations take more power and which take less - Instructions are bit-patterns. Hardware interprets
as commands.
Basic ISA classes - We know that hardware decides the instruction format. Internal storage space in a
processor is a factor impacting an ISA.

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- Instructions are to execute operations that will take one or more operands.
– Based on where the operands are stored and whether they are named explicitly or implicitly, the ISA can
be classified as Stack Architecture, Accumulator Architecture, and Register-set Architecture.
Stack Architecture - The operands are put into the stack. Operations take place at the top two locations on
the stack, destroying the operands, and leaving the result on the top of the stack. - Stack is a block of
memory in RAM, but CPU keeps a stack pointer register points to the top of the stack. Data in stack are
first-in last-out.
- Two operations, push and pop, have one operand. Push a value at the top of the stack, or pop the top
element of the stack to a destination. Other operations have implicit operands, which are the top element(s)
of the stack. To perform an operation, the operands are pushed into the stack first. Once performed an
operation, its operand(s) are deleted from the stack, and its result is stored at the top of the stack. Then, it
can use pop command to store the result back to the memory. - This architecture was used in computers in
1960s
- Suppose we want to ask a stack architecture machine to conduct the operation
C = A + B, where A, B, and C are memory addresses. The result of A + B are stored at location C.
- Then, to implement the operation in a stack architecture, we need the following steps:
PUSH A # push value at location A to the top of the stack
PUSH B # push value at location B to the top of the stack
ADD # add the top two elements of the stack and save the result back to the top of the stack
POP C # store the value at the top of the stack (which is the result) to location C
Accumulator Architecture
- It places one operand in the accumulator and one in memory. The one in the accumulator is implicit, and
the one in the memory is an explicit memory address. The result of ALU is written back to the accumulator.
- The operand in the accumulator is loaded from memory using the command LOAD, and the result is
stored in memory from accumulator using the command STORE.
- This architecture was used by early computers like IBM 7090. Today, it’s used by some microprocessor
chips, such as some digital signal processors. - Suppose we want to ask an accumulator architecture machine
to conduct the same operation C = A + B as above.
- Then, to implement the operation in an accumulator architecture, we need the following steps:
LOAD A # load value at location A from main memory to ACC
ADD B # fetch the v
alue at location B, add it with the value at ACC (which is the value A), and save the result back to ACC
STORE C # store the value at ACC (which is the result of A + B) to location C
Register-set Architecture
- It’s the dominant architecture used by modern computers.
- Modern CPUs have a number of general-purpose registers (GPRs) for internal storage, at least 8 and as
many as 32.
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Computer Processing Unit Organization
Introduction to CPU
The operation or task that must perform by CPU is:
• Fetch Instruction: The CPU reads an instruction from memory.
• Interpret Instruction: The instruction is decoded to determine what action is required.
• Fetch Data: The execution of an instruction may require reading data from memory or I/O module.
• Process data: The execution of an instruction may require performing some arithmetic or logical operation
on data.
• Write data: The result of an execution may require writing data to memory or an I/O module.
To do these tasks, it should be clear that the CPU needs to store some data temporarily. It must remember
the location of the last instruction so that it can know where to get the next instruction. It needs to store
instructions and data temporarily while an instruction is being executed. In other words, the CPU needs a
small internal memory. These storage locations are generally referred as registers.
The major components of the CPU are an arithmetic and logic unit (ALU) and a control unit (CU). The
ALU does the actual computation or processing of data. The CU controls the movement of data and
instruction into and out of the CPU and controls the operation of the ALU.
The CPU is connected to the rest of the system through system bus. Through system bus, data or
information gets transferred between the CPU and the other component of the system. The system bus may
have three components:
Data Bus: Data bus is used to transfer the data between main memory and CPU.
Address Bus: Address bus is used to access a particular memory location by putting the address of the
memory location.
Control Bus: Control bus is used to provide the different control signal generated by CPU to different part
of the system.
As for example, memory read is a signal generated by CPU to indicate that a memory read operation has
to be performed. Through control bus this signal is transferred to memory module to indicate the required
operation.

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Figure 1: CPU with the system bus.
There are three basic components of CPU: register bank, ALU and Control Unit. There are several data
movements between these units and for that an internal CPU bus is used. Internal CPU bus is needed to
transfer data between the various registers and the ALU.

Figure 1: Internal Structure of CPU

What is Computer Architecture?

Computer Architecture is a set of rules and methods that describe the functionality, organisation and
implementation of computer systems. Some definitions of architecture define it as describing the
capabilities and programming model of a computer but not a particular implementation.
Computer Architecture can also be defined as the design methodology of how computer hardware
components interact based on the challenges imposed by real world components and technology and also
depends on the current market demands.
Building an architecture deals with the materials (components, subsystems) at hand and many levels of
detail are required to completely specify a given implementation, however, a very good example is von
Neumann architecture.
which is still used by most types of computers today. This was proposed by the mathematician John von
Neumann in 1945. It describes the design of an electronic computer with its CPU, which includes the
arithmetic logic unit, control unit, registers, memory for data and instructions, an input/output interface and
external storage functions. Von Neumann architecture is based on the stored-program computer concept,
where instruction data and program data are stored in the same memory. This design is still used in most
computers produced today are shown in the figure 2.

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 Fig. 2: Von Neumann Architecture

• Central Processing Unit (CPU) At the heart of any computer, modern or early, is a circuit called an
Arithmetic Logic Unit (ALU). It is comprised of a few simple operations which can be done very quickly.
This along with a small amount of memory running at processor speed called registers which make up what
is known as the Central Processing Unit (CPU). This executes the instruction of a computer program. It is
sometimes referred to as the microprocessor or processor. A CPU is not very useful unless there is some
wa y to communicate to it, and receive information back from it. This is usually known as a Bus. The Bus
is the input/output (I/O) gateway for the CPU. The primary area with which the CPU communicates with
its system memory is what is commonly known as Random Access Memory (RAM). Depending on the
platform, the CPU may communicate with other parts of the system or it may communicate just through
memory. The CPU contains the ALU, Control Unit and a variety of registers.
• Memory Unit The memory unit consists of RAM, sometimes referred to as primary or main memory.
Unlike a hard drive (secondary memory), this memory is fast and also directly accessible by the CPU. RAM
is split into partition, each partition consists of an address and its contents (both in binary form). The address
will uniquely identify every location in the memory. Loading data from permanent memory (hard drive),
into the faster and directly accessible temporary memory (RAM) allows the CPU to operate much quicker
Registers
Registers are high speed storage areas in the CPU. All data and instruction must be stored in a register
before it can be processed. A Register is a group of flip-flops with each flip-flop capable of storing one bit
of information. An n-bit register has a group of n flip-flops and is capable of storing binary information of
n-bits.
A register consists of a group of flip-flops and gates. The flip-flops hold the binary information and gates
control when and how new information is transferred into a register. Various types of registers are available
commercially. The simplest register is one that consists of only flip-flops with no external gates. These
days’ registers are also implemented as a register file such as:
• Register Load: The transfer of new information into a register is referred to as loading the register.
If all the bits of register are loaded simultaneously with a common clock pulse than the loading is
said to be done in parallel.
• Register Transfer Language: The symbolic notation used to describe the micro-operation transfers
amongst registers is called register transfer language. The term "register transfer" means the
availability of hardware logic circuits that can perform a stated micro-operation and transfer the
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 result of the operation to the same or another register. The word "language" is borrowed from
programmers who apply this term to programming languages. This programming language is a
procedure for writing symbols to specify a given computational process.
Following are some commonly used registers:
• Accumulator: This is the most common register, used to store data taken out from the memory.
• General Purpose Registers: This is used to store data intermediate results during program execution. It
can be accessed via assembly programming.
• Special Purpose Registers: Users do not access these registers. These registers are for Computer system,
➢ MAR: Memory Address Register are those registers that holds the address for memory unit.
➢ MBR: Memory Buffer Register stores instruction and data received from the memory and sent from
the memory.
➢ PC: Program Counter points to the next instruction to be executed.
➢ IR: Instruction Register holds the instruction to be executed.

Table 1: Types of Register

Memory Address Register (MAR) Holds the memory location of data that
need to be accessed
Memory Data Register (MDR Holds data that is being transferred to or
from memory
Accumulator (ACC) Where intermediate arithmetic and logic
results are stored
Program Counter Current Contains the address of the next
Instruction Register instruction to be executed
Current Instruction Register (CIR) Contains the current instruction during
processing

Micro-Operations The operations executed on data stored in registers are called micro-operations. A
microoperation is an elementary operation performed on the information stored in one or more registers.
Example: Shift, count, clear and load.
Types of Micro-Operations
The micro-operations in digital computers are of 4 types:
1. Register Transfer Micro-Operations: Ttransfer binary information from one register to another.
2. Arithmetic Micro-Operations: Perform arithmetic operations on numeric data stored in registers.
3. Logic Micro-Operations: Perform bit manipulation operation on non-numeric data stored in registers. 4.
Shift Micro-Operations: Perform shift micro-operations performed on data.
• Register Transfer Micro-Operations
Information transferred from one register to another is designated in symbolic form by means of
replacement operator.

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R2 ← R1; It denotes the transfer of the data from register R1 into R2. Normally we want the transfer to
occur only in predetermined control condition. This can be shown by following if-then statement: if (P=1)
then (R2 ← R1)
P is a control signal generated in the control section.
Control Function A control function is a Boolean variable that is equal to 1 or 0. The control function is
shown as:
P: R2 ← R1 The control condition is terminated with a colon. It shows that transfer operation can be
executed only if P=1.
• Arithmetic Micro-Operations: This allows arithmetic (add, subtract etc.) and logic (AND, OR, NOT
etc.) operations to be carried out. Some of the basic micro-operations are addition, subtraction, increment
and decrement.
a) Add Micro-Operation
It is defined by the following statement: R3 → R1+ R2 The above statement instructs the data or
contents of register R1 to be added to data or content of register R2 and the sum should be transferred
to register R3.

b) Subtract Micro-Operation
Let us again take an example:
R3 → R1+ R2 +1 In subtract micro-operation, instead of using minus operator we take 1's compliment
and add 1 to the register which gets subtracted, i.e R1− R2 is equivalent to R3 → R1+ R2 +1
c) Increment/Decrement Micro-Operation
Increment and decrement micro-operations are generally performed by adding and subtracting 1 to and
from the register respectively.
R 1→R 1 +1
R 1 → R1- 1
Table 2: The Symbolic Description
Table 2: The Symbolic Description

Symbolic Designation Description

R3 ← R1 + R2 Contents of R1+R2 transferred to R3.
R3 ← R1 - R2 Contents of R1-R2 transferred to R3.
R2 ← (R2)' Compliment the contents of R2.
R2 ← (R2)' + 1 2's compliment the contents of R2.
R3 ← R1 + (R2)' + 1 R1 + the 2's compliment of R2 (subtraction).
R1 ← R1 + 1 Increment the contents of R1 by 1.
R1 ← R1 - 1 Decrement the contents of R1 by 1.

Instruction Codes
While a Program is a set of instructions that specify the operations, operands, and the sequence by which
processing has to occur. An instruction code is a group of bits that tells the computer to perform a specific
operation part.

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• Operation Code
The operation code of an instruction is a group of bits that define operations such as add, subtract, multiply,
shift and compliment. The number of bits required for the operation code depends upon the total number
of operations available on the computer. The operation code must consist of at least n bits for a given 2^n
operations. The operation part of an instruction code specifies the operation to be performed.
• Register Part
The operation must be performed on the data stored in registers. An instruction code therefore specifies not
only operations to be performed but also the registers where the operands (data) will be found as well as
the registers where the result has to be stored.
• Stored Program Organisation
The simplest way to organize a computer is to have Processor Register and instruction code with two parts.
The first part specifies the operation to be performed and second specifies an address. The memory address
tells where the operand in memory will be found. Instructions are stored in one section of memory and data
in another.
Computers with a single processor register are known as Accumulator (AC). The operation is performed
with the memory operand and the content of AC.
• Common Bus System
The basic computer has 8 registers, a memory unit and a control unit. Paths must be provided to transfer
data from one register to another. An efficient method for transferring data in a system is to use a Common
Bus System. The output of registers and memory are connected to the common bus.
• Load (LD)
The lines from the common bus are connected to the inputs of each register and data inputs of memory.
The particular register whose LD input is enabled receives the data from the bus during the next clock pulse
transition.
Before studying about instruction formats lets first study about the operand address parts.
When the 2nd part of an instruction code specifies the operand, the instruction is said to have immediate
operand. And when the 2nd part of the instruction code specifies the address of an operand, the instruction
is said to have a direct address. And in indirect address, the 2nd part of instruction code, specifies the
address of a memory word in which the address of the operand is found.
COMPUTER INSTRUCTIONS
The basic computer has three instruction code formats. The Operation Code (opcode) part of the instruction
contains 3 bits and remaining 13 bits depends upon the operation code encountered.
There are Three Types Of Instruction Formats:
Three-Address Instructions
Computers with three-address instruction formats can use each address field to specify either a processor
register or a memory operand. The program in assembly language that evaluates X = (A + B) ∗ (C + D) is
shown below, together with comments that explain the register transfer operation of each instruction.
ADD R1, A, B R1 ← M [A] + M [B]
ADD R2, C, D R2 ← M [C] + M [D]
MUL X, R1, R2 M [X] ← R1 ∗ R2

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It is assumed that the computer has two processor registers, R1 and R2. The symbol M [A] denotes the
operand at memory address symbolized by A.
The advantage of the three-address format is that it results in short programs when evaluating arithmetic
expressions.
The disadvantage is that the binary-coded instructions require too many bits to specify three addresses. An
example of a commercial computer that uses three-address instructions is the Cyber 170. The instruction
formats in the Cyber computer are restricted to either three register address fields or two register address
fields and one memory address field.
Two-Address Instructions
Two address instructions are the most common in commercial computers. Here again each address field
can specify either a processor register or a memory word. The program to evaluate
X = (A + B) ∗ (C + D) is as follows:
MOV R1, A R1 ← M [A]
ADD R1, B R1 ← R1 + M [B]
MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
MUL R1, R2 R1 ← R1∗R2
MOV X, R1 M [X] ← R1
The MOV instruction moves or transfers the operands to and from memory and processor registers. The
first symbol listed in an instruction is assumed to be both a source and the destination where the result of
the operation is transferred.
One-Address Instructions
One-address instructions use an implied accumulator (AC) register for all data manipulation. For
multiplication and division there is a need for a second register. However, here we will neglect the second
and assume that the AC contains the result of tall operations. The program to evaluate
X = (A + B) ∗ (C + D) is
LOAD A AC ← M [A]
ADD B AC ← A [C] + M [B]
STORE T M [T] ← AC
LOAD C AC ← M [C]
ADD D AC ← AC + M [D]
MUL T AC ← AC ∗ M [T]
STORE X M [X] ← AC
All operations are done between the AC register and a memory operand. T is the address of a temporary
memory location required for storing the intermediate result.
Zero-Address Instructions
A stack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH
and POP instructions, however, need an address field to specify t he operand that communicates with the
stack. The following program shows how X = (A + B) ∗ (C + D) will be written for a stack organized
computer. (TOS stands for top of stack)
PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A + B)

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PUSH C TOS ← C
PUSH D TOS ← D
ADD TOS ← (C + D)
MUL TOS ← (C + D) ∗ (A + B)
POP X M [X] ← TOS
To evaluate arithmetic expressions in a stack computer, it is necessary to convert the expression into reverse
Polish notation. The name “zero-address” is given to this type of computer because of the absence of an
address field in the computational instructions.

Instruction Cycle
An instruction cycle, also known as fetch-decode-execute cycle is the basic operational process of a
computer. This process is repeated continuously by CPU from boot up to s hut down of computer.
Following are the steps that occur during an instruction cycle:
• Fetch the Instruction
The instruction is fetched from memory address that is stored in Program Counter (PC) and stored in the
Instruction Register (IR). At the end of the fetch operation, PC is incremented by 1 and it then points to the
next instruction to be executed.
• Decode the Instruction
The instruction in the IR is executed by the decoder.
• Read the Effective Address
If the instruction has an indirect address, the effective address is read from the memory. Otherwise
operands are directly read in case of immediate operand instruction.
• Execute the Instruction
The Control Unit passes the information in the form of control signals to the functional unit of CPU. The
result generated is stored in main memory or sent to an output device.
The cycle is then repeated by fetching the next instruction. Thus in this way the instruction cycle is repeated
continuously.

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Figure 3: Instruction Cycle
CISC and RISC ARCHITECTURES
What is CISC and RISC?
Central Processing Unit Architecture operates the capacity to work from “Instruction Set Architecture” to
where it was designed. There are 2 types of concepts to implement the processor hardware architecture.
The architectural designs of CPU are:
• RISC (Reduced Instruction Set Computing)
• CISC (Complex Instruction Set Computing)
Complex instruction set computing (CISC) has the ability to execute addressing modes or multistep
operations within one instruction set. It is the design of the CPU where one instruction performs many low-
level operations. For example, memory storage, an arithmetic operation and loading from memory. RISC
is a CPU design strategy based on the insight that simplified instruction set gives higher performance when
combined with a microprocessor architecture which has the ability to execute the instructions by using
some microprocessor cycles per instruction. Hardware of the Intel is termed as Complex Instruction Set
Computer (CISC) while Apple hardware is Reduced Instruction Set Computer (RISC).
Hardware designers invent numerous technologies and tools to implement the desired architecture in order
to fulfil these needs. Hardware architecture may be implemented to be either hardware specific or software
specific, but according to the application both are used in the required quantity.

Figure 4: RISC and CISC Architecture

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• CISC Architecture
The CISC approach attempts to minimize the number of instructions per program, sacrificing the number
of cycles per instruction. Computers based on the CISC architecture are designed to decrease the memory
cost. Because, the large programs need more storage, thus increasing the memory cost and large memory
becomes more expensive. To solve these problems, the number of instructions per program can be reduced
by embedding the number of operations in a single instruction, thereby making the instructions more
complex.

Figure 5: CISC Architecture

MUL loads two values from the memory into separate registers in CISC. CISC uses minimum possible
instructions by implementing hardware and executes operations.
Characteristics of CISC Architecture
i. Instruction-decoding logic will be Complex.
ii. One instruction is required to support multiple addressing modes.
iii. Less chip space is enough for general purpose registers for the instructions that are operated directly on
memory.
iv. Various CISC designs are set up two special registers for the stack pointer, handling interrupts e.t.c.
v. MUL is referred to as a “complex instruction” and requires the programmer for storing functions.

• RISC Architecture
RISC (Reduced Instruction Set Computer) is used in portable devices due to its power efficiency. RISC is
a type of microprocessor architecture that uses highly-optimized set of instructions. RISC does the opposite
by reducing the cycles per instruction at the cost of the number of instructions per program Pipelining is
one of the unique features of RISC. It is performed by overlapping the execution of several instructions in
a pipeline fashion.
It has a high performance advantage over CISC. RISC processors take simple instructions and are executed
within a clock cycle
Example: Apple iPod and Nintendo DS.

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Figure 6: RISC Architecture
RISC Architecture Characteristics
i. Simple Instructions are used in RISC architecture.
ii. RISC helps and supports few simple data types and synthesizes complex data types.
iii. RISC utilizes simple addressing modes and fixed length instructions for pipelining.
iv. RISC permits any register to use in any context.
v. One Cycle Execution Time
vi. The amount of work that a computer can perform is reduced by separating “LOAD” and
“STORE” instructions.
vii. RISC contains Large Number of Registers in order to prevent various numbers of interactions
with memory.
viii. In RISC, Pipelining is easy as the execution of all instructions will be done in a uniform interval
of time i.e. one click.
ix. In RISC, more RAM is required to store assembly level instructions.
x. Reduced instructions need a less number of transistors in RISC.
xi. RISC uses Harvard memory model means it is Harvard Architecture.
xii. A compiler is used to perform the conversion operation means to convert a high-level language
statement into the code of its form.
• RISC & CISC Comparison
CISC RISC
It is prominent on hardware It is prominent on the software
It has high cycle per second It has low cycle per second
It has transistors used for storing More transistors are used for storing
instruction which are complex memory
LOAD and STORE memory-to- LOAD and STORE register-register
memory is induced in instructions ate independent
It has multi-clock It has a single clock

The Advantages and Disadvantages of RISC and CISC

• The Advantages of RISC architecture
i. RISC(Reduced instruction set computing)architecture has a set of instructions, so highlevel language
compilers can produce more efficient code
ii. It allows freedom of using the space on microprocessors because of its simplicity.
iii. Many RISC processors use the registers for passing arguments and holding the local variables.
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iv. RISC functions use only a few parameters, and the RISC processors cannot use the call instructions, and
therefore, use a fixed length instruction which is easy to pipeline.
v. The speed of the operation can be maximized and the execution time can be minimized. Very less number
of instructional formats, a few numbers of instructions and a few addressing modes are needed.

• The Disadvantages of RISC architecture

i. Mostly, the performance of the RISC processors depends on the programmer or compiler as the
knowledge of the compiler plays a vital role while changing the CISC code to a RISC code
ii. While rearranging the CISC code to a RISC code, termed as a code expansion, will increase the size.
And, the quality of this code expansion will again depend on the compiler, and also on the machine’s
instruction set.
iii. The first level cache of the RISC processors is also a disadvantage of the RISC, in which these
processors have large memory caches on the chip itself. For feeding the instructions, they require very fast
memory systems
• Advantages of CISC architecture
i. Microprogramming is easy assembly language to implement, and less expensive than hard wiring a
control unit.
ii. The ease of microcoding new instructions allowed designers to make CISC machines upwardly
compatible:
iii. As each instruction became more accomplished, fewer instructions could be used to implement a given
task.
• Disadvantages of CISC architecture
i. The performance of the machine slows down due to the amount of clock time taken by different
instructions will be dissimilar
ii. Only 20% of the existing instructions is used in a typical programming event, even though there
are various specialized instructions in reality which are not even used frequently.
iii. The conditional codes are set by the CISC instructions as a side effect of each instruction which
takes time for this setting – and, as the subsequent instruction changes the condition code bits –
so, the compiler has to examine the condition code bits before this happens.

Addressing Modes
Addressing Mode Addressing modes are the ways how architectures specify the address of an object they
want to access. In machines, an addressing mode can specify a constant, a register or a location in memory.
The operation field of an instruction specifies the operation to be performed. This operation will be executed
on some data which is stored in computer registers or the main memory. The way any operand is selected
during the program execution is dependent on the addressing mode of the instruction.
The purpose of using addressing modes is as follows:
• To give the programming versatility to the user.
• To reduce the number of bits in addressing field of instruction.

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Types of Addressing Modes
• Immediate Mode In this mode, the operand is specified in the instruction itself. An immediate mode
instruction has an operand field rather than the address field. For example: ADD 7, which say Add 7 to
contents of accumulator. 7 is the operand here.
• Register Mode In this mode the operand is stored in the register and this register is present in CPU. The
instruction has the address of the Register where the operand is stored

Advantages of this mode:

• Shorter instructions and faster instruction fetch.
• Faster memory access to the operand(s)
Disadvantages of this mode:
• Very limited address space
• Using multiple registers helps performance but it complicates the instructions.
• Register Indirect Mode In this mode, the instruction specifies the register whose contents give us the
address of operand which is in memory. Thus, the register contains the address of operand rather than the
operand itself.

• Direct Addressing Mode In this mode, effective address of operand is present in instruction itself. For
Example: R1, 4000 - In this the 4000 is effective address of operand.
NOTE: Effective Address is the location where operand is present.
• Single memory reference to access data.
• No additional calculations to find the effective address of the operand
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• Indirect Addressing Mode In this, the address field of instruction gives the address where the effective
address is stored in memory. This slows down the execution, as this includes multiple memory lookups to
find the operand.

• Displacement Addressing Mode

In this the contents of the indexed register is added to the Address part of the instruction, to obtain the
effective address of operand. EA = A + (R) in this, the address field holds two values, A (which is the base
value) and R (that holds the displacement), or vice versa.

• Relative Addressing Mode

It is a version of Displacement addressing mode. In this the contents of PC (Program Counter) is added to
address part of instruction to obtain the effective address. EA = A + (PC), where EA is effective address
and PC is program counter. The operand is A cells away from the current cell (the one pointed to by PC)
• Base Register Addressing Mode: It is again a version of Displacement addressing mode. This can be
defined as EA = A + (R), where A is displacement and R holds pointer to base address.

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• Stack Addressing Mode: In this mode, operand is at the top of the stack. For example: ADD, this
instruction will POP top two items from the stack, add them, and will then PUSH the result to the top of
the stack. Auto Increment/Decrement Mode In this the register is incremented or decremented after or
before its value is used.
Table 4: Summary of the Addressing Mode
The most common names for addressing modes (names may differ among architectures)
Addressing modes Example Instruction meaning When used
Register Add R4,R3 R4 <- R4 + R3 When a value is in a register
Immediate Add R4,#3 R4 <- R4 + 3 For constant
Displacement Add R4, 100(R1) R4 <- R4 + Accessing local variables
M[100+R1]
Register deferred Add R4,(R1) R4 <- R4 + M[R1] Accessing using a pointer or a
computed address
Indexed Add R3, (R1 + R2) R3 <- R3 + M[R1+R2] Useful in array addressing: R1
- base of array R2 - index
amount
Direct Add R1, (1001) R1 <- R1 + M[1001] Useful in accessing static data
Memory deferred Add R1, @(R3) R1 <- R1 + M[M[R3]] If R3 is the address of a
pointer p, then mode yields *p
Auto -increment Add R1, (R2)+ R1 <- R1 +M[R2] R2 Useful for stepping through
<- R2 + d arrays in a loop. R2 - start of
array d - size of an element
Auto-decrement Add R1,-(R2) R2 <-R2-d R1 <- R1 + Same as auto-increment. Both
M[R2 can also be used to implement
a stack as push and pop
Scaled Add R1, 100(R2)[R3] R1<- Used to index arrays. May be
R1+M[100+R2+R3*d] applied to any base addressing
mode in some machines.

Stack Organization
A useful feature that is included in the CPU of most computers is a stack or last in, first out (LIFO) list. A
stack is a storage device that stores information in such a manner that the item stored last is the first item
retrieved. The operation of a stack can be compared to a stack of trays. The last tray placed on top of the
stack is the first to be taken off.
The stack in digital computers is essentially a memory unit with an address register that can only( after an
initial value is loaded in to it).The register that hold the address for the stack is called a stack pointer (SP)
because its value always points at the top item in stack. Contrary to a stack of trays where the tray itself
may be taken out or inserted, the physical registers of a stack are always available for reading or writing
The two operation of stack are the insertion and deletion of items. The operation of insertion is called PUSH
because it can be thought of as the result of pushing a new item on top. The operation of deletion is called
POP because it can be thought of as the result of removing one item so that the stack pops up. However,
nothing is pushed or popped in a computer stack. These operations are simulated by incrementing or
decrementing the stack pointer register.
Register stack:
A stack can be placed in a portion of a large memory or it can be organized as a collection of a finite number
of memory words or registers. Figure X shows the organization of a 64-word register stack. The stack
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pointer register SP contains a binary number whose value is equal to the address of the word that is currently
on top of the stack. Three items are placed in the stack: A, B, and C in the order. item C is on the top of the
stack so that the content of sp is now 3. To remove the top item, the stack is popped by reading the memory
word at address 3 and decrementing the content of SP. Item B is now on top of the stack since SP holds
address 2. To insert a new item, the stack is pushed by incrementing SP and writing a word in the next
higher location in the stack. Note that item C has read out but not physically removed. This does not matter
because when the stack is pushed, a new item is written in its place.
In a 64-word stack, the stack pointer contains 6 bits because 26 =64. since SP has only six bits, it cannot
exceed a number grater than 63(111111 in binary). When 63 is incremented by 1, the result is 0 since
111111 + 1 =1000000 in binary, but SP can accommodate only the six least significant bits. Similarly, when
000000 is decremented by 1, the result is 111111. The one bit register Full is set to 1 when the stack is full,
and the one-bit register EMTY is set to 1 when the stack is empty of items. DR is the data register that holds
the binary data to be written in to or read out of the stack.

Figure 3: Block Diagram Of A 64-Word Stack

Initially, SP is cleared to 0, Emty is set to 1, and Full is cleared to 0, so that SP points to the word at address
o and the stack is marked empty and not full. if the stack is not full , a new item is inserted with a push
operation. the push operation is implemented with the following sequence of micro-operation.
SP ←SP + 1 (Increment stack pointer)
M(SP) ← DR (Write item on top of the stack)
if (sp=0) then (Full ← 1) (Check if stack is full)
Emty ← 0 ( Marked the stack not empty)

The stack pointer is incremented so that it points to the address of the next-higher word. A memory write
operation inserts the word from DR into the top of the stack. Note that SP holds the address of the top of
the stack and that M(SP) denotes the memory word specified by the address presently available in SP, the
first item stored in the stack is at address 1. The last item is stored at address 0, if SP reaches 0, the stack is
full of item, so FULLL is set to 1. This condition is reached if the top item prior to the last push was in
location 63 and after increment SP, the last item stored in location 0. Once an item is stored in location 0,
there are no more empty register in the stack. If an item is written in the stack, Obviously the stack can not
be empty, so EMTY is cleared to 0.
DR← M[SP] Read item from the top of stack
SP ← SP-1 Decrement stack Pointer
if( SP=0) then (Emty ← 1) Check if stack is empty
FULL ← 0 Mark the stack not full

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The top item is read from the stack into DR. The stack pointer is then decremented. if its value reaches zero,
the stack is empty, so Emty is set to 1. This condition is reached if the item read was in location 1. once this
item is read out , SP is decremented and reaches the value 0, which is the initial value of SP. Note that if a
pop operation reads the item from location 0 and then SP is decremented, SP changes to 111111, which is
equal to decimal 63. In this configuration, the word in address 0 receives the last item in the stack. Note
also that an erroneous operation will result if the stack is pushed when FULL=1 or popped when EMTY
=1.
Memory Stack
A stack can exist as a stand-alone unit as in figure 4 or can be implemented in a random access memory
attached to CPU. The implementation of a stack in the CPU is done by assigning a portion of memory to a
stack operation and using a processor register as a stack pointer. Figure shows a portion of computer
memory partitioned in to three segment program, data and stack. The program counter PC points at the
address of the next instruction in the program. The address register AR points at an array of data. The stack
pointer SP points at the top of the stack. The three register are connected to a common address bus, and
either one can provide an address for memory. PC is used during the fetch phase to read an instruction. AR
is used during the execute phase to read an operand. SP is used to push or POP items into or from the stack.
As show in figure below: the initial value of SP is 4001 and the stack grows with decreasing addresses.
Thus the first item stored in the stack is at address 4000, the second item is stored at address 3999, and the
last address hat can be used for the stack is 3000. No previous are available for stack limit checks. We
assume that the items in the stack communicate with a data register DR. A new item is inserted with the
push operation as follows.
SP← SP-1
M[SP] ← DR
The stack pointer is decremented so that it points at the address of the next word. A Memory write operation
insertion the word from DR into the top of the stack. A new item is deleted with a pop operation as follows.
DR← M[SP]
SP←SP + 1
The top item is read from the stack in to DR. The stack pointer is then incremented to point at the next item
in the stack.

Most computer do not provide hardware to check for stack overflow (FULL) or underflow (Empty). The
stack limit can be checked by using two prossor register :
one to hold upper limit and other hold the lower limit. after the pop or push operation SP is compared with
lower or upper limit register.

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Figure 4: computer memory with program, data and stack segments

Interrupt:
- When a Process is executed by the CPU and when a user Request for another Process then this will create
disturbance for the Running Process. This is also called as the Interrupt.
Interrupts can be generated by User, Some Error Conditions and also by Software’s and the hardware’s.
But CPU will handle all the Interrupts very carefully because when Interrupts are generated then the CPU
must handle all the Interrupts Very carefully means the CPU will also Provide Response to the Various
Interrupts those are generated. So that When an interrupt has Occurred then the CPU will handle by using
the Fetch, decode and Execute Operations.
Interrupts allow the operating system to take notice of an external event, such as a mouse click. Software
interrupts, better known as exceptions, allow the OS to handle unusual events like divide-by-zero errors
coming from code execution.
The sequence of events is usually like this:
Hardware signals an interrupt to the processor
The processor notices the interrupt and suspends the currently running software
The processor jumps to the matching interrupt handler function in the OS
The interrupt handler runs its course and returns from the interrupt
The processor resumes where it left off in the previously running software
The most important interrupt for the operating system is the timer tick interrupt.

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The timer tic interrupt allows the OS to periodically regain control from the currently running user process.
The OS can then decide to schedule another process, return back to the same process, do housekeeping,
etc. The timer tick interrupt provides the foundation for the concept of preemptive multitasking.
TYPES OF INTERRUPTS
Generally there are three types of Interrupts those are Occurred For Example
1) Internal Interrupt
2) External Interrupt.
3) Software Interrupt.
1.Internal Interrupt:
When the hardware detects that the program is doing something wrong, it will usually generate an interrupt
usually generate an interrupt.
– Arithmetic error - Invalid Instruction
– Addressing error - Hardware malfunction
– Page fault – Debugging
• A Page Fault interrupt is not the result of a program error, but it does require the operating system to get
control. The Internal Interrupts are those which are occurred due to Some Problem in the Execution For
Example When a user performing any Operation which contains any Error and which contains any type of
Error. So that Internal Interrupts are those which are occurred by the Some Operations or by Some
Instructions and the Operations those are not Possible but a user is trying for that Operation. And The
Software Interrupts are those which are made some call to the System for Example while we are Processing
Some Instructions and when we wants to Execute one more Application Programs.
2.External Interrupt:
• I/O devices tell the CPU that an I/O request has completed by sending an interrupt signal to the processor.
• I/O errors may also generate an interrupt.
• Most computers have a timer which interrupts the CPU every so many interrupts the CPU every so many
milliseconds. The External Interrupt occurs when any Input and Output Device request for any Operation
and the CPU will Execute that instructions first For Example When a Program is executed and when we
move the Mouse on the Screen then the CPU will handle this External interrupt first and after that he will
resume with his Operation.
3.Software interrupts: These types if interrupts can occur only during the execution of an instruction.
They can be used by a programmer to cause interrupts if need be. The primary purpose of such interrupts
is to switch from user mode to supervisor mode.
A software interrupt occurs when the processor executes an INT instruction. Written in the program,
typically used to invoke a system service. A processor interrupt is caused by an electrical signal on a
processor pin. Typically used by devices to tell a driver that they require attention. The clock tick interrupt
is very common; it wakes up the processor from a halt state and allows the scheduler to pick other work to
perform.

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 A processor fault like access violation is triggered by the processor itself when it encounters a condition
that prevents it from executing code. Typically when it tries to read or write from unmapped memory or
encounters an invalid instruction

MEMORY ORGANIZATION
A memory unit is the collection of storage units or devices together. The memory unit stores the binary
information in the form of bits. Generally, memory/storage is classified into 2 categories:
• Volatile Memory: This loses its data, when power is switched off.
• Non-Volatile Memory: This is a permanent storage and does not lose any data when power is switched
off.

Memory Hierarchy

Memory Hierarchy
The total memory capacity of a computer can be visualized by hierarchy of components. The memory
hierarchy system consists of all storage devices contained in a computer system from the slow Auxiliary
Memory to fast Main Memory and to smaller Cache memory.
• Auxiliary memory access time is generally 1000 times that of the main memory, hence it is at the bottom
of the hierarchy.
• The main memory occupies the central position because it is equipped to communicate directly with the
CPU and with auxiliary memory devices through Input/output processor (I/O).
When the program not residing in main memory is needed by the CPU, they are brought in from auxiliary
memory. Programs not currently needed in main memory are transferred into auxiliary memory to provide
space in main memory for other programs that are currently in use.
• The cache memory is used to store program data which is currently being executed in the CPU.
Approximate access time ratio between cache memory and main memory is about 1 to 7~10
Memory Access Methods
Each memory type is a collection of numerous memory locations. To access data from any memory, first it
must be located and then the data is read from the memory location. Following are the methods to access
information from memory locations:
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 1. Random Access: Main memories are random access memories, in which each memory location has a
unique address. Using this unique address any memory location can be reached in the same amount of time
in any order.
2. Sequential Access: This method allows memory access in a sequence or in order.
3. Direct Access: In this mode, information is stored in tracks, with each track having a separate read/write
head.

1. Main Memory The memory unit that communicates directly within the CPU, Auxillary memory and
Cache memory, is called main memory. It is the central storage unit of the computer system. It is a large
and fast memory used to store data during computer operations.Main memory is made up of RAM and
ROM, with RAM integrated circuit chips holing the major share.
i. Random Access Memory (RAM):
• DRAM: Dynamic RAM, is made of capacitors and transistors, and must be refreshed every 10~100 ms.
It is slower and cheaper than SRAM.
• SRAM: Static RAM, has a six transistor circuit in each cell and retains data , until powered off.
• NVRAM: Non-Volatile RAM, retains its data, even when turned off. Example: Flash memory.
ii. Read Only Memory (ROM):
is non-volatile and is more like a permanent storage for information. It also stores the bootstrap loader
program, to load and start the operating system when computer is turned on. PROM (Programmable ROM),
EPROM (Erasable PROM) and EEPROM (Electrically Erasable PROM) are some commonly used
ROMs.
2. Auxiliary Memory
Devices that provide backup storage are called auxiliary memory. For example: Magnetic disks and tapes
are commonly used auxiliary devices. Other devices used as auxiliary memory are magnetic drums,
magnetic bubble memory and optical disks. It is not directly accessible to the CPU, and is accessed using
the Input/Output channels.
3. Cache Memory
The data or contents of the main memory that are used again and again by CPU, are stored in the cache
memory so that we can easily access that data in shorter time.

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Whenever the CPU needs to access memory, it first checks the cache memory. If the data is not found in
cache memory then the CPU moves onto the main memory. It also transfers block of recent data into the
cache and keeps on deleting the old data in cache to accomodate the new one
• Hit Ratio The performance of cache memory is measured in terms of a quantity called hit ratio. When
the CPU refers to memory and finds the word in cache it is said to produce a hit. If the word is not found
in cache, it is in main memory then it counts as a miss. The ratio of the number of hits to the total CPU
references to memory is called hit ratio. Hit Ratio = Hit/(Hit + Miss)
4. Associative Memory
It is also known as content addressable memory (CAM). It is a memory chip in which each bit position can
be compared. In this the content is compared in each bit cell which allows very fast table lookup. Since the
entire chip can be compared, contents are randomly stored without considering addressing scheme. These
chips have less storage capacity than regular memory chips.
5. Mapping and Concept of Virtual Memory
The transformation of data from main memory to cache memory is called mapping. There are 3 main types
of mapping:
• Associative Mapping
• Direct Mapping
• Set Associative Mapping
6. Virtual Memory
Virtual memory is the separation of logical memory from physical memory. This separation provides large
virtual memory for programmers when only small physical memory is available. Virtual memory is used
to give programmers the illusion that they have a very large memory even though the computer has a small
main memory. It makes the task of programming easier because the programmer no longer needs to worry
about the amount of physical memory available.

Control unit
Control unit design and implementation can be done by two general methods:
• A hardwired control unit is designed from scratch using traditional digital logic design techniques to
produce a minimal, optimized circuit. In other words, the control unit is like an ASIC (application-specific
integrated circuit).
• A micro-programmed control unit is built from some sort of ROM. The desired control signals are simply
stored in the ROM, and retrieved in sequence to drive the micro operations needed by a particular
instruction.
Micro programmed control:
Micro programmed control is a control mechanism to generate control signals by using a memory called
control storage (CS), which contains the control signals. Although micro programmed control seems to be
advantageous to CISC machines, since CISC requires systematic development of sophisticated control
signals, there is no intrinsic difference between these 2 control mechanisms.

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 Hard-wired control:
This is a control mechanism to generate control signals by using appropriate finite state machine (FSM).
The pair of "microinstruction-register" and "control storage address register" can be regarded as a "state
register" for the hardwired control. Note that the control storage can be regarded as a kind of combinational
logic circuit. We can assign any 0, 1 values to each output corresponding to each address, which can be
regarded as the input for a combinational logic circuit. This is a truth table.

Input –Output Organization:

The I/O subsystem of a computer provides an efficient mode of communication between the central system
and the outside environment. It handles all the input-output operations of the computer system.
Peripheral Devices
Input or output devices that are connected to computer are called peripheral devices. These devices are
designed to read information into or out of the memory unit upon command from the CPU and are
considered to be the part of computer system. These devices are also called peripherals. For example:
Keyboards, display units and printers are common peripheral devices.
There are three types of peripherals:
1. Input peripherals
Allows user input, from the outside world to the computer. Example: Keyboard, Mouse etc.
2. Output peripherals:
Allows information output, from the computer to the outside world. Example: Printer, Monitor etc
3. Input-Output peripherals: Allows both input(from outised world to computer) as well as,
output(from computer to the outside world). Example: Touch screen etc.

Interfaces
Interface is a shared boundary between two separate components of the computer system which can be
used to attach two or more components to the system for communication purposes.
There are two types of interface:
1. CPU Inteface
2. I/O Interface
Let's understand the I/O Interface in details,

Input-Output Interface
Peripherals connected to a computer need special communication links for interfacing with CPU. In
computer system, there are special hardware components between the CPU and peripherals to control or
manage the input-output transfers. These components are called input-output interface units because they
provide communication links between processor bus and peripherals. They provide a method for
transferring information between internal system and input-output devices.

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