IEEE EMBEDDED SYSTEMS LETTERS, VOL. 16, NO.

3, SEPTEMBER 2024 299

FPGA-Based Digital Taylor–Fourier Transform

Abstract—This research centers on the application of the emerged as a superior alternative for achieving accurate
discrete-time Taylor–Fourier transform (DTTFT) algorithmic phasor estimates, even in the presence of oscillatory condi-
implementation for phasor estimation on a field-programmable tions [3], [5].
gate array board. The system employs a finite impulse response Diverse methodologies have been employed for phasor
structure of a digital Taylor–Fourier filter to extract amplitude estimation, such as the Hilbert transform [6] and the fast
and phase information. The hardware description utilizes a
multiply accumulator architecture with only forty embedded
discrete orthonormal stockwell transform (FDOST) [7], among
9-bit multiplier elements, achieving an 18-bit input–output reso- others. These efforts highlight the continuous progress in state
lution. Performance assessment involves signal analysis through and parameter estimation, contributing to the improvement of
FPGA-in-the-loop simulation in MATLAB/Simulink. Findings real-time monitoring of electric and electronic systems.
demonstrate that the DTTFT-based phasor estimator can be Theoretical explorations utilizing techniques such as Prony
effectively characterized using VHDL code and implemented on as is presented in [8] and Taylor–Kalman–Fourier outlined
an Intel D2-115 board. in [9] for dynamic phasor estimation offer reduced processing
Index Terms—Digital signal processing (DSP), discrete-time times, yielding instantaneous outcomes. Additionally, in recent
Taylor–Fourier transform (DTTFT), field-programmable gate years, a variety of methods have been studied to achieve results
array (FPGA) FPGA-in-the-loop (FIL), phasor estimation. with decreased error and lower computational complexity.
Among them, there is a symmetric Taylor-based weighted least
square filter [10], the Matrix and Pencil method [11], [12],
and a Morlet Wavelet Transform detailed in [13], all of
I. I NTRODUCTION
which have demonstrated promising results, although practical
IGITAL signal processing (DSP) is a crucial component
D of electronic instrumentation, finding applications in
diverse fields, such as audio, video, digital image process-
implementations have not been widely explored.
This work addresses limitations in algorithms based on
the static phasor concept by introducing the discrete-time
ing, data compression, telecommunications, control systems, Taylor–Fourier transform (DTTFT) implemented in a field-
biomedical engineering, and cryptography. The hardware- programmable gate array (FPGA). DTTFT provides improved
based nature of digital design makes it a reliable tool for approximations for oscillatory signals with reduced errors and
control and monitoring. The integration of real-time synchro- low computational demand, making it suitable for hardware.
nization with DSP enhances the effectiveness and reliability of This work introduces an innovative, cost-effective phasor mea-
electronic systems, enabling accurate information processing surement prototype based on hardware description, featuring
and control in various domains. The real-time synchronization parallel processing and low-level implementation.
of electrical parameters, including voltages and currents, is
crucial in modern electrical systems. This synchronization
uses phasor-form measurements to offer insights into signal II. FPGA-BASED M ETHODOLOGY
characteristics such as amplitude and phase, playing a role in A. Discrete-Time Taylor–Fourier Transform
state estimation, dynamic stability monitoring, event detection, The DTTFT is based on the dynamic phasor model, reported
and cybersecurity [1], [2]. in [14] that represents in a better way a signal from a real
Historically, the discrete Fourier transform (DFT) stood out electric system in comparison with the traditional signal model
as the predominant choice for phasor estimation. Its straight- where amplitude and phase are constants. The fundamental
forward application yields accurate outcomes, especially in theory about the DTTFT construction is presented on [15]
stable operating conditions [3]. However, this approach posed where the DTTFT is described as an expansion of the
limitations, particularly when addressing the primary goal of traditional Fourier model through the addition of the Taylor
systems monitoring: obtaining accurate estimates for phasor polynomial coefficients. The (1) shows the classical signal
information, especially during dynamic events [4]. In addition model with the inclusion of the dynamic phasor
to the DFT, many conventional algorithms adopt a static
 
model for phasor estimation, leading to similar performance
s(t) = Re a(t)eϕ(t) ej2π f1 t (1)
outcomes. Recognizing this limitation, dynamic phasors have
Manuscript received 16 November 2023; revised 19 February 2024; where p(t) = a(t)eϕ(t) is the dynamic phasor, with time vary-
accepted 1 April 2024. Date of publication 3 April 2024; date of current ing amplitude a(t) and phase ϕ(t), and f1 is the fundamental
version 30 August 2024. This manuscript was recommended for publication frequency. Then, the dynamic phasor can be approximated
by J. Gak. (Corresponding author: Jose de Jesus Rangel-Magdaleno.)
The authors are with the Electronics Coordination, Digital Systems by a Taylor polynomial centered at t0 and truncated at an
Group, Instituto Nacional de Astrofísica Óptica y Electrónica, Puebla index K
72810, Mexico (e-mail: [email protected]; [email protected];
[email protected]; [email protected]). (t − t0 )K
Digital Object Identifier 10.1109/LES.2024.3384843 pK (t) = p(t0 ) + ṗ(t0 )(t − t0 ) + · · · + pK (t0 ) (2)
K!
1943-0671 
c 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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300 IEEE EMBEDDED SYSTEMS LETTERS, VOL. 16, NO. 3, SEPTEMBER 2024

TABLE I
with T as the period of the signal and t0 − (T/2) ≤ t ≤ CORDIC M ODES
t0 + (T/2).
Then, the analysis (3), which represents the filtering algo-
rithm, is given by the traditional Fourier transform equation
with the inclusion of the dynamic phasor approximation based
on the Taylor polynomial terms (2) in the traditional signal
model (1)
ξ̂ = B† s (3)
where X[n] is the digital form of the continuous-time signal
where ξ̂ denotes the estimated Taylor–Fourier coefficients and model presented in (1) for this study case with n as the
its derivatives, B† is the pseudoinverse of the Taylor–Fourier discrete-time sample and f [n] as the filter coefficients [17].
matrix presented in (4), and s represents the measured signals 2) Multiply Accumulator: Digital implementations are fre-
⎛ ⎞⎛ ⎞ quently based on structures of MAC. This architecture is based
t0n1 t1n1 ··· tK
n1 WN 0 ··· 0
⎜ t0 ⎟⎜ 0 on a linear convolution algorithm, such as the one presented
⎜ n2 t1n2 ··· tK
n 2 ⎟⎜ WN ··· 0 ⎟⎟ in (7), known as an efficient way to implement an accumulative
B=⎜
⎜ .. .. .. .. ⎟ ⎜
⎟⎜ . .. .. .. ⎟
⎟. (4)
⎝ . . . . ⎠⎝ .. . . . ⎠ sum of products.
t0nC t1nC ··· tK 0 0 ··· WN From (7), L multiplications and L−1 sums are performed for
nC
each sample of Y[n]. In this way, an N × N bits multiplier has
From matrix B, it is important to highlight that the number to be combined with an accumulator. Hence, the accumulator
of cycles (C = K + 1) is crucial to avoid indeterminacy in the is usually designed with an extra bit to avoid any loss of
matrix equation system. WN represents the Fourier submatrix information [17].
with harmonic phase factors ωNh = ej2π h/N in each vector 3) CORDIC: The CORDIC algorithm is commonly used
h = 0, . . . , N − 1 where N is the number of samples per cycle. in digital design when there exists a nontrivial algebraic
The vectors tn comprise samples, creating a diagonal matrix function [18]. CORDIC enables the transformation between
with polynomial pieces corresponding to Taylor contributions. rectangular and polar coordinates using circular, linear, and
These contributions are described by tn = −(K +1)Ts (ns /2) to hyperbolic operations within defined iterations. Each opera-
(K + 1)Ts (ns /2), where ns represents each sample of Taylor’s tional mode consists of two rotation directions: 1) rotation and
interpolating polynomial at each sampling period Ts or sampling 2) vectoring.
frequency Fs . According to [16], the phasor amplitude and The next mathematical model can define the CORDIC
phase information are obtained according to the next equations algorithm
â(t0 ) = ξ̂ (5) Xk+1 1 −mδk 2−k Kk
= −k
ϕ̂(t0 ) = ∠ξ̂ . (6)
Yk+1 δk 2 1 Yk
Zk+1 = Zk + δk θk . (8)
As observed, the algorithmic implementation of the DTTFT
consists of matrix and vector operators, trigonometric func- This mapping is implemented at each iteration, where k
tions, complex numbers algebra, and operations like divisions, represents the iteration, K is the radius factor, m denotes the
which require special DSP techniques to be implemented CORDIC mode, θk is the angle (these parameters are given
on FPGA. Those techniques are presented in the following in Table I), δk = ±1, and the two rotation directions are
sections. ZK → 0 and YK → 0 [17]. Following this procedure and
with an adequate selection of initial values, nearly all the
B. Digital Signal Processing Techniques on FPGA transcendental functions can be computed by means of the
In signal processing implementations, basic instances like CORDIC algorithm.
registers, counters, and state machines are present. Depending 4) Polynomial Approximation: The Taylor series provides a
on the nature of operations, certain techniques, such as com- powerful tool for approximating nontrivial algebraic functions
plex number algebra or trigonometric functions, are needed in implementing
√ DSP algorithms on FPGAs. For functions
to approximate results that FPGA cannot directly calculate. such as x or arctan (y/x), the Taylor series expansion can be
The DTTFT FPGA-based implementation in this letter utilizes applied to achieve a polynomial approximation.
functions like CORDIC, multiply accumulator (MAC), and The general form of the Taylor series expansion for a
precalculation of coefficients through polynomial approxima- function f (x) around a point x0 is given by
tion. These techniques aim to achieve the Taylor–Fourier filter K
as a finite impulse response (FIR) filter. f k (x0 )
f (x) = (x − x0 )k . (9)
1) FIR: Digital FIR filters are frequently employed to mod- k!
k=0
ify input signal characteristics in either the time or frequency
domain. A FIR filter is a finite sum of convolutions between Here, f k (x) represents the kth derivative of f (x).
the filter’s impulse response and the signal. In this context, the Implementing special functions through polynomial approx-
filter coefficients remain constant over time, allowing them to imations has become a practical alternative. While the Taylor
be stored in memory for later use. series converges rapidly for some functions, such as ex , numer-
Then, the output signal Y[n] of the FIR filter of length L ous product terms are required to accurately approximate
applied to an input signal X[n] is given by the finite sum of special functions like arctan(x).
convolutions defined by Polynomial approximation in FPGA involves expressing
L−1 series terms through multiplication and accumulation oper-
Y[n] = X[n] ∗ f [n] = f [k]X[n − k] (7) ations using MAC units [17]. FPGA configurability allows
k=0 tailoring the polynomial degree K for a balance between
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AVALOS-ALMAZAN et al.: FPGA-BASED DIGITAL TAYLOR–FOURIER TRANSFORM 301

Fig. 1. DTFT FPGA-based architecture.

computational accuracy and resource utilization. The choice Taylor–Fourier matrix (4) both from (7), giving as a result
of x0 determines the approximation center, which is crucial in at the output of MAC1 and MAC2 the estimated Taylor–
this process [19]. Fourier coefficients represented by (3). The results of this stage
correspond to the real and imaginary parts of Y[n] in (7).
As is shown in Fig. 1, the matrix (4) is separated into two
III. DTFT E MBEDDED I MPLEMENTATION
real and imaginary parts due the FPGA limitations for complex
The digital Taylor–Fourier transform (DTFT) is the algo- number operations, giving as a result the estimated Taylor–
rithmic implementation of the DTTFT. The FPGA phasor Fourier coefficients ξ̂ in separate imaginary an real operators.
estimation architecture is depicted in Fig. 1 and represents the
signal flow diagram of the hardware description based on the
C. Amplitude and Phase Estimation
DTTFT theory, which comprises three main stages: 1) calcula-
tion of coefficients for memory storage; 2) matrix arithmetic; Within this stage, transcendental functions are calculated
and 3) calculations of amplitude and phase, in accordance using CORDIC and successive approximations. The arctan-
with [14]. The phasor estimation system is deployed on gent is computed through the CORDIC algorithm to estimate
an Altera DE2-115 board, equipped with a Cyclone IV the phase angle; meanwhile, by using the successive approx-
EP4CE115 FPGA, 114 480 logic elements, three 50-MHz imations method the division and square root are calculated.
oscillator clocks, Nios II processor, among other features. Finally, amplitude and phase angle results are displayed on
MATLAB through FPGA-in-the-loop (FIL) with an 18-bit
fixed point format.
A. Calculation of Coefficients for Memory Storage Finally, tests are conducted in MATLAB/Simulink to assess
The initial stage consists of calculating the DTFT the system’s performance.
coefficients. The real and imaginary parts of the coefficients
are stored in separate read-only memories (ROMs) to ease the IV. E XPERIMENTAL R ESULTS
following operations. On the other hand, the digitized signal
X[n] derived from s(t) of (1) is stored with an 18-bit fixed- In this section, phasor estimation results for a dynamic
point format in a random access memory (RAM), as illustrated state signal are discussed. A voltage signal is analyzed to
in Fig. 1. assess the phasor estimation performance embedded into the
The windowing signal process employs parallel–parallel device. A FIL process is conducted using a JTAG connection
registers arranged in a first in-first out (FIFO) data stack between the device and the Simulink environment, as depicted
configuration. These registers shape the windowing process in Fig. 1. In this process, the stimulus for the design is
for the MAC green blocks in Fig. 1, comprising a 4-cycle given through Simulink, after performing its computations, the
array with 42 samples per cycle. A multiplexer then selects the FPGA processes and sends back the results to the computer
X[n] sample to be processed in the MAC using Taylor–Fourier for visualization. The DTTFT-based FIR coefficients are cal-
coefficients stored in ROMs. culated considering a fundamental frequency of 60 Hz and a
third-order Taylor polynomial (K = 3). The voltage signal
analyzed in this work is conformed by 42 samples per cycle.
B. Matrix Arithmetic Aiming to provide the DTFT estimates, a voltage signal is
In the second stage, the ROMs coefficients are operated processed by the system embedded into the FPGA through
in parallel into independent MAC blocks: MAC1 performs the FIL. To this end, a rectangular sliding window approach
operations with real coefficients, while MAC2 performs oper- is updated sample by sample within the FPGA architecture.
ations with imaginary coefficients. The inputs of the blocks Figs. 2 and 3 show the amplitude and phase angle estimates,
MAC1 and MAC2 are multiplexed samples of X[n] and the comparing the theoretical results from MATLAB and the actual
FIR filter’ coefficients f [n] which are the coefficients of the results from the FIL working at the FPGA. The phase angle
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302 IEEE EMBEDDED SYSTEMS LETTERS, VOL. 16, NO. 3, SEPTEMBER 2024

V. C ONCLUSION
The successful implementation of the DTFT for dynamic
phasor estimation on an FPGA emphasizes its reliability as
a real-time algorithm for monitoring and control. This work
introduces a robust system that minimizes hardware resources,
contrasting with general-purpose systems like microcomput-
ers or microcontrollers. The system’s efficiency is amplified
through parallel processing and shorter processing times, all
facilitated by hardware description. The DTFT emerges as a
promising approach for dynamic phasor estimation, offering
both accuracy and efficiency in FPGA-based implementations.

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