Logic Design

Assoc. Prof Mina Ibrahim

Lecture 11
 Sequential Circuit
Sequential circuit is a combinational
circuit with storage elements connected
to form a feedback path
It is specified by a time sequence of
inputs, outputs, and internal states . In
contrast, the outputs of combinational
logic depend only on the present values of
the inputs.
 Sequential Circuit
There are two main types of sequential
circuits (a synchronous sequential and an
asynchronous sequential), and their
classification is a function of the timing of
their signals:
 A synchronous sequential circuit is a system
whose behavior can be defined at discrete
instants of time.
 The behavior of an asynchronous sequential
circuit depends upon the input signals at any
instant of time and the order in which the
inputs change.
 Sequential Circuit
Synchronization sequential circuit (clocked
sequential circuit) is achieved by a timing
device called a clock generator (clk), which
provides a clock signal having the form of a
periodic train of clock pulses.
 Storage Elements
Storage elements (memory) that operate
with signal levels are referred to as
latches (level sensitive devices)
Storage elements those controlled by a
clock transition are flip-flops (edge-
sensitive devices)
The two types of storage elements
are related because latches are the basic
circuits from which all flip-flops are
constructed
Storage Elements
 Storage Elements
The storage elements used in clocked
sequential circuits are flipflops
A flip-flop is a binary storage device
capable of storing one bit of information.
A sequential circuit may use many flip-
flops to store as many bits as necessary
The new value is stored (the flip-flop is
updated) when a pulse of the clock signal
occurs
 Latches (SR Latch)
The SR Latch is a circuit with two cross-
coupled NOR gates or two cross-coupled
NAND gates, and two inputs labeled S for
set and R for reset Remember

0 NOR A = A’
1 NOR A = 0
 Latches (SR Latch)
The SR Latch is a circuit with two cross-
coupled NOR gates or two cross-coupled
NAND gates, and two inputs labeled S for
set and R for reset Remember

0 NAND A = 1
1 NAND A = A’
 Latches (SR Latch)
The operation of the basic SR latch can
be modified by providing an additional
input signal that determines (controls)
when the state of the latch can be
changed Remember

0 NAND A = 1
1 NAND A = A’
 Latches (D Latch)
One way to eliminate the undesirable
condition of the indeterminate state in the
SR latch is to ensure that inputs S and R
are never equal to 1 at the same time as it
is done in the D latch (transparent latch)
Latches (D Latch)
 Flip-Flops
The state of a latch or flip-flop is
switched by a change in the control input.
This momentary change is called a trigger,
and the transition it causes is said to
trigger the flip-flop
The D latch with pulses in its control
input is essentially a flip-flop (edge-
triggered D Flip-Flop or for shorten D Flip-
Flop) that is triggered every time the
pulse goes to the logic-1 level
Flip-Flops (Edge-Triggered D Flip-Flop)
 Flip-Flops (D Flip-Flop)
The most economical and efficient flip-
flop constructed is the edge-triggered D
flipflop, because it requires the smallest
number of gates. Other types of flip-flops
can be constructed by using the D flip-flop
and external logic.
Flip-Flops (JK Flip-Flop)
Flip-Flops (T Flip-Flop)
 Characteristic Tables and Equations
Characteristic tables (state tables)
define the next state as a function of the
inputs and the present state
Q (t) is the present state and Q(t+1) is
the next state
The next state is the state that results
from a clock transition
Characteristic Tables and Equations

Remember

0 XOR Q = Q
1 XOR Q = Q’
 Design Procedure
The design of the synchronous
sequential circuit consists of choosing the
flip-flops and then finding a combinational
gate structure that, together with the flip-
flops, produces a circuit which fulfills the
stated specifications
The combinational circuit is derived from
the state table by evaluating the flip-flop
input equations and output equations
 Design Procedure
The procedure for designing
synchronous sequential circuits can be
summarized by a list of recommended
steps:
 From the word description and
specifications of the desired operation,
obtain the state table for the circuit
 Choose the type of flip-flops to be used
 Derive the simplified flip-flop input
equations and output equations
 Draw the logic diagram
 Design Procedure
During the design process, the transition
from the present state to the next state is
known and wish to find the flip-flop input
conditions that will cause the required
transition (we need an excitation table)
 Design Procedure
Ex: Using JK Flip-Flops to design a sequential
circuit that has the following state-table:
Design Procedure
Design Procedure
Design Procedure
 Design Procedure
Ex: Using T Flip-Flops to design a sequential
circuit that has the following state diagram:
Design Procedure
Design Procedure
Design Procedure
Design Procedure
 Registers and Counters
A clocked sequential circuit consists of a
group of flip‐flops and combinational
gates. The flip‐flops are essential because,
in their absence, the circuit reduces to a
purely combinational circuit (provided
that there is no feedback among the
gates).
A circuit with flip‐flops is considered a
sequential circuit even in the absence of
combinational gates.
Two such circuits are registers and
counters.
 Registers
A register is a group of flip‐flops, each one
of which shares a common clock and is
capable of storing one bit of information
An n‐bit register consists of a group of n
flip‐flops capable of storing n bits of binary
information
In addition to the flip‐flops, a register may
have combinational gates that perform
certain data‐processing tasks. The flip‐flops
hold the binary information, and the gates
determine how the information is
transferred into the register
 Registers
Various types of registers
are available commercially.
The simplest register is one
that consists of only
flip‐flops, without any gates
The figure shows such a
register constructed with
four D‐type flip‐flops to form
a four‐bit data storage
register
The common clock input
triggers all flip‐flops and the
binary data available at the
four inputs are transferred
into the register
 Counters
A counter is essentially a special type of
registers that goes through a
predetermined sequence of binary states.
Counters are available in two categories:
 Ripple counters: the CLK input of some or all
flip-flops are triggered, not by the common
clock pulses, but rather by the transition of
other flip-flop outputs. Ripple counters are
event driven counters
 Synchronous counters: the CLK inputs of all
flip‐flops are triggered by the common clock
pulses. Synchronous counters are time
driven counters
 Binary Ripple Counter
A binary ripple counter consists of a
series connection of complementing flip-
flops, with the output of each flip-flop
connected to the CLK input of the next
higher order flip-flop.
An n‐bit binary counter consists of n
flip‐flops and can count in binary from 0
through 2n-1
 Binary Ripple Counter
A3 A2 A1 A0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Binary Ripple Counter
 Binary Ripple Counter
The count starts with binary 0 and
increments by 1 with each count pulse input
After the count of 15, the counter goes
back to 0 to repeat the count
The least significant bit, A0 is
complemented with each count pulse input
Every time that A0 goes from 1 to 0, it
complements A1
Every time that A1 goes from 1 to 0, it
complements A2
Every time that A2 goes from 1 to 0, it
complements A3