ECE 6775

High-Level Digital Design Automation

Fall 2024

Analysis of Algorithms
Announcements

▸Lab 1 due tomorrow

▸HW 1 will be released today

▸Instructor office hours rescheduled to

Thursdays 5-6pm, starting today

1
Review: LUT Mapping

(1) How many 3-input LUTs are needed to implement the

following full adder?
(2) How about using 4-input LUTs?

A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
2
Agenda

▸Basics of algorithm analysis

– Complexity analysis and asymptotic notations
– Taxonomy of algorithms

▸Basics of graph algorithms

– An EDA application: static timing analysis

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[3B2-14] mdt2010030062.3d 4/5/010 16:1 Page 68

Recap: Algorithms Drive Automation

Perspectives
Topics touched on in 6775

Place and
ExtTool SimTool STA Synthesis EC Formal
route

Circuit Timing Logic Model

Extraction Placement Routing
analysis analysis optimization checking

DAE PDE Compilers Concurrency

solvers solvers Machine
learning
Search Decision
Function Model procedures
approximations reduction

Fast F. Lang.,
Nonlinear Continuous Discrete Combinatorial Logic and
linear automata and
solvers optimization optimization algorithms semantics
solvers concurrency

Continuous mathematics Discrete mathematics

Key Algorithms in EDA

Figure 1. Fundamental areas and domain knowledge in EDA. (Courtesy Andreas Kuehlmann, Cadence
Design Systems, Inc.) [source: Andreas Kuehlmann, Synopsys Inc.] 4

subject matter are lost to other disciplines. The work- engineering change, and formal verification. The
Analysis of Algorithms
▸ Need a systematic way to compare two algorithms
– Execution time is typically the most common criterion used
– Space (memory) usage is also important in most cases
– But difficult to compare in practice since these algorithms
may be implemented on different machines, use different
languages, etc.
– Plus, execution time is usually input-dependent

▸ big-O notation is widely used for asymptotic analysis

– Complexity is represented with respect to some natural &
abstract measure of the problem size N

5
Big-O Notation

▸ Express execution time as a function of input size n

– Running time F(n) is of order G(n), written as F(n) is O(G(n)) when
∃n0, "n ≥ n0, F(n) ≤ K・G(n) for some constant K

– F will not grow larger than G by more than a constant factor

– G is often called an “upper bound” for F

▸ Interested in the worst-case input & the growth rate for

large input size

6
Big-O Notation (cont.)

▸ How to determine the order of a function?

– Ignore lower order terms
– Ignore multiplicative constants
– Examples:
3n2 + 6n + 2 is O(n2)
n1.1 + 1000n is O(n1.1), n1.1 is also O(n2)
n! > Cn > nC > log n > log log n > C
Þ n! > n10 > n2 > n log n > n > log n

▸ What do asymptotic notations mean in practice?

– If algorithm A is O(n2) and algorithm B is O(n log n),
we usually say algorithm B is more scalable.
7
More Asymptotic Notions

▸ big-Omega notation: F(n) is W(G(n))

– ∃n0, "n ≥ n0, F(n) ³ K・g(n) for some constant K
G is called a “lower bound” for F

▸ big-Theta notation: F(n) is Q(G(n))

– If G is both an upper and lower bound for F, it describes the
growth of a function more accurately than big-O or big-Omega
– Examples:
4n2 + 1024 = Q(n2)
n3 + 4n ≠ Q(n2)

8
Exponential Growth
▸ Consider a 1 GHz processor (1 ns per clock cycle)
running 2N operations (assuming each op requires one cycle)

N 2N 1ns x 2N
10 103 1 us
20 106 1 ms
30 109 1s
40 1012 16.7 mins
50 1015 11.6 years
60 1018 31.7 years
70 1021 31710 years

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NP-Complete

▸ The class NP-complete (NPC) is the set of decision

problems which we “believe” there is no polynomial time
algorithms (hardest problem in NP)

▸ NP-hard is another class of problems, which are at least

as hard as the problems in NPC (also containing NPC)

▸ If we know a problem is in NPC or NP-hard, there is

(very) little hope to solve it exactly in an efficient way

10
How to Identify an NP-Complete Problem
§ I can’t find an efficient § I can’t find an efficient
algorithm, I guess I’m just algorithm, but neither can all
too dumb. these famous people.

§ I can’t find an efficient

algorithm, because no such
algorithm is possible. More formally – In NP-completeness proofs,
a reduction is the process of transforming
one problem (which is known to be NPC)
into another in polynomial time to show that
solving the second problem would also
solve the first, proving the second problem
is at least as hard.
[source: “Computers and Intractibility”
11
by Garey and Johnson]
Problem Intractability

▸ Most of the nontrivial EDA problems are intractable

(NP-complete or NP-hard)
– Best-known algorithm complexities that grow exponentially with
n, e.g., O(n!), O(nn), and O(2n).
– No known algorithms can ensure, in a time-efficient manner,
globally optimal solution

▸ Heuristic algorithms are used to find near-optimal

solutions
– Be content with a “reasonably good” solution

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Types of Algorithms

▸ There are many ways to categorize different types of

algorithms
– Polynomial vs. Exponential, in terms of computational effort
– Optimal (or Exact) vs. Heuristic, in solution quality
– Deterministic vs. Stochastic, in decision making
– Constructive vs. Iterative, in structure
…

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Various Algorithm Design Techniques

▸ There can be many different algorithms for solving the

same problem
– Exhaustive search Topics touched on in 6775
– Divide and conquer
– Dynamic programming
– Greedy
– Linear programming (LP)
– Integer linear programing (ILP)
– Network flow
– Evolutionary algorithms
– Simulated annealing
…

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Broader Classification of Algorithms
▸ Combinatorial algorithms
– Graph algorithms
…
▸ Computational mathematics
– Optimization algorithms
Topics touched on in 6775
– Numerical algorithms
…
▸ Computational science
– Bioinformatics
– Linguistics
– Statistics
…
▸ Digital logic
– Boolean minimization
…
▸ Information theory & signal processing
…
▸ Machine learning and statistical classification

Many more

[source: en.wikipedia.org/wiki/List_of_algorithms]
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Graph Definition

▸ Graph: a set of objects and their connections

– Ubiquitous: any binary relation can be represented as a graph

▸ Formal definition:
– G = (V, E), V = {v1, v2, ..., vn}, E = {e1, e2, ..., em}
• V : set of vertices (nodes), E : set of edges (arcs)
– Undirected graph: an edge {u, v} also implies {v, u}
– Directed graph: each edge (u, v) has a direction

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Simple Graph

▸ Loops, multi edges, and simple graphs

– An edge of the form (v, v) is said to be a self-loop
– A graph permitted to have multiple edges (or parallel edges)
between two vertices is called a multigraph
– A graph is said to be simple if it contains no self-loops or
multiedges

Simple graph Multigraph

b a
a
f
b
c

e g
d c

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Graph Connectivity

▸ Paths
– A path is a sequence of edges connecting two vertices
– A simple path never goes through any vertex more than once

▸ Connectivity
– A graph is connected if there is a path between any two vertices
– Any subgraph that is connected can be referred to as a
connected component
– A directed graph is strongly connected if there is always a
directed path between vertices

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Trees and DAGs

▸ A cycle is a path starting and ending at the same vertex.

A cycle in which no vertex is repeated other than the
starting vertex is said to be a simple cycle

▸ An undirected graph with no cycles is a tree if it is

connected, or a forest otherwise
– A directed tree is a directed graph which would be a tree if the
directions on the edges were ignored

▸ A directed graph with no directed cycles is said to be a

directed acyclic graph (DAG)

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 Examples
Tree
a

b c d

e f g h i j k

Directed graphs with cycles Directed acyclic graph (DAG)

c f c f
a a
b d g b d g

e e

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Graph Traversal

▸ Purpose: visit all the vertices in a particular order,

check/update their properties along the way

▸ Commonly used algorithms: Depth-first search (DFS);

Breadth-first search (BFS)

a DFS order (from node a):

aà?

b BFS order:
aà?
d
c

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Topological Sort

▸ A topological order of a directed graph is an ordering

of nodes where all edges go from an earlier vertex (left)
to a later vertex (right)
– Feasible if and only if the subject graph is a DAG

b
a b d c

c d

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Application in EDA: Static Timing Analysis

▸ In circuit graphs, static timing analysis (STA) refers to

the problem of finding the delays from the input pins of the
circuit (esp. nodes) to each gate
– In sequential circuits, flip-flop (FF) input acts as output pin, FF
output acts as input pin
– Max delay of the output pins determines clock period
– Critical path is a path with max delay among all paths

▸ Two important terms

– Required time: The time that the data signal needs to arrive at
certain endpoint on a path to ensure the timing is met
– Arrival time: The time that the data signal actually arrives at
certain endpoint on a path

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STA: An Example

▸ pred(n): predecessors of node n

– e.g., pred(f) = {d, e}
▸ succ(n): successors of node n
– e.g., succ(e) = {f, g}

a d f

Output pins
Input pins

b e h

24
STA: Arrival Times
▸ Assumptions
– All inputs arrive at time 0
– All gate delays = 1ns (d = 1); all wire delays = 0
▸ Questions: Arrival time (AT) of each gate output?
Minimum clock period?
ATf = maxkÎpred(f){ATk} + df

0 1 2 3
a d f 3
0
4
g 4
1
0 b e h 5
2 5
0 1
c
0

Gates are visited in a topological order 25

STA: Required Times
▸ Assumptions
– All inputs arrive at time 0
– All gate delays = 1ns (d = 1); all wire delays = 0
– Clock period = 5ns (200MHz frequency)
▸ Question: Required time (RT) of each gate output in
order to meet the clock period?
RTf = minkÎsucc(f){RTk – dk}

0 1 2
3
a d f 5
0
4
g 5
1
0 b e
2 h 5
5
3 4
c
3
Gates are visited in a reverse topological order 26
STA: Slacks

▸ In addition to the arrival time and required time of each

node, we are interested in knowing the slack (= RT - AT)
of each node / edge
– Negative slacks indicate unsatisfied timing constraints
– Positive slacks often present opportunities for additional
(area/power) optimization
– Node on the critical path have zero slacks

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STA: Use of Slacks
▸ Assumptions:
– All inputs arrive at time 0
– All gate delays = 1ns, wire delay = 0
– Clock period = 5ns
▸ Question: What is the maximum slowdown of each gate
without violating timing?
Slacki = RTi – ATi
0-0=0 1-1=0 2-2=0
3-3=0
5-3=2
0-0=0
4-4=0
5-4=1
1-1=0
0-0=0 5-5=0
2-2=0
5-5=0
3-0=3
3-0=3 4-1=3
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Next Lecture

▸Binary decision diagrams (BDDs)

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Acknowledgements

▸These slides contain/adapt materials from /

developed by
– Prof. David Pan (UT Austin)
– “VLSI Physical Design: From Graph Partitioning to
Timing Closure” authored by Prof. Andrew B. Kahng,
Prof. Jens Lienig, Prof. Igor L. Markov, Dr. Jin Hu

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