DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING (AI)

QUESTION BANK (UNIT I)

COURSE: DIGITAL ELECTRONICS CODE: BOE-410

YEAR/SEM: 2nd/ IVth SESSION: 2024-25

ALL QUESTIONS ARE FROM CO 1

CO 1: Apply concepts of Digital Binary System and implementation of Gates.

1. What is the difference between binary, decimal and hexadecimal number system?
2. How are binary digits used to express the integer and fractional parts of a number?
3. Explain the signed binary number.
4. Define the term universal gates and their applications.
5. Define the term binary codes with an example.
6. Differentiate between SOP & POS form.
7. Explain NAND and NOR as Universal Gates.
8. Interpret the binary number (1011)2 into (i) Gray code (ii) Excess-3 Code.
9. Evaluate (1011)2 - (1101)2 using 1’s and 2’s complement method.
10. Convert the following,
(i) (5162)10 = ()2
(ii) (11011001)2 = ()10
(iii) (6273)10 = ()8
(iv) (7860)10 = ()16
(v) (A23B8)16 = ()10
11. Explain the SOP and POS forms in Boolean Algebra. How are they derived?
12. Implement the Boolean function F (x, y, z) = (1,2,3,4,6,7) using NAND gates.
13. Simplify Y=∑m (3,6,7,8,10,12,14) + d (0,1,6,15) using K-map method and implement the
simplified circuit using logic gates.
14. Minimize the following Boolean function using tabulation method:
F (a, b, c, d, e) = ∑ m (0,4,12,16,19,24,27,28,29,31)
15. (i) Reduce the expression f = ∑ m (0,1,2,3,5,7,8,9,10,12,13) using K-maps and
implement the real minimal expression using NAND logic.
(ii)Design the logic circuit for a BCD to decimal decoder.
16. Explain different steps associated to Quine Mc Culsy (Tabular Method) of minimizing Boolean
Functions.
17. Design an XOR gate by using NAND gate implementation.
18. Define the De-morgans theorem of Logic Simplification for SOP & POS forms.

FACULTY:
DEEPAK SAHU
AP, DEPTT. OF ECE
 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING (AI)
QUESTION BANK (UNIT II)

COURSE: DIGITAL ELECTRONICS CODE: BOE-410

YEAR/SEM: 2nd/ IVth SESSION: 2024-25

ALL QUESTIONS ARE FROM CO 2

CO 2: Analyze and design of Combinational logic circuits.

1. Explain the function of magnitude comparator.

2. Describe the function of half and full adders. Provide truth tables and circuit diagrams.
3. Discuss the operation of BCD adders and their significance.
4. Implement 4-to-1 multiplexer using basic logic gates.
5. Elaborate the term Combinational Circuits.
6. Define BCD codes and convert (A5D8)16 into BCD number.
7. Design 4:1 multiplexer using gates.
8. Design a 4-bit adder circuit using gates.
9. Design a 3:8 Decoder circuit using gates.
10. Differentiate between the serial and parallel adder.
11. How many 4×1 multiplexers are required to implement 64×1 multiplexer.
12. Construct a full adder and implement the full adder with the help of half adders. Also implement
the full adder with NAND gates only.
13. Design a BCD adder using 4-bit parallel adder.
14. Draw and Explain 2-bit magnitude comparator. Also represent output with the help of logic
diagram.
15. Implement a 4:1multiplexer using 2:1 multiplexer.
16. Demultiplexer is decoder circuit with an additional enabling input. Do you agree with the above
statement?
17. (i)Implement a full subtractor circuit using only NAND gates. (ii)Using4:1multiplexers,
implement the following function F (A, B, C) = ∑m (0,2,3,5,7)
18. Construct BCD adder using two 4-bit binary parallel adder and logic gates.
19. Explain 4-bit magnitude comparator.
20. Design a full adder and full subtractor using NAND gates only.

FACULTY:
DEEPAK SAHU
AP, DEPTT. OF ECE
 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING (AI)
QUESTION BANK (UNIT III)

COURSE: DIGITAL ELECTRONICS CODE: BOE-410

YEAR/SEM: 2nd/ IVth SESSION: 2024-25

ALL QUESTIONS ARE FROM CO 3

CO 3: Analyze and design of Sequential logic circuits with their applications.

1. Differentiate between synchronous and asynchronous counters.

2. Explain the concept of ring counter.
3. Define the storage elements and discuss the characteristics of latches and flip-flops.
4. Explain the concept of ripple counters and synchronous counters.
5. Convert the JK flip-flop to T flip-flop and demonstrate its operation and characteristics equation.
6. Explain the term storage elements.
7. Illustrate the term sequential logic.
8. Elaborate the characteristic equations of S-R and J-K Flip-Flops.
9. Elaborate the working and circuit of a Serial-in-Serial-Out shift register.
10.Explain the working and circuit of a modulo-5 counter using gates.
11.What is the difference between characteristic and excitation table.
12.Differentiate between combinational and sequential circuits.
13.Discuss excitation table for SR, JK, T and D flip flop.
14.Design and implement MOD-10 synchronous counter.
15.For the clocked JK Flip-Flop write the state table, state equation with state.
16.Give the difference between positive and negative edge triggering.
17.A flip-flop has 5ns delay from the time the clock edge occurs to the time the output is
complemented. What is the maximum delay in a10-bit binary ripple counter that uses these flip-
flops? What is the maximum frequency the counter can operate reliably?
18. Define bi-directional shift register. Draw and explain 3-bit bi-directional shift register using D
flip-flop.
19.Design a 3-bitUP/DOWN counter with a direction control M, using J K flip-flops.
20.Explain the working of J-K Flip-Flop.
21. Describe the operations and applications of a Serial-in Parallel-out Shift Register with a neat
diagram.

FACULTY:
DEEPAK SAHU
AP, DEPTT. OF ECE
 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING (AI)
QUESTION BANK (UNIT IV)

COURSE: DIGITAL ELECTRONICS CODE: BOE-410

YEAR/SEM: 2nd/ IVth SESSION: 2024-25

ALL QUESTIONS ARE FROM CO 4

CO 4: Implement the Design procedure of Synchronous & Asynchronous Sequential Circuits.

1. What are the advantages of synchronous counters over asynchronous counters?

2. Explain the concept of hazards in digital circuits and methods to eliminate them.
3. Explain the process of state reduction and assignments in sequential circuit design.
4. Discuss the concept of race free state assignment and how it is achieved.
5. Explain the term synchronous circuits.
6. Illustrate the State reduction technique for Digital Circuits.
7. Illustrate the working and applications of Asynchronous sequential circuits.
8. Explain the term, Hazard. Define different types of Hazards along with detection and reduction of
Hazards.
9. Define term propagation delay.
10.Define race around condition in JK flip-flop.
11.Discuss Mealy and Moore finite state machine with an example.
12.Explain State Reduction and assignment with suitable example.
13.Design a sequential circuit with two flip flops, A & B and one input X. When X=0 state of the
circuit remains the same, when X =1 circuit passes through the state transition from 00 to 01 to
11 to 10 back to 00 and repeat.
14.Define critical race and non-critical race.
15.What is the significance of state assignment?
16.Design a primitive state diagram and state table for a circuit with two asynchronous
inputs (X and Y) and one output Z. This circuit is to be designed so that if any
change takes place on X and Y. Z is to change states. Assume initially that the two
inputs never change simultaneously.
17.(i) Distinguish between static and dynamic hazard. How will you determine hazard in
combinational circuits? (ii) Draw the logic diagram of the product-of-sums expression Y=
(x1+x2’) (x2+x3) Show that there is a static 0-hazard when x1 and x3 are equal to 0 and x2 goes
from 0 to 1. Find a way to remove the hazard by adding one more OR gate.
18.Define Asynchronous circuits.
19.Discuss hazards.
20.Define the state reduction steps for a machine.
21.Design a sequential circuit with two flip flops A & B and one input x when x=0, the state of the
circuit remains the same and when x=1 the circuit passes through the state transitions from 00 to
01 to 11 to 10 back to 00 and repeat.

FACULTY:
DEEPAK SAHU
AP, DEPTT. OF ECE
 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING (AI)
QUESTION BANK (UNIT V)

COURSE: DIGITAL ELECTRONICS CODE: BOE-410

YEAR/SEM: 2nd/ IVth SESSION: 2024-25

ALL QUESTIONS ARE FROM CO 5

CO 5: Apply the concept of Digital Logic Families with circuit implementation.

1. Compare and contrast different digital logic families in terms of their characteristics.
2. Explain the concept of fan-out, fan-in and noise margin in digital logic circuits.
3. Define the TTL (Transistor-Transistor-Logic) logic Family used for digital circuits.
4. Illustrate the use of logic families in digital circuits.
5. Elaborate the term Fan-in in digital circuits.
6. Why ECL is better? Implement NAND gate with DTL and TTL.
7. Define noise margin, Fan-in, Fan-out as characteristics of logic families. Implement NAND gate
with CMOS.
8. Draw a neat diagram of TTL NAND gate and explain its operation.
9. (i) Write a note on interfacing TTL with CMOS.
(ii) Explain the parameters used to characterize logic families.
10.Why is ECL logic faster than TTL?
11.Give the difference between PAL and PLOA.
12.Design 8Kx8 RAM memory system, using 1Kx8 memory ICs.
13.What do you mean by a memory?
14.Discuss different types of RAM memory cell.
15.Explain the working and structure of EEPROM cell.
16.Describe the difference between PAL & PLA using neat diagram and suitable examples.
17.Define the SRAM cell with working and circuit diagram along with applications.
18.Elaborate the PLA (Programmable Logic Array) along with working and applications.
19.Compare static RAM and dynamic RAM.
20.Design a BCD to Excess-3 code converter and implement it using a suitable PLA.
21.Describe the working principles of PLA and PAL and also their application.

FACULTY:
DEEPAK SAHU
AP, DEPTT. OF ECE