Laboratory Manual

ECEN 474/704 VLSI Circuit Design

Department of Electrical and Computer Engineering

Texas A&M University
Fall 2015

Table of Contents

Lab 0: Introduction ............................................................................................................. 1

Lab 1: Introduction to Cadence........................................................................................... 3
Lab 2: Layout Design........................................................................................................ 23
Lab 3: More Layout Techniques ....................................................................................... 32
Lab 4: MOS Device Characterization ............................................................................... 35
Lab 5: Current Mirrors ...................................................................................................... 41
Lab 6: Inverting Amplifiers .............................................................................................. 47
Lab 7: Differential Pairs.................................................................................................... 58
Lab 8: Operational Transconductance Amplifiers ............................................................ 68
Lab 9: 2 Stage Miller OTA ............................................................................................... 74

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Lab 0: Introduction

This laboratory complements the course ECEN 474/704: VLSI Circuit Design. The lab
manual details basic CMOS analog integrated Circuit design, simulation, and testing techniques.
Several tools from the Cadence Development System have been integrated into the lab to teach
students the idea of computer aided design (CAD) and to make the analog VLSI experience more
practical.
To fully appreciate the material in this lab course, the student should have a minimal
background with the following computer systems, equipment, and circuit analysis techniques.
Students should be familiar with the Linux operating system. Previous experience using a
SPICE-like circuit simulator is also important. This course does not explain the various SPICE
analyses and assumes the student is capable of configuring the appropriate SPICE analysis to
obtain the desired information from the circuit. Finally, the student should have general
familiarity with active circuit “hand” analysis. All of these prerequisites are satisfied by having
credit for ECEN 325 and ECEN 326.
The lab manual develops the concepts of analog integrated circuit design in a bottom-up
approach. First, the basic devices of CMOS circuit design, the NMOS and PMOS transistors, are
introduced and characterized. Then, one or more transistors are combined into a subcircuit such
as a differential pair, current-mirror, or simple inverter and these small circuits are analyzed.
Finally, these subcircuits are connected to form larger circuits such as operational
transconductance amplifiers and operational amplifiers, and the idea of design methodologies is
developed. Continuing with the bottom-up approach, these circuits can be combined to form
systems such as filters or data converters (not currently covered in this course). The following
figure illustrates the bottom-up approach used in the laboratory.

Figure 0-1: Bottom-Up Approach

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 The lab activities will generally be one-week labs. However there will be some longer
labs toward the end that will be two-week labs. Before the lab, the student should read through
the lab description and perform the pre-lab exercises. Generally, the pre-lab exercises are the
“hand” design for the circuit being studied. During the lab, students will perform circuit
simulations to verify their hand calculations. Tweaking circuit parameters will usually need to
be done since hand calculations will not always be 100 % accurate. Also, the integrated circuit
layout will be created. This will often require more time to do than three-hour lab time that is
allocated and will need to be finished outside of lab sometime before the next lab meeting.
Lab Report
Each student will submit one lab report for each lab. Reports are due at the beginning of
class. Lab reports will consist of not more than three typed pages of single-spaced text. Be
concise.
 TITLE PAGE
 DESCRIPTION
Include three or four sentences which describe the significant aspects of the lab. This
section specifies problems or theory that will be investigated or solved. The description is
a more detailed version of the objective.
 DESIGN
Include circuit diagrams and design formulas/calculations. All circuit diagrams must be
descriptively titled and labeled. A design formula/calculation must be given for each
component. Do not derive equations.
 RESULTS
This section usually consists of tables and SPICE plots.
 DISCUSSION
This is the most important part of the lab report. Simply justify the difference between the
theoretical and simulated values and answer and needed questions.
 CONCLUSION
Two or three sentence summary of what the lab demonstrated. The conclusion usually
responds to the problems specified in the DESCRIPTION section.

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Lab 1: Introduction to Cadence

Objectives
Learn how to login on a Linux workstation, perform basic Linux tasks, and use the
Cadence design system to simulate and layout simple circuits.
Introduction
This lab will introduce students to the computer system and software used throughout the
lab course. First, students will learn how to login and logout of a Linux workstation. Next, basic
operating system commands used to perform file management, printing, and various other tasks
will be illustrated. Finally, students will be given an overview of the Cadence Development
System.
In-class examples will demonstrate the creation of libraries, the construction of schematic
symbols, the drafting of schematics, and the layout of simple transistors. The student will apply
this knowledge to the creation of a CMOS inverter.
Logging-In/Logging-Out
In order to use the Linux machines, you must first login to the system. As with the PC
lab, enter the logon id and password at the prompts. Login using the logon ID and password
obtained from the Electrical and Computer Engineering department. This is your account and all
files stored in this area will be retained by the system after logging-out.
Using the Linux Operating System
Using the Linux operating system is similar to using other operating systems such as
DOS. Linux commands are issued to the system by typing them in a “shell” or “xterm”. Linux
commands are case sensitive so be careful when issuing a command, usually they are given in
lower-case.
The following list summarizes some basic commands required to manage the data files
you will be creating in this lab course. All Linux commands are entered from the shell or xterm
window. Do not use Linux commands for modifying, deleting, or moving any Cadence data files.

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 Table 1-1: Common UNIX Commands
ls [–la] List files in the current directory. ”l” lists with properties and “a”
also lists hidden files (ones beginning with a “.”).
cd XXXX Change the current directory to XXXX.
cd .. Change the current directory back one level.
cp XXXX YYYY Copy the file XXXX to YYYY.
mv XXXX YYYY Move file XXXX to YYYY. Also used for rename.
rm XXXX Delete the file XXXX (use /bin/rm to remove without prompt).
mkdir XXXX Create the directory XXXX.
lp -dXXXX YYYY Print the textfile or postscript file YYYY to the printer named
XXXX, where XXXX can be either “ipszac” or “hpszac”.
gedit XXXX& Start the gedit text editor program and load file XXXX.
ps –u user List processes of user.
top Check available processes and memory usage.
quota –v Check for disk space available.
kill -1 -1 Kill all my processes.
Note: The command “&” tells Linux to execute the command and return the prompt to the active
shell.

Cadence
The Cadence Development System consists of a bundle of software packages such as
schematic editors, simulators, and layout editors. This software manages the development
process for analog, digital, and mixed-mode circuits. In this course, we will strictly use the tools
associated with analog circuit design.
All the Cadence design tools are managed by a software package called the Design
Framework II. This program supervises a common database which holds all circuit information
including schematics, layouts, and simulation data.
From the Design Framework II also known as the "framework", we can invoke a program
called the Library Manager which governs the storage of circuit data. We can access libraries
and the components of the libraries called cells.
Also, from the framework we can invoke the schematic entry editor called "Composer".
Composer is used to draw circuit diagrams and draw circuit symbols.
A program called "Virtuoso Layout Suite" is used for creating integrated circuit layouts.
The layout is used to create the masks which are used in the integrated circuit fabrication
process.
Finally, circuit simulation is handled through an interface called Analog Design
Environment (ADE). This interface can be used to invoke various simulators including Hspice,
Spectre, and Verilog. We will be using the Spectre simulator in this course.

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Starting Cadence Using Linux Workstations in CVLB 324:
You can connect to ECE servers or lab workstations using secure shell (ssh) from another
computer on campus. If the computer has Linux or Unix operating system, you can use the
following command to connect to lab workstations:
ssh -X hostname
You can also connect to ECE Linux servers as follows:
ssh -X apollo.ece.tamu.edu
ssh -X hera.ece.tamu.edu
If you are connecting from a computer that has Windows operating system, you need to have an
ssh client and an X-server installed. Make sure that X11 connections are tunneled within the
settings of ssh client you are using. Once you login, you can start Cadence using the following
commands:
cd cadence
/disk/amsc/bin/ibm180 &
Starting Cadence from a Workstation within the Campus:
After logging in apollo or hera, open a Terminal window. You need to create a directory before
you run Cadence for the first time using the following command:
mkdir cadence
The above step is needed only once. To start Cadence, use the following commands:
cd cadence
/disk/amsc/bin/ibm180 &

This will load Cadence. The Command Interpreter Window (CIW) will now load as shown in
Figure 1-1.

Figure 1-1: The Cadence CIW

Starting a Design
From the CIW select Tools → Library Manager to load the Library Manager (Figure
1-2). The Library Manager stores all designs in a hierarchal manner. A library is a collection of
cells. For example, if you had a digital circuits library named Digital, it will have several cells
included in it. These cells will be inverters, nand gates, nor gates, multiplexers, etc. Each cell

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has different views. These views will in general be things such as symbols, schematics, or
layouts of each cell.

Figure 1-2: Library Manager

The first thing you need to do to start a design is create a library to store the cells you will
be designing in this lab. Let’s call this library “ee474”. From the Library Manager select File →
New → Library. Name the library “ee474” (without quotes) and select OK. In the window that
appears select “Attach to an existing techfile” (Figure 1-3) and select OK. In the next window
make sure that cmhv7sf Technology library is selected and select OK.

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 Figure 1-3: Creating a Library and Attaching a Tech Library
Creating a Schematic
The first circuit we will design is a simple inverter. Select which library you want to put
the cell into, in this case “ee474”, and then File → New → Cell View. Name your cell
INVERTER. The application you want to use here is Schematics L as seen in Fig. 1-4.

Figure 1-4: Creating a new cell view

After selecting OK, the schematic window opens. We wish to add two transistors so that
we can make an inverter. To do this we need to add an instance. You can do this by either
clicking Create → Instance or by pressing “i” on the keyboard. A window titled “Component
Browser” should pop up. Hit the “Browse” button, and make sure that the library cmhv7sv is
selected. Select nfetx and then symbol. Go back to the schematic and select where you would
like to add the NMOS transistor. Go back to the Component Browser and select pfetx and then
symbol. Add this transistor to your schematic. Hit ESC to exit the Add Instance mode.

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 Connect components together using wires. You can select Add → Wire or use the “w”
hotkey.
Pins identify the inputs and outputs of the schematic. Click Add → Pin or use the “p”
hotkey. Pin names and directions must be consistent between the symbol, schematic, and layout.
The name uniquely identifies the pin while the direction indicates the usage of the pin. Using the
inputOutput direction is recommended for power supplies.
To change the properties of a device use Edit → Properties → Objects or use the “q”
hotkey. In order to compensate for lower mobility in the PMOS, try changing the width of the
PMOS transistor from 500n to 1u. Place pins on the wires each net. Beware of the direction of
pins. When finished, your schematic should resemble Fig. 1-5.
Important: Use all uppercase letters in the PDK when naming pins and/or nets.

Figure 1-5: Inverter schematic

Select Design → Check and Save, or press F8 to save your schematic and make sure that
there are no errors or warnings.

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Creating a Symbol
From the schematic window, select Create → Cellview → From Cellview, and click
OK (see Fig. 1-6). In the next window, arrange the pin specifications and click OK. The symbol
editor will appear with the default symbol. Using the editor, modify the symbol so that it will
resemble the one shown in Figure 1-7.

Figure 1-6: Creating Symbol from Schematic

Figure 1-7: Final Inverter Symbol

Useful Tip: Pressing Ctrl + D allows to deselect any object in schematic, symbol, and layout.

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Creating a Layout
After the schematic and symbol have been designed, it is time to move onto the layout of
the circuit. From the library manager select File → New → Cell View. Select Layout L as the
application (Figure 1). After clicking OK, Virtuoso Layout Suite should open as shown in
Figure 1-9.

Figure 1-8: Creating a layout cell view

Figure 1-9: Virtuoso Layout Suite

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 Figure 1-10: Uncheck Gravity on
First, go to the Options → Editor to disable “Gravity On” in order to effectively place
and route objects in the layout . The layout consists of instances, paths, rectangles and pins. A
transistor can be inserted into the layout using Create → Instance, or press i and selecting nfetx
layout or pfetx layout after clicking on Browse button. Use “Shift-f” hotkey to see the layers
after inserting the instances. Properties such as W and L of the transistors/metal wires can be
modified from the Properties window (“q” hotkey after selection).
Alternatively, transistors can be created from scratch (not recommended) by drawing
rectangles for its gate, diffusion, and metal regions. The gate region is created by drawing a
rectangle with poly (drw) or "r" on the keyboard. The diffusions for a transistor are created by
drawing a rectangle with the active (drw) layer. The intersection of poly and active regions
defines the size (length and width) of the transistors. In order to define whether a transistor is
NMOS or PMOS, nselect (drw) or pselect (drw) needs to surround the active area. The design
rules describe minimum spacing and size requirements for various rectangles. Some basic
design rules for this technology are shown in Figure 1-11.
Substrate contacts and vias between layers of metal can also be inserted using Create →
Via or press “o”. Use RX_M1 via for both NTAP and PTAP(substrate connections). Enclose

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NTAP with NW, PTAP with BP. To add a pin, select Create → Pin. “Terminal Name” should
be the name of the pin in the schematic. Make sure that the “Display Pin Name” option is
checked in the Options → Display so that the pin name will appear in the layout. Pin Layer
should be the same as the metal layer that it is connecting to but the its Purpose should be label.
Design Rule Check needs to be performed during the placement of instances and
throughout the layout development. To avoid extra work later, DRC needs to be run as often as
possible during the completion of layout (see the next section). When finished, enclose the
entire layout with GRLOGIC layer. And, you should obtain a layout of the inverter which
resembles Figure 1-12.
After the layout is done, several steps have to be followed to insure that the layout is
correct. These steps involve performing the analysis in the following sections.

Figure 1-11: Basic design rules

Figure 1-12: Inverter layout

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 Table 1-2: Post-Layout Steps
DRC Design Rule Check. Checks physical layout data against fabrication-specific
rules. Typical checks include spacing, enclosure and overlap.
LVS Layout Versus Schematic. Compares a physical layout design to the schematic
from where it was designed.
Extract Device parameter and connectivity are extracted from the layout in order to
perform ERC, Short Locator, LVS and post-layout simulation and analysis.

DRC
To run DRC for the layout, select Calibre → Run DRC. You do not need to make any
modifications to the window that opens up with default setting. The total number of errors will
show up in the RVE window as seen in Figure 1-12. DRC check should be performed not only
after the layout is completed, but also during the layout work as mentioned earlier.

Figure 1-13: RVE window showing DRC result

The errors will usually show up in the layout with highlights. To have Cadence address
what and where the error is, double click the error and number, respectively. And, Cadence will
explain what design rules are broken. Adjust the layout to fix these errors and then rerun DRC
until you have no design rule errors except density violations that can be waivered until design
rule of the layout is evaluated at the full chip level.

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LVS
From the schematic window, select IBM_PDK→Netlist→Create CDL Netlist to
produce a netlist for LVS. Confirm “netlist generation succeeded” message. And, then select
IBM_PDK → Netlist → CDL pre_Process for LVS. Type ~/LVS for Run Directory, then click
on Refresh Files List. Click on the *.netlist file created in the first netlisting step, then click on
<< to list file to Process, then hit OK as shown in Figure 1-14. Finally, the netlist for LVS is
created under the name of *.netlist.lvs.

Figure 1-14: Netlist generation from schematic for LVS

On the layout window, select Calibre → Run LVS. In the Calibre Interactive – nmLVS
window as shown in Figure, click on Inputs and select Netlist tap. Deselect “Export from
schematic viewer” and choose the *.netlist.lvs file generated in the previous step. Click Run
LVS. The LVS window is shown in Figure 1-15. Make sure Rewiring, Device Fixing, and
Terminals are selected under LVS Options. Click Run. A window should pop up once LVS has
completed saying that the job succeeded. Click OK. From the Calibre - RVE window popped
up, smile emoticon should appear to verify match between the schematic and the layout. If they
do not match, go back to the LVS window. Select Error Display to find out what your errors are.
Adjust the layout to match, rerun DRC, and LVS until the netlists match.

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Figure 1-15: Calibre Interactive – nmLVS window

Figure 1-16: Calibre – RVE LVS window

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Extract
Once DRC and LVS are successful, you can now extract the layout for post-layout simulation.
On the terminal window as a one-time procedure, copy cellmap file to your local directory for
Extraction by executing a command

cp /disk/amsc/IBM_PDK/cmhv7sf/rel/Calibre/xRC/*.cellmap ~/PEX

From the layout window select Calibre → Run PEX. In the Calibre Interactive – PEX
wiondow, click on Inputs and then Netlist. Choose the same *.netlist.lvs file created during LVS
procedure. Click on Outputs and then change the format to CALVIEW on the netlist tap as
shown in Figure 1-17.

Figure 1-17: Calibre Interactive - PEX windows

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 Figure 1-18: Calibre View Setup window

In the middle of the extraction process, Calibre View Setup window will pop up as shown in
Figure 1-18. Locate the cellmap file which was copied to your local directory in the previous
step.

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Simulating the Schematic
To test the inverter, we need to create a new schematic cell view called
“INVERTER_tb” in order to build a test bench. To simulate the design, add the inverter
symbol, signal sources, power supplies, and loads as illustrated in Figure 1-1.

Figure 1-19: Inverter test-bench schematic

Start the simulator environment by selecting Launch → ADE L. The simulator should
appear in a few moments. Select Setup → Simulator/Directory/Host and verify that spectre is
the simulator.
Next we need to configure the environment to run our first simulation. In the ADE
window, select Analyses → Choose. Select “dc”, check “Component Parameter”, click on
“Select Component” and then click on the desired voltage source in the schematic to sweep. In
this case we want to sweep the input voltage source which is V2 in Figure 1-20. Select “dc” as
the variable to sweep when the popup window opens. We wish to sweep the source from the
negative supply to the positive supply, so input 0 into “Start” and 1.8 into “Stop”. Select OK.

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 Figure 1- 20: Analog Design Environment and dc analysis setup
The simulator should now be configured to run the simulation. Select Simulation →
Netlist and Run. Once the simulation is complete, we can plot any output using Results →
Direct Plot → DC, then clicking on the net (or nets) in the schematic window, followed by ESC.
Alternatively, we can plot waveforms using the calculator. To access the calculator,
select Tools → Calculator in the Analog Environment. Since our analysis that was ran was a dc
sweep, click the “vs” button (The “v” is for voltage and the “s” is for DC sweep). Next, click on
the output node in the schematic. You can now plot the output as a function of the swept
variable, which in this case is the inverter input, by selecting Tools → Plot. Your output
waveform should resemble Figure 1-21.

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 Figure 1-21: Inverter Input & output plot

Simulating the Extracted Layout

For post-layout simulation to account for various parasitics, you must prioritize extracted
caliber in the view list over schematic and/or veriloga in the spectre environment before running
simulations.
In the Analog Environment, select Setup → Environment. In the field labeled “Switch
View List”, add “calibre” before “schematic” as shown in Figure 1-421. All other steps in
simulation of the extracted view will now be the same as they were for simulating the schematic.

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 Figure 1-21: Adding extracted view to switch view list

Prelab
No prelab lab report is required this week other than the printouts listed in the Prelab
section.

Lab Report
This exercise is to be done during the lab under supervision of the TA. Turn in print outs
of the following as a lab report next week:
1) Inverter schematic
2) Inverter symbol
3) DC sweep output graph showing the inverter was simulated
4) Inverter layout
5) Copy of the LVS output file showing that the netlists match
6) Post-layout Simulation
7) Discussion

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 Figure 1-4: Adding extracted view to switch view list

Prelab
No prelab lab report is required this week other than the printouts listed in the Prelab
section.

Lab Report
This exercise is to be done during the lab under supervision of the TA. Turn in print outs
of the following as a lab report next week:
1) Inverter schematic
2) Inverter symbol
3) DC sweep output graph showing the inverter was simulated
4) Inverter layout
5) Copy of the LVS output file showing that the netlists match

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Lab 2: Layout Design

Objective
Learn techniques for successful integrated circuit layout design.
Introduction
In this lab you will learn in detail how to generate a simple transistor layout. Next,
techniques will be developed for generating optimal layouts of wide transistors and matched
transistors. Layout techniques for resistors and capacitors will also be illustrated. Finally, you
will use all of these layout techniques to produce a two-stage opamp layout (Lab 3).
Layout Techniques
Transistors

In Lab 1 you learned how to layout small size transistors. Most analog designs will not
be limited to these small width transistors, thus special layout techniques need to be learned to
layout large width MOSFETS. Luckily, wide transistors can be broken into parallel
combinations of small width transistors as seen in Figure 2-1. By doing this horizontal
expansion technique for the wide transistor, the drain and source area can be reduced which
decreases parasitic capacitance and resistance.

Figure 2-1: Wide MOS transistor layout

Another good layout technique is to use “dummy” transistors on both ends of a transistor
layout. These dummy transistors insure that the etching and diffusion processes occur equally
over all segments of the transistor layout.

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 Figure 2-2: Dummy transistor layout
Notice the gate, drain, and source are connected together which keeps it from conducting
any current. This shorted transistor is connected to the drain or source of the functional
transistor. Another alternative for dummy transistors is to have the gate and source tied together.
When laying out any device the key is symmetry, especially when laying out fully-
differential components. For matched devices, use interdigitized or common-centroid layout
techniques. A matched device is one where two transistors need to have exactly the same
geometries. Examples include current mirrors and differential pairs.
An interdigitized layout is shown in Figure 2-3. Notice that the two transistors have been
split into smaller size devices and interleaved. This layout minimizes the effects of process
variations on the parameters of the transistors.
The idea behind splitting a transistor up is to average the process parameter gradient over
the area of the matched devices. For example, the process variation of KP and of the
transconductance parameter on the wafer is characterized by a global variation and a local
variation. Global variations appear as gradients on the wafer as in Figure 2-4. However, local
variations describe the random change in the parameter from one point on the chip to another
nearby point. By using layout techniques such as interdigitized and common-centroid, the
process variation can hopefully be averaged out among the matched devices.
When laying out wider matched transistors the common-centroid layout may be a better
choice. This layout technique is illustrated in Figure 2-5 for the case of 8 matched M1 and M2
transistors of a differential pair.

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 D D D D

G1 G2 G1 G2

a) b)

S S

G2
D1

D1 S D2 S D1 S D2 S D1

S
D2
G1

c)

G2
D1

S D1 S D2 S D1 S D2 S

S
D2
G1

d)

Figure 2-3: Interdigitized layout of a differential pair

a) Differential pair
b) Horizontal expansion
c) Interdigitized layout (Drain areas are different. Common centroid.)
d) Interdigitized layout (Drain areas are equal. Not common centroid.)

KP  27 A V 2

KP  20A V 2
KP  29 A V 2

KP  25A V 2

KP  33A V 2

Figure 2-4: Gradient of KP on a wafer

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 Figure 2-5: Common-centroid layout of a differential pair

The idea behind the common-centroid layout is to average linear processing gradients
that affect the transistors’ electrical properties. Common-centroid layouts should have the
centroid (center of mass) of each transistor positioned at the same location. The following
examples illustrate what is common-centroid and what is not common-centroid.

Figure 2-6: Common-centroid examples

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Capacitors

A capacitor is formed when an insulator separates two conducting sheets. Various types of
monolithic capacitors using MOSFET, MIM(metal-insulator-metal), poly-to-poly, MOM(metal-
oxided-metal), etc can be fabricated on integrated circuits. In this lab MOM capacitor will be
practiced. Forming a MOM capacitor is by using lateral flux between plates formed by
interdigitated finger metal layers as shown in Fig. The MOM cap has been widely used due to
the following characteristics:

 High capacitance density (Please, refer to the design manual)

 Low parasitic capacitance
 Good linearity with dimension
 Symmetric plate design, thus good matching characteristic
 No additional masks or other fab process, i.e. freely available with modern CMOS

MOM capacitors can be constructed of any number of consecutive metal levels connected in
parallel with vias. The model support variable dimensions for width(W) and length(L).
Normally, lowest metal layers (e.g, M1 – M5) with fixed metal line width and spacing are used
in order to allow maximum capacitance density and high yield. In order to reduce parasitic
capacitance induced between the bottom metal layer and the substrate, lower level of metal could
be removed by trading-off capacitance density.

Figure 2-7: Metal-oxide-metal Capacitor

Thus, the total capacitance can be calculated by

C C W L 2d
where:
Cf = capacitance density in fF/um2 (Refer to the design manual)

W = total width in um

L = total length in um

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 Like matched MOSFETS, the common-centroid layout technique can be employed for
matched capacitors. Figure 2-7 gives a simplified layout floor plan for two equally sized, well-
matched capacitors.

C2 C1 C2 C1

C1 C2 C1 C2

C2 C1 C2 C1

C1 C2 C1 C2

Figure 2-7: Common-centroid capacitor layout

Remember, the purpose of using the unit capacitor is to keep the ratio of the areas and
perimeters the same. This prevents (delta) variations in capacitor dimensions from changing the
capacitor ratio (See the lecture note on the Layout techniques for proof). If a non-integral number
of unit capacitors are required then the perimeters and areas can still be kept the same. If the ratio
of capacitors is where 1<N<2, then we can add a non-unit capacitor Cnu = NCu to
form C2 and have equal perimeter/Area. The unit capacitor has side length L0 and the non-unit
capacitor has the length Lnu and the width Wnu. Use the following formulas to calculate the side
lengths of the non-unit capacitor:
1

Keep the unit capacitor side length L0 in the range from 10m-25m. Also, within the
capacitor array, use a consistent method of routing lines between the capacitor segments. Each
unit capacitor should be surrounded by similar routing lines. Use multiple contacts to lower
series resistance. For capacitors near the edge of the array, use “dummy” routing lines. Also, be
sure that parasitic capacitance formed by overlapping conductors is the same for the matched
capacitors.

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Resistors

As for capacitors, many different types of resistors are available in integrated circuits.
Other than active devices biased to act as resistors, we can use the inherent resistivity of the
polysilicon or diffusions to create resistors. As an example, the following table shows the typical
values of a poly resistance for the IBM 180nm process that we will be using to design circuits.

Process OPRPPRES
Description
Parameter Min Nominal Max. Unit

Rs Sheet Resistance(0V,25°C) 0.1518 0.165 0.1782 kΩ/sq

Rcon Contact Resistance 0.005 0.015 0.050 kΩ-μm

The total resistance of a monolithic resistor is the sum of the contact resistance and the
ohmic resistance of the diffusion material. The following formula can be used to estimate
resistance for polysilicon and diffusion resistors:
L Rcon
R nom  R S   2
W W
where:
RS is the resistance per square [kΩ/sq] for the chosen resistor type
L is the length [μm]of the resistor
W is the width [μm] of the transistor
Rcon is the contact [kΩ-μm] resistance
Figure 2-8 shows a layout of one of polysilicon in the design kit. The resistor is built in
by containing a strip of poly and poly-M1 contacts. The length of the OP mask determines the
length of the OP resistor.

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 Figure 2-8: Poly resistor(OPRPPRES) layout
If the circuit operation depends on the ratio of resistance, then good matching can be
obtained by using interdigitized or common-centroid techniques. When matching resistors, be
sure to keep device orientation and sizes the same. Also, since contacts contribute resistance,
keep the contacts in the same ratio. An interdigitized layout of resistors is illustrated in Figure
2-9. Notice that the interconnecting metal is overlapping the resistor array and non-overlapping
the resistor array in equal lengths for the two resistors.

Figure 2-9: Interdigitized resistor layout

30
Prelab
Answer the following questions. No computer work is required for the prelab. The prelab is due
at the beginning of class.

1) What are the absolute minimum dimensions of a transistor? Explain your reasoning.
Remember to consider minimum contact size. Do we actually use this minimum size of
do we use a slightly larger size for convenience.
2) Draw a common-centroid layout of a simple current mirror with equal size transistors of
L = 180nm and W = 16 μm. Use a finger width of 500nm devices for each transistor
segment. Remember to draw drain, source, gate, and bulk connections. Use dummy
transistors and all other good layout techniques learned in the lab. Include a floor plan.
3) Design a common-centroid layout for a MOM capacitor array using only M4. The
capacitors have a ratio of 1.3:1. The capacitor array should consist of eight unit
capacitors and one non-unit capacitor. Determine the form of the common-centroid
layout and interconnect the capacitors. Each unit capacitance should have a separate top
and bottom plate. Do not use a common bottom plate. Use the techniques described in
the lab manual to give good matching. Also, give the size of the non-unit capacitor. The
unit capacitor is 10.56μm X 10.56 μm (W × L).
4) Design a four matched polysilicon (OPRPPRES) resistor pairs to realize a resistance of
12kΩ each. Remember to account for contact resistance. Determine the approximate
length and width of the diffusion. Use an interdigitized layout with six resistance
segments. Use good layout techniques.

Lab
1. Practice good layout techniques by laying out the following:
A) Current-mirror from prelab question #2
B) Capacitor array from prelab question #3
C) Matched resistors from prelab question #4
2. Include in the lab report
A) Schematic printout
B) Layout printout
C) LVS printout showing that layout and schematic match

31
Lab 3: More Layout Techniques

Guard Rings
When laying out sensitive analog blocks, we need to help minimize the effect of substrate
noise. One way to do this is with a guard ring. A guard ring is an array of substrate contacts
which will then be connected to a clean supply (VSS or ground).
Figure 3-1 illustrates an example of a guard ring. This example shows a ring with a
single contact. For more isolation, this ring can be made wider with more substrate contacts.
It is also important to note that the PMOS devices have an n-well contact ring
surrounding them. This is good practice because it helps to act as an additional guard ring while
also minimizing the possibility of latch up between the n-well and substrate.

Figure 3-1: Guard ring illustration

32
Prelab
There is no prelab work required for this lab.
Lab
Use good layout techniques with guard rings to create a layout of the two-stage op-amp in Figure
3-2. Table 3-1 lists the transistor sizes for the op-amp. Figure 3-3 is a suggested floor plan to
use. In this floor plan each transistor has a finger width of 720nm.

Include in the lab report:

A) Schematic printout
B) Layout printout
C) LVS printout showing that layout and schematic match

Figure 3-2: Two-Stage Op-Amp

33
 Table 3-1: Transistor Sizes
MOSFET W L
M1 2.88u 180n
M2 2.88u 180n
M3 5.76u 180n
M4 5.76u 180n
M5 1.44u 180n
M6 2.88u 180n
M7 5.76u 180n
M8 23.04u 180n

D D D D D D D D M8 M8 M8 M8 M8 M8 M8 M8 D

D M3 M3 M4 M4 M3 M3 D M8 M8 M8 M8 M8 M8 M8 M8 D

D M4 M4 D D M4 M4 D M8 M8 M8 M8 M8 M8 M8 M8 D

D M3 M3 M4 M4 M3 M3 D M8 M8 M8 M8 M8 M8 M8 M8 D

D M1 M1 M2 M2 M2 M2 M1 M1 D D D D D D D D

D M5 M6 M6 M7 M7 M7 M7 M7 M7 M7 M7 M6 M6 M5 D D

CC

Figure 3-3: Floor plan for two-stage op-amp layout

34
Lab 4: MOS Device Characterization

Objective
Understand and measure transistor model parameters.
Introduction
In this lab you will review basic transistor operation and learn how the SPICE model
parameters relate to the physical structure and electrical equations of the device. Then you will
measure various electrical model parameters: VT0, λ, KP, and γ.
Transistor Operation
MOS transistors are the fundamental devices of CMOS integrated circuits. The
schematic symbols for an NMOS and PMOS transistor are illustrated in Figure 4-1 and Figure 4-
2.

D S

G B G B

S D
Figure 4-1: NMOS Transistor Figure 4-2: PMOS Transistor
A cross sectional view of an NMOS transistor is shown in Figure 4-3. When the
potential difference between the source (S) and drain (D) is small (~ 0V), and a large potential (>
VT0) is applied between the gate (G) and source, the transistor will be operating in the linear or
ohmic region. The positive gate potential causes electrons to gather below the surface of the
substrate near the gate in a process called “inversion”. This region of mobile charge forms a
“channel” between the source and drain. The amount of charge is a function of the gate
capacitance (Cox) and the gate-to-source overdrive voltage:
Q m  C ox VGS  VT0 

S G D

+++++++++++++

------------------

N+ N+
Qm

P-

Figure 4-3: Cross-sectional view of an NMOS transistor

35
 The term VT0 is the threshold voltage. When the gate-to-source voltage (VGS), exceeds
this value, an inversion region is formed. Before reaching the inversion region, as the gate-to-
source voltage is increased, the transistor passes through the accumulation region where holes
are repelled from and electrons are attracted to the substrate region under the gate. Immediately
before inversion, the transistor reaches the depletion region (weak-inversion) when the gate-to-
source voltage is approximately equal to the threshold voltage. In this region a very small
current flows.
In the linear region, the MOSFET acts as a voltage-controlled resistor. Resistance is
determined by VGS, transistor size, and process parameters.
When the drain-to-source voltage (VDS) is increased, the quantity and distribution of
mobile charge carriers becomes a function of VDS as well. Now the total charge is given by:
Q m  C ox VGS  VT  VDS 
The threshold voltage (now denoted as VT) becomes a function of VDS. The distribution
of this charge is such that Qm is greater near the source and less near the drain. To find the
channel conductance, the charge must be recast as a function of position Qm(y) and integrated
from the source to drain. Since the charge was a function of VDS, the conductance depends on
VDS. The channel current becomes:
W
I D  μ 0  C ox  VGS  VT   VDS
L
or
W
I D  KP  VGS  VT   VDS
L
As VDS increases, eventually the drain current saturates. That is, an increase in VDS does
not cause an increase in current. The saturation voltage depends on VGS and is given by VDS(sat)
= VGS – VT. The equation for the drain current becomes:
1 W
 KP  VGS  VT0 
2
ID 
2 L
At this point the transistor is operating in the saturation region. This region is commonly
used for amplification applications. In saturation, ID actually depends weakly on VDS through the
parameter λ. Also, the threshold voltage depends on the bulk-to-source voltage (VBS) through
the parameter γ. A better equation for the MOSFET in saturation is given by:
1 W
 KP  VGS  VT   1  λ  VDS 
2
ID 
2 L
In the equation above VT includes the effects of VBS.
When VGS is less than the threshold voltage, the channel also conducts current. This
region of operation is called weak-inversion or sub-threshold and is characterized by an
exponential relationship between VGS and ID. Also, when VGS becomes very large the charge
carrier’s velocity no longer increases with the applied voltage. This region is known as

36
saturation and has an ID that depends linearly on VGS as opposed to the squared relation shown
above.
Figure 4-4 is a three-dimensional cross-sectional view of a MOSFET. Notice in the
figure the overlap between the gate region and the active regions. The overlap forms parasitic
capacitors CGS and CGD.

CGB=CGBO*L GATE

CGD=CGDO*W CGS=CGSO*W
RD=RSH*NRD RS=RSH*NRS

DRAIN SOURCE
POLY Si
WM
LM

TOX OXIDE

N+ L LD N+ XJ

CJD=CJ*AD P- C JS=CJ*AS

CSWD=CJ*PD NSUB CSWS=CJ*PS

Figure 4-4: Physical structure of a MOSFET

The reverse-biased junctions between the active regions and the bulk form the parasitic
capacitors CDB and CSB. The conductivity of the active regions forms the parasitic resistors RD
and RS. A schematic symbol with the parasitic resistors and capacitors is illustrated in Figure
4-5.

DRAIN

RD

CGD CDB=CJD+CSWD

GATE BULK
RG RB

CGS CSB=CJS+CSWS

RS

SOURCE

Figure 4-5: MOSFET parasitic resistors and capacitors

37
Device Characterization
To characterize the MOSFETs so that hand calculations can be done in the future,
simulations need to be done to measure KP, VT0, λ, and γ.
λ Measurement

To measure λ you need to do a DC sweep of VDS and plot ID as shown in Figure 4-6.
Each curve represents a different VGS value. Any one of these curves can be used to calculate λ.
Make sure that VBS is 0V for this simulation. The formula for calculating λ given two points on
the saturation portion of a single curve is:
I D2  I D1
λ
I D1  VDS2  I D2  VDS1

Figure 4-6: NMOS I-V characteristic plot

38
VT0 Measurement

VT0 can also be obtained from Figure 4-6. Using the saturation portion of two curves
with equal VDS, VT0 can be calculated as
I D1
VGS1   VGS2
I D2
VT0 
I D1
1
I D2
KP Measurement

Knowing λ and VT0, KP can easily be found from the equation for MOSFET drain current
in the saturation region. A little algebra gives that KP is
2  ID
KP 
W
 VGS  VT0   1  λ  VDS 
2

L
γ Measurement

To obtain γ you must first give the transistor a non-zero VBS. Next calculate the new VT
using the same procedure that you used to obtain VT0. γ is then given as
VT  VT0
γ
Φ 0  VBS  Φ 0
Φ0 is the built-in potential of an open-circuit pn junction and can usually be approximated
to be 0.9V.
Simulation
In order to obtain the ID vs. VDS vs. VGS plot of Figure 4-6, you need to setup your
schematic as shown in Figure 4-7. A simple DC sweep of VDS needs to be performed, however
to get multiple I-V curves, a parametric analysis needs to be run.
To do a parametric sweep on your VGS voltage source, you need to setup a design
variable in Cadence. First, modify the properties of the VGS source. Instead of giving a constant
DC voltage, make it a variable by naming it “vgs”. In the Analog Environment window, select
Variables → Edit. In the “Name” field type “vgs”. You can give a value to the variable that
Cadence will use for all simulations other than the parametric sweep. Once finished, select
“Add” and then “OK”.
To get to the parametric analysis simulation, go to the Analog Environment and select
Tools → Parametric Analysis. In the “Variable Name” field add “vgs” and enter sweep
parameters. Choose Analysis → Start to run the parametric sweep. Once the simulation is
finished, use the calculator to plot ID.

39
 ID

VGS VBS VDS

Figure 4-7: Simulation Test Setup

Prelab
No computer work is required for the prelab.
1) Derive the equations for the four electrical parameters given in the Device Characterization
portion of the manual.
Lab
1) Use Cadence to produce ID vs. VDS vs. VGS plots similar to Figure 4-6 for transistors of size
1.26u/180n and 2.52u/180n. Sweep VGS from 0.8 to 1.2 with 5 steps.
2) Extract the four electrical parameters (λ, VTO, KP, γ) for both NMOS and PMOS transistors
for both transistor sizes.
3) Compare the extracted parameters to the equivalent model parameters given by the simulator
(see the note below). Compute the percent difference and explain any discrepancies.

Note: To find the model files used, go to the Analog Environment window. Select Setup →
Model Libraries. You can also see the model parameters from “Results → Print → Model
Parameters” and clicking on the transistor after running dc analysis with “Save DC Operating
Point” option.

40
Lab 5: Current Mirrors

Objective
Design, simulate, layout, and test various current-mirror circuits.
Introduction
Current mirrors are fundamental building blocks of analog integrated circuits.
Operational amplifiers, operational transconductance amplifiers, and biasing networks are
examples of circuits that are composed of current mirrors. Analog integrated circuit
implementation techniques such as current-mode and switched current use current mirrors as the
basic circuit element. The design and layout of current mirrors is therefore an important aspect
of successful analog circuit design.
In the simplest form, a current mirror is composed of two transistors as shown in Figure
5-1. Transistor M1 is diode connected and acts as the low-impedance input of the current mirror.
The drain of M2 is the output of the current mirror.

Figure 5-1: Simple current mirror

Since the gate-to-source voltage is the same for both transistors, then, according to the
first-order MOSFET model, the drain currents will be equal. This assumes that the transistor
sizes are equal as well as the process parameters.
A current mirror is used to mirror the input current into the output branch. A current (Iin)
entering the diode connected transistor establishes a gate voltage (VGS). The gate voltage causes
Iout to flow through the output transistor. Notice that the input transistor will show a low small-
signal resistance (1/gm) and the output transistor will exhibit a high small-signal resistance (ro).
If the ratio of the transistors is changed, then the current-mirror acts as a current
amplifier. The gain of the amplifier is given by:
 W2 
 L 2 
Ai  
 W1 
 L 
 1

41
 The above analysis assumed ideal operation of the current mirrors meaning that the drain
currents are independent of VDS; however, due to channel length modulation we know this not to
be true. The following equation, which you should be familiar with by now, illustrates the
dependence of drain current on VDS.
1 W
 VGS  VT   1  λ  VDS 
2
ID   KP 
2 L
The excess current due to differences in VDS1 and VDS2 will cause a difference in ID1 and
ID2. To reduce “lambda” effects, the drain-to-source voltages of the two transistors need to be
kept equal.
Another non-ideality of current mirrors is the limited range of VDS2. Since M1 remains in
saturation for all input currents due to its diode connected configuration, M2 needs to be kept in
saturation to assume proper operation. If VDS2 drops too low, M2 will enter the triode region, and
the output current will be much less than what is wanted. The minimum output voltage required
for the current mirror is sometimes referred to as the compliance voltage. For the simple current
mirror, the compliance voltage is VDS,sat2.
The ratio of the input to output currents is also process dependent. Because of this
process dependency, good layout techniques such as interdigitized and common-centroid
methods are used to layout current mirrors.
As previously mentioned, to obtain good matching between input and output currents, the
drain-to-source voltages of M1 and M2 must be kept equal. One way to achieve this is by using a
cascode current mirror which is pictured in Figure 5-2.

Figure 5-2: Cascode current mirror

Transistors M1 and M2 determine the ratio of the input and output currents. M3 biases M4
which is used to control the drain voltage of M2. If designed correctly, VDS1 is approximately
equal to VDS2. The benefits of the cascode current mirror are better matching of output currents

42
and larger output resistance. The disadvantage is that a larger compliance voltage is needed to
keep both M2 and M4 in saturation. To find the compliance voltage we will use Figure 5-3.

Figure 5-3: Cascode current mirror

Node 1: The voltage here is VGS1 = VT + VDS,sat1.

Node 2: For good matching between input and output currents, we want VDS1 and VDS2
to be equal. Thus, the voltage at node 2 is also VT + VDS,sat1.
Node 3: The minimum compliance voltage will be the minimum voltage to keep M3 and
M4 in saturation. This will be VT + VDS,sat1 + VDS,sat2.
As you can see, adding the cascode transistor does not just increase the required
compliance voltage by one VDS,sat, it also increases it by a threshold voltage. If we have 200 mV
overdrive voltages on all transistors with threshold voltages of 700 mV, the output voltage will
have to be greater than 1.1 V. This makes cascode current mirrors not desirable for modern
processes since the required supply voltage is already small.
In order to have the good current matching capabilities of the cascode current mirror,
while not having such a large compliance voltage, we can use the low voltage cascode current
mirror as pictured in Figure 5-4. If designed correctly, M1 and M2 will be biased such that they
are at the edge of saturation, thus their VDS ≈ VDS,sat. If this is the case then the compliance
voltage drops to VDS,sat2 + VDS,sat4. This is one whole threshold voltage less than the regular
cascode current mirror of Figure 5-2. MB will usually have a small W/L ratio, and should have a
VDS,sat = VDS,sat1 + VDS,sat2.

43
 VDD VDD

Ibias Iin Iout

M3
MB M4

M1 M2

Figure 5-4: Low voltage cascode current mirror

Simulating Current Mirrors

Figure 5-5: Current mirror test configuration

Once a current mirror has been designed (hand calculations), use the test configuration in
Figure 5-5. Iin is whatever DC current you designed your current mirror to have. Vout is a DC
source that will be varied in a DC sweep simulation. Plot ID2 vs. Vout, and you should get a plot
which resembles Figure 5-6. The compliance voltage will be the point on the plots where Iout
begins to change rapidly indicating the output transistor is entering the linear region of operation.
In order to find the output impedance an AC simulation needs to be run. First, give Vout a
DC voltage greater than VDS,sat (say 1V) with an AC voltage of 1V. The output impedance will
be the plot of the inverse of the AC drain current. An example is shown in Figure 5-7. In this
example the output impedance is about 60 kΩ at low frequencies and then begins to decrease
around 10 GHz.

44
Figure 5-6: Current mirror simulation results

Figure 5-7: Current mirror output impedance

45
Prelab
The prelab exercise is due at the beginning of the lab period.
1) Make a table which lists the three current mirror topologies described in this lab. Rate each
topology using good, medium, or bad for the following design considerations: Rout,
accuracy, complexity, and compliance voltage.
2) Design a simple 1:1 current mirror that has a compliance voltage of 100 mV to 150 mV. The
output current should be 100 μA. Determine W/L for each transistor and what the expected
output impedance should be.
3) Design a low-voltage cascode current mirror with a 1:2 input current to output current ratio.
The low frequency output impedance should be greater than 1 MΩ. Assume a 50 μA input
current.
Lab
1) Simple current mirror
A) Design in Cadence the simple current mirror from the prelab. If needed, modify the
design so that it meets the given specifications.
B) Generate the plots of Figure 5-6 and Figure 5-7 for this design. Determine the
compliance voltage, low frequency output impedance, and comment on the accuracy.
C) Layout the current mirror. Run post layout simulations. Include plots of both layout and
schematic simulations in your lab report.
2) Low-voltage cascode current mirror
A) Design in Cadence the low-voltage cascode current mirror from the prelab. If needed,
modify the design so that it meets the given specifications.
B) Generate the plots of Figure 5-6 and Figure 5-7 for this design. Determine the compliance
voltage, low frequency output impedance, and comment on the accuracy.
C) Layout the current mirror. Run post layout simulations. Include plots of both layout and
schematic simulations in your lab report.
3) Be sure to include in your reports the LVS results showing that the layout matches the
schematic.

46
Lab 6: Inverting Amplifiers

Objective
Design, simulate, and layout various inverting amplifiers.
Introduction
Inverting amplifiers are fundamental building blocks of electronic circuits. These
amplifiers are used in a variety of circuit applications such as the gain stage of operational
amplifiers and as the NOT gate in digital logic. Due to the utility of inverting amplifiers,
learning the process of analyzing and designing these basic building blocks is important to
successful circuit design.
Studying inverting amplifiers also gives us insight into basic circuit concepts such as
small-signal frequency response and feedback. In this lab, the small-signal model of a generic
inverting amplifier is analyzed while a generic design procedure is developed. Next, the lab
manual presents advantages and disadvantages of several circuit structures. Finally, the students
will design various inverting amplifiers by choosing a circuit structure and developing a design
procedure.
The basic inverting amplifier is shown in Figure 6-1. The input signal Vin will contain an
AC signal component as well as a DC component used to set the operating point:
vIN = VBIAS + vin
Transistor M1 is called the driver since the input signal controls the amplifier from this
point. An ideal load will have infinite impedance. In the basic inverting amplifier circuit of
Figure 6-1, the load is represented by an ideal current source.
The DC operating point of the circuit is determined by IBIAS and VBIAS. These currents
and voltages determine the transistor’s small-signal parameters and establish the quiescent output
voltage.

vdd

Ibias
Vin Vout Vout
Vin M1

vss
Figure 6-1: Basic inverting amplifier

47
 The small-signal model for an inverting amplifier is given in Figure 6-2. The circuit
consists of two connected nodes which will result in two poles and one zero. The resistance RA
represents the voltage source’s resistance RS and any resistance used to establish the DC biasing.
The resistance RB includes the load resistance and the small-signal output resistance of the
driving transistor. The capacitance CA includes source capacitance and the small-signal input
capacitance of the transistor. Similarly, CB represents the load capacitance and the small-signal
output capacitance of the transistor. Finally, CC consists of any external stray capacitance and
internal capacitance between the drain and gate of the driving transistor.
RA CC
Vin Vout
+
VA CA Gm VA RB CB
-

Figure 6-2: Generic inverting amplifier small-signal model

Using node voltage equations or mesh currents, the input-output transfer function for the
inverting amplifier can be obtained by with some work. The transfer function for the generic
amplifier of Figure 6-2 is given by:
CC  G m 
s  
R A  C C 
Hs   (1)
 
CA  CC C B  CC   CC2 s 2   CA  CC  C B  CC  G m CC s  1

 RB RA  R AR B
This formula is too complicated to gain any useful insight as to how various resistors and
capacitors affect the frequency response of the inverting amplifier. Various assumptions can be
made to simplify (1). If we make the assumptions CB >> CA and CC >> CA, then the transfer
function can be simplified to:
1  Gm 
 s  
R ACB  CC 
Hs   (2)
 
 
 1 1 Gm  1
s 
2
  s
 R BC B C BCC C B  R A R BC BC C
 RA 
 C B  CC 
This simplification is useful because CC is generally a large transistor used to set the
gain-bandwidth product, and the total load capacitance is generally larger than any parasitic input
capacitances.
Next, we can simplify (2) in two different meaningful ways. The first way assumes RA is
small while the second assumes RA is large. Using the first assumption that RA is small, we have

48
 1
RA << RB and RA << . With this simplifying assumption, the transfer function in (2)
Gm
becomes:
 Gm 
1
 s  
R ACB
 C C 
Hs   (3)
 
 
 1 s  1
s 
2
 C BCC  R A R BCBCC
 RA 
 CB  CC 
Also, if we assume the poles are far apart, that is p1 << p2, then we can use the following
simplification when factoring:
Ds   s  p1 s  p 2   s 2  p1  p 2 s  p1p 2  s 2  p 2 s  p1p 2
The above simplification assumes a dominant pole exists. The dominant pole is the pole
which is significantly closer to the origin than all the other poles. The non-dominant poles occur
at a much greater frequency than the dominant poles. Using this simplification, the denominator
in (3) can be factored as shown in (4). From (4) the poles can easily be determined.
 Gm 
1
 s  
R ACB
 C C 
Hs   (4)
 
 
 1  1
 s   s  
 CB  CC R B  R A
 C BC C


 C B  CC 
Now that the transfer function is in factored form, we can find the DC gain, poles, and
zero for the case when CA is small and RA is small:
A V 0  G m R B
1
p1 
CB  CC R B
1
p2 
C BCC
CA is small, R A is small
RA
CB  CC
Gm
z
CC

49
 1
Assuming RA is large, that is RA ≈ RB and RA >> . With this assumption, the
Gm
transfer function given by (2) can be factored using the procedure given above:
1  Gm 
s  
R ACB  CC 
Hs   (5)
 G m  1 
 s   s  
 CB  G m R A R BCC 
With this transfer function in factored form, we can find the DC gain, poles, and zero for
the case when CA is small and RA is large:
A V 0  G m R B
1 1
p1  
G m R BC C R A A V 0 CC R A
 Gm
p2  CA is small, R A is l arg e 
CB
Gm
z
CC
Notice that the dominant pole has been shifted towards the origin. This is an example of
Miller’s Effect.
Next the frequency response of the two transfer functions derived above will be
examined. For the case when RA is small, the poles are greatly separated. Usually this system
can be represented adequately by a first-order transfer function. The pole-zero diagram is shown
in Figure 6-3. Since this system is first-order stability problems are less likely; however, the
right-half plane zero will reduce phase margin. If stability becomes a problem, increase CB
relative to CC.

Figure 6-3: Pole-Zero diagram for small RA

For the case when RA is large, the system consists of a dominant pole, a non-dominant
pole, and a right-half plane zero. Due to these three phase margin reducing components, careful
circuit design is required to guarantee stability. The zero reduces phase margin and should be
placed as far to the right as possible, while the non-dominant pole should be placed as far to the
left as possible. Figure 6-4 illustrates the pole-zero diagram for this system.

50
 Figure 6-4: Pole-Zero diagram for large RA
Two other simplifications are shown below. The first simplification assumes CA>>CB,
CA>>CC, and RARB. This situation may occur when the inverter is used to amplify a signal
from a capacitive transducer.
A V 0  G m R B
1
p1 
R A  CA
1
p2  CA is l arg e, R A is l arg e 
R B C B  CC 
Gm
z
CC
The second set of equations assumes CB>>CC, CB>>CA, and RBRA. These equations are
useful if a wideband inverter is driving a capacitive load.
A V 0  G m R B
1
p1 
R B  CB
1
p2  CB is l arg e, R B is l arg e 
R A C A  CC 
Gm
z
CC

51
Design Description
This section of the lab will discuss in detail four inverting amplifier configurations. The
first inverter uses a current-mirror as the active load. The second is a basic inverter commonly
used in CMOS digital logic. The last two amplifiers employ diode connected transistors as
loads. The last to amplifiers employ diode connected transistors as loads. Each of these
amplifiers has characteristics which makes its use advantageous in certain applications.
Inverter with Current-Mirror Load

The inverter of Figure 6-5 employs an NMOS driver and a PMOS current-mirror as the
load. The current-mirror provides a large small-signal output resistance and constant biasing
current. The biasing current establishes the operating point for transistor M1, which in turn
determines its small-signal transconductance. This circuit can provide a high output resistance
and a large small-signal gain.
A disadvantage of this circuit is the need for a biasing current which requires additional
circuitry. However, since this circuit is biased by another circuit, this amplifier can be
programmed or tuned to operate at a specific operating point even during the presence of process
variations.

Figure 6-5: Inverting amplifier with current-mirror load

Design Procedure
This design procedure is only an example. To achieve the desired inverter performance another
procedure may need to be used.
1) Determine the Miller compensation capacitor Cm from the gain-bandwidth product (GBW)
specification. Remember GBW = AV0 · p1.
2) To guarantee stability be sure the phase margin is greater than 60º, make sure the non-
dominant pole p2 is at least three times greater than the GBW. Use this information along
with the load capacitance to determine gm1.
3) Determine IBIAS to provide the desired DC gain.
4) Using gm1 and IBIAS, determine the size for transistor M1.

52
5) Use a 1:1 current-mirror sized such that the transconductance is equal to that of the driver
transistor.
Digital CMOS Inverter

Figure 6-6 illustrates the basic CMOS inverter. This circuit is commonly used in digital
logic circuits. Since both transistors are driven by the input source, the voltage gain will be
higher with this circuit than the amplifier with the current-mirror load.
An advantage of this circuit is that it does not need external biasing circuitry. The
operating point of this circuit is determined by the ratio of the transistor sizes. Using large
transistors will cause Gm to be high. This allows higher frequency operation when driving large
capacitive loads.

Figure 6-6: Digital CMOS inverting amplifier

Figure 6-7 illustrates the effect of changing the ratio of the transistors. Typically, the
transition region will be half the supply voltage. In this case, the products of the
transconductance and transistor sizes for the NMOS and PMOS must be equal. If process
variations cause KP or KN to change, then the transition region will shift.
Figure 6-7 also shows the gain and linearity of the amplifier. The slope of the curve at
any point it the gain. The vertical section of the graph is a region of high gain. Since the slope
of the curve changes with signal amplitude, the amplifier exhibits high distortion. To obtain low
distortion operation, the input voltage must remain small.

Design Procedure
This design procedure is only an example. To achieve the desired performance another
procedure may need to be used.
1) First, notice the DC gain is determined by the power supply voltage for symmetrical
operation:
1 2 2
A V 0  G m R B  g m1  
 I BIAS  VGS  VT   VDD  VT 
2) Determine Miller Compensation capacitor Cm from gain-bandwidth product (GBW)
specification or dominant pole specification. Remember GBW = AV0 p1.

53
 Vout W 
KPP  
 L P
1
VDD W 
KPN  
W   L N
KPP  
 L P  1
W 
KPN   W 
 L N KPP  
0  L P  1
W 
KPN  
 L N

VSS Vin
- V 0 V

Figure 6-7: Transition regions for various transistor size ratios

3) To guarantee stability be sure the phase margin is greater than 60. This requires the non-
dominant pole p2 to be at least three times higher in frequency than the gain-bandwidth
product (p2 > 3 GBW). Use this information to determine gm1.
4) Remember, for symmetrical operation the transistors must be in the ratio:
W
KN N
L 1
W
KP P
L
5) Using the value for gm1 and the above equation, determine the size for transistors Ml and M2.
Remember, the current through both transistors is the same.
W g m1, 2
K N,P N, P 
L VDD  VT 
PMOS Only Inverter with Self-Biased Load

Figure 6-8 shows a PMOS inverter. This inverter does not require a CMOS process. Due
to the diode connected load, the inverter has a low output resistance which in turn gives it a low
gain. This inverter however is very linear.
The derivation of the large-signal transfer function is easy. Assume both transistors are
the same size and perfectly matched. Since the drain current is the same for both transistors:
1 W
I  I D1  I D 2  KP VGS1  VT 2
2 L
and M2 is diode connected, Vout is given by:

54
 Vout  VSS  VGS2
2I
Vout  VSS   VT
W
KP
L
The gate to source voltage of M1 is equal to the input voltage and the equation becomes:
1 W
2 KP VDD  Vin  VT 2
Vout  VSS  2 L
W
KP
L
Vout  VSS  VDD  Vin
Vout  Vin

Figure 6-8: PMOS only inverter with self-biased load

Design Procedure
This design procedure is only an example. To achieve the desired inverter performance
another procedure may need to be used.
1) First, notice the DC gain is determined by the sizes of the transistors. For a unity-gain buffer,
the gain is one.
g m1
A V0  G mR B 
gm2
2) Determine the Miller compensation capacitor Cm from the dominant pole location of the
GBW product specification.
3) To guarantee stability, be sure the phase margin is greater than 60º. This requires the non-
dominant pole p2 to be at least three times higher in frequency than the GBW product. Use
this information to determine gm1 and gm2.
4) Using the value for the transistor transconductance determine the size for transistors M1 and
M2. Remember, the current through both transistors is the same.

55
CMOS Inverter with Self-Biased Load

The inverter of Figure 6-9 is similar to the previous inverter except it requires a CMOS
process. Matching of transistors is also difficult. Use a design procedure similar to the previous
inverter.

Figure 6-9: CMOS inverter with self biased load

Summary of AC Characteristics

Table 6-1 lists the capacitors and resistors from Figure 6-2 and gives the parameter value
for each of the four configurations. This table does not include all possible parasitic capacitance
associated with the transistors. The table also does not include stray capacitance associated with
circuit layout. Depending on the application, the stray capacitance might be a significant
component of the frequency response.
Table 6-1: Relationship between the generic amplifier model and various inverter circuits
Current-Mirror Digital CMOS Self-Biased Self Biased
Load PMOS CMOS
RA RS RS RS RS
RB ro1||ro2||RL ro1||ro2||RL ro1||1/gm2||RL ro1||1/gm2||RL
CA Cgs1 Cgs1+ Cgs2 Cgs1 Cgs1
CB (Cbd1||Cbs1)+ (Cbd1||Cbs1)+ (Cbd1||Cbs1)+ (Cbd1||Cbs1)+
(Cbd2||Cbs2)+ (Cbd2||Cbs2)+ (Cbd2||Cbs2)+ (Cbd2||Cbs2)+
CL CL CL+ Cgs2 CL+ Cgs2
CC Cgd1+Cm Cgd1+Cgd2+Cm Cgd1+Cm Cgd1+Cm
Gm gm1 gm1+gm2 gm1 gm1

56
Prelab
The prelab exercises are due at the beginning of the lab period. No late work is accepted.
1) Create a table ranking the various amplifiers as good, medium, or poor in the following
categories: gain, input impedance, output impedance, and linearity. Include the expressions
for each design specification (except for linearity).
2) Derive the transfer function for the generic amplifier by applying Miller’s Theorem.
Compare this transfer function to the one derived in the lab manual. Comment on the utility
of Miller’s Theorem.
3) Design the following inverting amplifiers:
A) Current-mirror load inverter with the following specifications:
GBW = 1 MHz, PM = 60º, AV0 = 30 dB, VDD = -VSS = 0.9 V, RS = 100 kΩ, CL = 30 pF
B) Digital CMOS inverter with the following specifications:
GBW = 1 MHz, PM = 60º, AV0 = 30 dB, VDD = -VSS = 0.9 V, RS = 100 kΩ, CL = 30 pF
C) PMOS inverter with the following specifications
GBW = 1 MHz, PM = 60º, AV0 = 0 dB, VDD = -VSS = 0.9 V, RS = 100 kΩ, CL = 30 pF
D) Self-biased CMOS inverter with the following specifications
GBW = 1 MHz, PM = 60º, AV0 = 0 dB, VDD = -VSS = 0.9 V, RS = 100 kΩ, CL = 30 pF
Lab
1) Simulate the designs from the prelab indicated by the TA. Simulate and perform design
iterations until your circuit operates within specifications. These simulation results will be
included in the final lab report. After the circuit is operating properly, create a DC input-
output characteristic plot and comment on the linear region. Determine the input offset and
add a bias source to the circuit to insure Vout = Vin = 0. Create frequency response plots, and
determine the GBW, PM, p1, and AV0.
2) Layout your final design.
3) Repeat simulations from part 1 on the layout. Be sure parasitic capacitances from the layout
are included.

57
Lab 7: Differential Pairs

Objective
Design, simulate, and layout various differential pairs used in different types of
differential amplifiers such as operational transconductance amplifiers and operational
amplifiers.
Introduction
Differential pairs are the final set of basic circuit elements that will be discussed in this
lab course. These circuit elements are used as the input stages of operational amplifiers and
operational transconductance amplifiers, common-mode feedback circuits, and analog
multipliers. As with the other fundamental building blocks, a good under-standing of differential
pairs is required for successful analog circuit design.
A differential pair consists of two well-matched, source-coupled transistors as shown in
Figure 7-1. An input voltage between the two gate terminals produces an out-put current in the
drain terminals.

Figure 7-1: Basic differential pair

The most common application for a differential pair is the differential amplifier. Figure
7-2 shows the basic differential amplifier. It consists of a differential pair which is biased by the
tail current source Itail. Resistor Rtail models the output resistance of a real current source. Load
resistors RD1 and RD2 allow the amplifier to develop an output voltage. The output voltage can
be differential or single-ended. A differential output is developed between the two output
terminals, while the single-ended output is taken between one output and ground.
The task of the differential amplifier is to amplify the difference between its two input
signals. The signals can be decomposed into two components. The first component is called the
differential-mode voltage vDM and is given by:
vDM = v1 – v2
The second component is called the common-mode voltage vCM and is given by:
v1  v 2
v CM 
2

58
 Figure 7-2: Basic differential amplifier
Assuming M1 and M2 are in saturation, neglecting channel length modulation, and
assuming perfectly matched transistors, the large signal characteristics can be analyzed as
follows:
2I D1 2I D2
v DM  v G1  v G2  v GS1  v GS2  
β1 β2
I tail  I D1  I D2
where β  KP  W L  . Assuming that β  β1  β 2 and combining both equations, two equations
describing the drain currents are obtained.
1
I I  β  v 2DM β  v 4DM  2
I D1  tail  tail   
2 2  I tail 4  I 2tail 
1
I I  β  v 2DM β  v 4DM  2
I D1  tail  tail   
2 2  I tail 4  I 2tail 
These relationships are valid only for
2  I tail
v DM 
β
and for M1 and M2 in saturation. This means that for vDM greater than or equal to the above
expression, then only one of the transistors is conducting and the other is off.

59
 I
I tail

ID2 ID1

slope=-gm slope=gm

KP  W 
vDM  
2 2 I tail  L 

Figure 7-3: Normalized large signal transconductance characteristic of a MOS differential

amplifier
The desired behavior of the differential amplifier is to amplify the differential-mode
voltage and attenuate the common-mode voltage. The differential gain ADM of an amplifier with
a differential output is defined as:
v OD
A DM 
v DM
where vOD is the differential output voltage. For a single-ended differential amplifier, the gain is
defined as
v OS
A DM 
v DM
where vOS is the single-ended output voltage. For an amplifier with a differential output, the
common-mode gain is defined as:
v OD
A CM 
v CM
and for an amplifier with a single-ended output, the common-mode gain is defined as:
v OS
A CM 
v CM
For a symmetrical amplifier such as the fully-differential amplifier, that is an amplifier
with a differential output and a differential input, the common-mode voltage gain will be zero if
the differential pair is perfectly matched. Due to mismatches in the differential pair or in the
loads, a common-mode input voltage can cause a differential output voltage. A figure of merit
for differential amplifiers is the common-mode rejection ratio (CMRR). The CMRR is defined
as the ratio of the differential gain and common-mode gain:

60
 A 
CMRR  20  log10  DM 

 A CM 
The input common-mode voltage is limited in magnitude. The inputs must not force any
of the transistors out of saturation. The limitation on the common-mode voltage creates a
common-mode voltage range for the amplifier. When the common-mode voltage increases
above the upper limit, the transistors in the differential pair will leave the saturation region and
enter the linear region. If the common-mode voltage decreases below the lower limit, then the
transistors in the tail current source will be forced out of saturation. The common-mode voltage
range can be found by considering the saturation voltages for differential pair transistors and
current source transistors. Remember, for a transistor to be in saturation:
2I D
VDS(SAT)  VGS  VT 
W
KP 
L
The output voltage range is also limited. For a single-ended amplifier with symmetrical
power supplies, the magnitude of the output signal is limited to the supply rail:
VOS  VDD
However, for a fully-differential amplifier the output signal can be twice this amplitude.
Each output can swing to a supply rail, giving a differential output voltage that is twice as large
as either rail. As with all amplifiers, another limit on the output voltage swing is the allowable
distortion. An output signal swing which comes within 200 mV of the supply rails may have
10% THD; however, a signal which comes within 500 mV may have only 1% THD in the same
circuit. The output voltage range is dictated by the distortion requirement.
The input-output characteristic curves of the differential amplifier are shown in Figure
7-4. The region where the input is approximately zero volts is linear. The size of the linear
region is determined by the transistor sizes. Decreasing the transistor sizes will decrease the
transconductance and increase the size of the linear region.
The amplifier also has an input and output impedance. The differential input resistance
and the common-mode input resistance are large for MOSFET differential amplifiers. The
differential input resistance is the resistance between the two input terminals. The common-
mode input resistance is the resistance measured between the two interconnected inputs and
ground.
The output impedance can also be measured in two different ways. For fully differential
amplifiers, the differential output resistance is the resistance between the two output terminals.
For single-ended amplifiers, the common-mode output resistance is the resistance measured
between the output and ground.

61
 V0
+V0(max)

small W/L
linear region

Vin=Vi+-Vi-

large W/L

-V0(max)

Figure 7-4: Input-output characteristic curves for a differential amplifier

Another figure of merit for the differential amplifier is its power supply rejection ratio
(PSRR). This ratio indicates the effect of power supply variations or noise on the output voltage.
For full-differential amplifiers with perfect matching in the differential pair and load, the PSRR
is zero. PSRR is given by:
 A dm 
PSRR   20  log10  

 v o v DD 
 A dm 
PSRR   20  log10  

v v
 o SS 
The slew rate is a measure of how quickly the output of the differential amplifier can
change in response to an instantaneous rail-to-rail (large-signal) change in the input voltage.
Due to process variations, the differential pair will not be perfectly matched. As a result,
for equal input voltages, the drain currents will not be equal. Also, if the load is asymmetrical,
then a non-zero output voltage will exist. The voltage at the input which forces the output
voltage to zero is called the input offset voltage.
Design Description
This lab consists of the design of two single-ended differential amplifiers. Figure 7-5
illustrates the simple differential amplifier. This circuit consists of a differential pair biased by a
simple current mirror. The active load is a PMOS current mirror.
Differential Gain

The differential gain of this circuit is given by:

A DM  G m  R out  g m1,2  rds2 || rds6 

62
 Figure 7-5: Simple differential amplifier
Slew Rate

The biasing current and the amount of load capacitance determine the slew rate. The
slew rate is given by:
I tail
SR 
CL
GBW and Dominant Pole

Since the output node is a high-impedance node, the dominant pole is located at:
1
p1 
R out  C L
The gain-bandwidth product is then given by:
GBW  A DM  p1
Common-Mode Voltage Range

As mentioned previously, the common-mode voltage range is the range of input voltages
which keep the current-source and active load transistors in saturation. The common-mode
voltage range is determined by the sizes of the transistors. To increase the common-mode
voltage range, the sizes of the transistors must be increased. The common-mode voltage range is
given by:

63
 V V V

DS,sat4
  
DS, sat1,2
 
DS, sat5,6

2I tail I tail I tail

VSS    VTN  Vin(CM)  VDD   VTP  VTN
W W W
KN 3,4 K N 1,2 KP 5,6
L L L
Common Mode Gain

To design for common mode, we can no longer assume that there exists an AC signal
ground at the source of M1 and M2. This current source must be substituted by a resistor of value
equal to the output resistance of the current mirror. To help in the development of the design
equations, Figure 7-6 is used. From this figure, the common-mode voltage can be found by:
i d  g m v gs  g m v CM  v S 
v S  2i d ro4
 1 
v CM  i d   2ro4   2i d ro4
 gm 
Following a similar approach, the output voltage is given by
1
v out  i d
g m6
The common-mode gain is then given by:
1
v out g m6 1
A cm   
v CM 2ro4 2g m6 ro4
As can be seen from this equation, the CMRR can be improved by increasing the output
impedance of the tail current.
A dm
CMRR  20log10  20log10 g m1,2 rds2 || rds6 2g m6 ro4
A cm

64
 Figure 7-6: Differential amplifier used to determine CMRR

Cascode Differential Amplifier

The second differential amplifier is shown in Figure 7-7. This circuit utilizes low-voltage
cascode current mirrors as the current source and active load. Design equations for this structure
are the same as the previous structure except that the output impedance of the amplifier and
current source are now larger. This will increase differential-mode gain while decreasing
common-mode gain, thus a vastly improved CMRR. The main drawback of this circuit is a
reduced input common-mode range and output swing

65
 Figure 7-7: Cascode differential amplifier
Prelab
The prelab exercises are due at the beginning of the lab period. No late work is accepted.
1) Compare the two single-ended differential amplifiers discussed in this lab. Rate the
differential gain, common-mode gain, power supply voltage, CMRR, and common-mode
input range. Include the expressions for each design specification.
2) Design the simple differential amplifier in Figure 7-5 to obtain the following specifications:
Slew Rate 10 V/μs
Gain-Bandwidth Product 5 MHz
Common-Mode Voltage Range 0.5 V
Power Supply VDD = -VSS = 0.9 V
Load Capacitance 10 pF

3) Design the cascode differential amplifier in Figure 7-7 to obtain the following spec-
ifications:

66
 Slew Rate 10 V/μs
Gain-Bandwidth Product 5 MHz
CMRR > 60 dB
Power Supply VDD = -VSS = 0.9 V
Load Capacitance 10 pF

Lab
1) Simulate the design from the prelab indicated by the T.A.
Measure and plot:
 Common-mode range
 Differential-mode gain
 Common-mode gain
 CMRR
 GBW
 Dominant pole p1
 Slew rate

Use any analysis necessary to obtain the most accurate measurements. Include these results
in the lab report.
2) Layout the final design. Repeat above measurements. Be sure to include parasitic
capacitance in the layout extraction. Include these results in the lab report.

67
Lab 8: Operational Transconductance Amplifiers

Objectives
Design, simulate, and layout an operational transconductance amplifier.

Introduction
The operational transconductance amplifier (OTA) is a basic building block of electronic
systems. The function of a transconductor is to convert an input voltage into an output current.
The transconductance amplifier can be configured to amplify or integrate either voltages or
currents. The versatility of an OTA allows its use in many electronic systems such as filters,
analog-to-digital converters, and oscillators. An OTA is also used as the core amplifier for an
operational amplifier (discussed in Lab 9). The operational transconductance amplifier is an
essential element of many analog systems.
The symbol for a single-ended OTA is shown in Figure 8-1. The amplifier has two
voltage inputs and a single current output. Fully-differential versions are available and are
commonly used in integrated circuits.
The output current of an OTA is proportional to the difference between the input
voltages. The relationship between the input voltages and output current is given by:

I O  G m  Vi   Vi   .

Figure 8-1: OTA symbol

The input-output characteristic for an OTA is shown in Figure 8-2. Notice that this
characteristic is similar to the input-output characteristic for the differential amplifier. For a
given maximum output current, the width of the OTA’s linear region is inversely related to the
magnitude of the transconductance; the larger the linear region, the smaller the transconductance.
The input and output resistance must be large in an OTA. Infinite input impedance
allows maximum transfer of the source voltage to the input of the OTA. Maximum transfer of
output current to the load occurs when the output resistance is infinite.
The circuit diagram for a basic OTA is shown in Figure 8-3. Notice that this is the
differential amplifier from Lab 6.

68
 Figure 8-2: Input-output characteristic for an OTA

Figure 8-3: Differential amplifier used as an OTA

A quick analysis of this amplifier shows the transconductance is given by:
Gm = gm1,2
The input resistance is large due to the inputs being at the gate terminals of the MOS
differential pair. Notice that the output resistance is also large:
Rout = rds2 || rds6
The gain-bandwidth product is given approximately by:
g m1,2
GBW 
CL

69
 An improvement of the differential amplifier of Figure 8-3 is to use self-biased loads.
The circuit in Figure 8-4 is called a symmetric OTA or three current-mirror OTA. This circuit is
constructed from all the basic elements discussed in the previous labs. The input stage is a
differential pair (Lab 7). The sub-circuits composed of M1,3 and M2,4 are self-biased inverters
(Lab 6). Transistors M3,5, M4,6, M7,8, and M9,10 are simple current-mirrors (Lab 5).
VDD

M5 M3 M4 M6

A1 A2
Io

Rbias
CL
Vi- M1 M2 Vi+

Itail

M9 M10

M7 M8

VSS

Figure 8-4: Three current-mirror OTA

When designing the symmetrical OTA, transistors M1 = M2, M3 = M4, M5 = M6, and M7 =
M8. This reduces the number of designable parameters to four transistor sizes and the tail
current. An analysis of this amplifier shows the transconductance is given by:
G m  β  g m1,2

where
g m 5, 6

g m 3, 4
The input resistance is large due to the MOS input stage. The output resistance is given
by:
Rout = rds6 || rds8
The gain-bandwidth product is given approximately by:
g m1,2
GBW  β 
CL

70
 Analysis shows that the symmetric OTA has a larger transconductance, slew rate, and
GBW than the OTA of Figure 8-3. These specifications are made larger by increasing β.
Design Description
The design of an OTA begins with a consideration of the design specifications. The
typical design considerations for an OTA include transconductance, slew rate, output resistance,
GBW, noise, phase margin, power dissipation, and output loading. The transconductance of the
symmetric OTA was listed previously and is repeated here for convenience:
W
G m  β  g m1,2  β  I tail  K N  1,2
L
where
g m5,6
β
g m3,4
In the above equation, notice that the DC current in transistors M5,6 is β times larger than
the currents in transistors M3,4. The transconductance can be set by the tail current source,
current mirror ratio, or size of the input transistors. The transconductance is usually the most
important parameter, and it is fortunate that it can be determined by several parameters.
Automatic tuning circuits sometimes vary the bias current in order to adjust the transconductance
to the desired value.
The slew rate of the OTA is given by:
I tail
SR  β 
CL
Notice the slew rate is larger than the slew rate of the differential amplifier. The
increased slew rate comes with the disadvantage of an increase in current (power) consumption.
The current drawn from the power supply (not including bias current source) is given by:
1 1 1 1
I DD  I tail  I tail    I tail    I tail    1I tail
2 2 2 2
The output resistance was listed above and is repeated below as:
Rout = rds6 || rds8
The gain-bandwidth product is given by:
 1  Gm
GBW  A V0  p1  G m  R out   
 R out  C L  C L
Another design consideration is noise. The noise performance is improved when the
voltage gain of the first stage is large. The voltage gain of the first stage is given by:

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 W
1,2
1 KN L
A V1  g m1,2  
g m3,4 K P W 3,4
L
The phase margin is a measure of stability for the amplifier. In most cases, the load
capacitance is much larger than the capacitance at the other nodes. When this is the case, the
operational transconductance amplifier has a dominant pole at the output node and two non-
dominant poles at the other two nodes. Due to the symmetric behavior at the input stage, the
amplifier also has a right-half plane zero. For most symmetric OTA designs, the non-dominant
poles and zero are much larger than the gain-bandwidth product and degrade the phase margin
by less than 10º each. This gives a typical phase margin of greater than 60º. The transfer
function of the OTA is given by:
A V 0  123
s  z 
Hs   z
s  1 s  2 s  3 
where:

1
p1 - is the dominant pole, located at the output node: p1 
R out C L

p2 - is the non-dominant pole, located at nodes A1 and A2:

1 g
p2   m 3, 4
R A CA CA

1 g
p3 - is the non-dominant pole, located at node B: p 3   m7
R BC B C B

z - is the zero due to the pole-zero doublet formed by the symmetric input stage:
z = 2 p2

The phase margin is thus given by:

 GBW   GBW   GBW 

PM  1800  tan 1 A V 0   tan 1    tan 1    tan 1  
p
 2   2 p 2  p
 3 
 GBW   GBW   GBW 
 900  tan 1    tan 1    tan 1  
 p2   2p 2   p3 
The above design description shows that many performance figures are inversely related.
For example, increasing slew rate results in an increase in power dissipation.

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Prelab
The prelab exercises are due at the beginning of the lab period. No late work is accepted.
1) Design the three current mirror OTA of Figure 8-4 to obtain the following specifications:
Gm: 500 μA/V
Slew Rate: SR > 10 V/μs
CL: 20 pF
Power: PD < 1 mW (not including bias current source)
Power Supply: VDD = -VSS = 0.9 V
Lab
1) Simulate the design from the prelab. Measure the transconductance vs. frequency, slew rate,
power consumption, voltage gain vs. frequency, dominant pole frequency, phase margin, and
gain-bandwidth product. Use any analysis necessary to obtain the most accurate
measurements. These simulation results will be included in the final lab report.
2) Create three cell views for your OTA: symbol, schematic, and layout. Layout your final
design and use good layout techniques. In your lab report indicate which transistors should
be matched. Extract the layout and repeat simulations from part 1. Be sure to include
parasitic capacitances in the extraction.

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Lab 9: Two Stage Miller OTA

Objective
Design, simulate, layout, and test a two-stage operational amplifier.
Introduction
The operational amplifier (opamp), like the operational transconductance amplifier, is an
essential component of analog system design. Integrated circuit design, as well as board level
design, heavily uses operational amplifiers. This component is basically a high-gain voltage
amplifier. Opamps are used in many analog systems such as filters, regulators, and function
generators. This rudimentary device is also used to create buffers, logarithmic amplifiers, and
instrumentation amplifiers. The opamp can also function as a simple comparator. Knowledge of
operational amplifier function and design is important in analog design.
The symbol for an operational amplifier is shown in Figure 9-1. The basic device has
two inputs and a single output. A fully-differential version of the opamp is often used in high
performance integrated circuit designs.

Figure 9-1: Operational amplifier symbol

The operational amplifier functions as a voltage amplifier. The relationship between the
input and output voltage is given by:
Vo = AV0 · (Vi+ - Vi-)
The amplifier has a high voltage gain (AV0 > 1000 for CMOS opamps). Due to the high
gain, the linear region is very narrow. Figure 9-2 illustrates the typical input-output
characteristic for an operational amplifier used with and without feedback. The open-loop
(without feedback) plot shows the linear region is only a few millivolts wide. From Figure 9-2,
the open loop input-output characteristic is clearly nonlinear.

Figure 9-2: Input-output characteristic for an opamp

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 Due to the high gain and limited linear region, the opamp is commonly used in a negative
feedback loop. Figure 9-2 shows also the input-output characteristic when the amplifier is used
with feedback. Notice the closed-loop linear region consists of almost the entire input voltage
range. The application of feedback reduces the non-linearity, but also reduces the voltage gain.
The simplest operational amplifier is the differential amplifier studied in Lab 7. This
amplifier can be improved by adding a second stage. The second stage is an inverting amplifier
with a current-source load. The two-stage amplifier shown in Figure 9-3 is referred to as a
Miller OTA.

Figure 9-3: Miller OTA

The Miller OTA has a low frequency voltage gain of:
AV0 = Gm · (Rout || RL)
The transconductance is given by:
g m1, 2  g m8
Gm
g o2  g o4
The output resistance of the two-stage opamp is given by:
Rout = rds7 || rds8
Design Description
The two-stage amplifier can be modeled as a cascade arrangement of two amplifiers.
Figure 9-4 illustrates the sequence of amplifiers. The first stage is a differential amplifier. This
stage produces an amplified version of the difference in input signals. This stage determines the
CMRR, slew rate, and other performance specifications determined by the differential amplifier
described in Lab 7.

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 Figure 9-4: Three-stage operational amplifier model
The second stage is an inverting amplifier. The purpose of this stage is to provide a large
voltage gain. The gain stage and the input stage create two poles which affect the stability of the
system. Usually some form of compensation is required to assure the amplifier is unity-gain
stable. Additional gain stages can be employed to increase the gain, but this increases the
stability problems and requires complex compensation techniques. Refer to Lab 6 for details on
the inverting amplifier performance specifications.
The frequency response of an operational amplifier will be analyzed with help from a
macromodel of the structure. Figure 9-5 shows a macromodel of the opamp. The capacitor Cin
models the input capacitance of the opamp, which is due mostly from gate-to-source capacitance.
The subcircuit consisting of GmA, RA, and CA model the gain and frequency response of the input
stage. The capacitance CA includes the input capacitance of the second stage and the output
capacitance of the first stage. The components GmB, RB, and CB model the second stage. The
load capacitor and resistor are also included in RB and CB.

Figure 9-5: Operational amplifier macromodel

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 The transfer function of the macromodel is given by:
GmAGmB
AVo  1  2
H s  
C AC B

s  1 s   2   1  1 
 s   s  
 R AC A  RB C B 
This transfer function assumes the source resistance is zero ohms. Notice the two poles
are approximately equal. The capacitors CA and CB are dominated by gate-to-source capacitance,
and RA and RB are the parallel connected small-signal drain-to-source resistance. The pole-zero
plot of this transfer function is illustrated in Figure 9-6.

p2 p1

Figure 9-6: Pole-zero diagram for uncompensated opamp

Due to the two poles being located close together, the system is unlikely to be unity-gain
stable due to the large DC gain of an operational amplifier. Clearly, some form of compensation
is required. The modified macromodel shown in Figure 9-7 uses capacitor CC to compensate the
frequency response of the opamp by splitting the distance between the two poles.

Figure 9-7: Operational amplifier macromodel with compensation capacitor CC

Assuming RA is large, that is:
1
R A  R B and R A 
G mB
and CA is small:
C B  C A and C C  C A
and using the results obtained from the inverting amplifier lab, the transfer function for the
operational amplifier with the compensation capacitor is:

77
 A V 0  1 2 G mA  G mB 
s  z  s  
z C B  C C 
H C (s)  
s  1 s   2   1  G mB 
 s   s  
 G mB R A R B C C  CB 
These simplifying assumptions hold because capacitance CB will include the capacitance
of the load, and the compensation capacitance CC can be chosen to be the size of the load
capacitor. Also, for the two-stage OTA, capacitance CB will include the load capacitance CL.
With the transfer function in factored form, we can find the open-loop DC gain, poles,
and zero of the compensated opamp are given by:
AV 0  GmA GmB R A RB
1 1
1  
GmB RB CC R A AV 2 CC R A
 GmB
2 
CB
GmB
z
CC
GmA
GBW 
CC
Notice the addition of the compensation capacitor CC caused the poles to separate. One
pole moved closer to the origin by a factor of AV2 = GmB · RB, while the other pole moved away
from the origin by a factor of AV2. This compensation technique is called “pole splitting”. The
pole-zero plot of this transfer function is illustrated in Figure 9-8. Also, notice the creation of a
zero as a result of the transition path created by the capacitor.

Figure 9-8: Pole-zero plot for a compensated opamp

Using the compensated opamp in a feedback loop produces the following transfer
function:

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 H C s 
A C s  
1  H C s   
A 0 s  z 

s  1  s   2   A 0  s  z 
 G 
A 0  s  mB 
 CC 

 1 G G   1 G G 
s 2    mB  mA   s    mA mB  
 G mB R A R B C C C B CB   R ACBR BCC CBCC 
where
G mA
A0 
CB
The closed-loop transfer function using the compensated amplifier can be approximated
by:
 G mB 
G mA
 s  
CB
 C C 
A C s  
G G  G G 
s 2   mB  mA   s   mA mB  
 CB CB   CBCC 
The effect of the above simplification on the system is to assume the dominant pole is at
the origin. Notice that when the system is in open-loop (β = 0), the transfer function reduces to:
G mA  G mB 
 s  
CB  CC 
A C s  
 G 
s  s  mB 
 CB 
The factor β varies the position of the dominant pole from the origin to the neighborhood
of the non-dominant pole. Figure 9-9 illustrates the effect of feedback on the frequency
response.
H (s)
0

  0.5

 1

Figure 9-9: Closed-loop frequency response

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 To assure the feedback system is unity-gain stable (β = 1), the phase margin must be
examined. The phase margin is the amount of phase before phase inversion (180º) at the unity
gain frequency. The expression for the phase margin is given by:
     
PM  180 0  tan 1  0dB   tan 1  0 dB   tan 1  0 dB 
 p1   p2   z 
 GBW   GBW   GBW 
 180 0  tan 1    tan 1    tan 1  
 p1   p2   z 
 GBW   GBW 
 180 0  tan 1 A V 0   tan 1    tan 1  
 p2   z 
 GBW   GBW 
 90 0  tan 1    tan 1  
 p2   z 
The phase margin is improved by moving the non-dominant pole and zero to higher
frequencies away from the unity-gain frequency. The phase margin can also be improved by
using compensation techniques which place the zero in the left-half plane.
The slew rate is determined by the compensation capacitance and the tail current:
I tail
SR 
CC
The performance characteristics of the two-stage amplifier are summarized below:
A V0  g m1,2 g m8 rds2 || rds4  rds7 || rds8 || R L 
1
ρ1 
g m8 rds7 || rds8 || R L C C rds2 || rds4 
 g m8
ρ2 
CL
g m8
z
CC
g m1,2
GBW 
CC
I tail
SR 
CC
 GBW   GBW 
PM  90 0  tan 1    tan 1  
 p2   z 
Monte Carlo Analysis
Monte Carlo analysis provides an accurate and powerful method for parametric yield
estimation. The principle of Monte Carlo analysis can be defined as the generation of circuit

80
figure-of-merit distributions as a function of statistically varying device model parameters that
accurately reflect manufacturing process variations.
With Monte Carlo analysis, you can generate and save statistical information about a
circuit’s temperature and geometry-dependent performance characteristics. The mathematics
supporting this Monte Carlo method proves that the probability distribution of the simulated
results will be statistically the same as the actual measurements of a real circuit that has been
fabricated.
These are the steps involved in Monte Carlo simulation using Analog Artist:
1) Assign statistical parameters to devices in the model file.
2) Setup the simulation environment and run a normal analog simulation.
3) Open Monte Carlo window
4) Define the expressions for Monte Carlo analysis using the calculator.
5) Add expressions to the Monte Carlo window.
6) Define the Monte Carlo simulation parameters.
7) Start the analysis.
8) Use the statistics functions to display and analyze the results.
There are two basic statistical distribution functions that you can apply to device
parameters:
 Uniform
 Gaussian
The uniform distribution is defined with a mean value and a tolerance that defines the
minimum and maximum values. Statistically, all values between the minimum and maximum
values are equally likely to occur. Figure 9-10a shows a plot of a uniform distribution.
The Gaussian distribution is defined with a mean and a standard deviation. Statistically,
values about the mean are more likely to occur than values within the tails. Almost all values
fall within 3 standard deviations of the mean. Figure 9-10b shows a plot of a Gaussian
distribution.

 3  2     2 3

(a) (b)
Figure 9-10: a) Uniform distribution
b) Gaussian distribution
The most common analysis modes to perform are:

81
  Random variations
 Random variations with mismatch
With random variations, the parameters track exactly. All devices that share the same
model file share the same model statement in the netlist. With random variations with mismatch,
the system creates a separate model statement for each device.

Prelab
The prelab exercises are due at the beginning of the lab period. No late work is accepted.
1) Design the operational amplifier of Figure 9-3 to obtain the following specifications:
AV0 > 50 dB
CMRR > 60 dB
GBW > 2 MHz
PM > 45º
Output Swing >1V
CL 30 pF
PD < 500 µW

Lab
1) Simulate the design from the prelab. Adjust transistor sizes until all specifications are met.
Provide plots of frequency response, CMRR, PSRR+, PSRR-, and transient response. Include
the slew rate, phase margin, gain-bandwidth product, and power dissipation in your report.
2) Layout your final design using good layout techniques. Include the “net-lists match” page in
your report. Include the plots and data from part 1. Be sure to include parasitic capacitances
in your extraction.
3) Run a Monte Carlo simulation on the opamp design. Be sure to run this simulation with
process variations and mismatch. Generate a histogram of the following parameters:
 GBW
 p1
 PM
 AV0
Comment on the impact of process variations and mismatch on each parameter.

82