ADVANCED VLSI DESIGN

III SEMESTER, 2024-25

BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE PILANI,

PILANI CAMPUS

Digital Phase-Locked Loop with Jitter Bounded

Submitted to: Submitted by :

Dr. Anu Gupta Mayank Latke (2023H1230171P)
Electrical and electronics Kunal Kishor (2023H1230164P)
Department , BITS Pilani
Table of Contents

Report Description ........................................................................................................................................ 1

Table of Contents ............................................................................................................................ 2
Table of figures ................................................................................................................................ 3
Introduction ..................................................................................................................................... 4
Design Description........................................................................................................................... 5
Phase frequency detector (PFD) .................................................................................................... 6
Digital controlled oscillator (DCO) ................................................................................................ 9
Frequency divider ......................................................................................................................... 11
Up/Down counter .......................................................................................................................... 12
Integration and simulation results ............................................................................................... 14
Working ...................................................................................................................................................... 14
PLL Schematic............................................................................................................................................ 15
PLL Simulated Waveform .......................................................................................................................... 15
Frequency plot ............................................................................................................................................ 16
Jitter Calculation ......................................................................................................................................... 17
Output waveform ........................................................................................................................................ 17
Eye diagram ................................................................................................................................................ 18
Conclusions & Summery............................................................................................................... 19
Innovation & Challenges .............................................................................................................. 19
References ...................................................................................................................................... 20

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 Table of figures
Figure 1 PLL Schematic ..................................................................................................................... 5
Figure 2 illustrated modified section .................................................................................................. 5
Figure 3 switching states .................................................................................................................... 6
Figure 4 PFD Schematic ..................................................................................................................... 6
Figure 5 PFD implemented Schematic .............................................................................................. 7
Figure 6 simulated waveform ............................................................................................................. 7
Figure 7 reference clock is slower ...................................................................................................... 8
Figure 8 digitally controllled delay element ....................................................................................... 9
Figure 9 Digitally Controlled Oscillator ........................................................................................... 10
Figure 10 Simulation Waveform of DCO ........................................................................................ 10
Figure 11 frequency divider ............................................................................................................. 11
Figure 12 simulated waveform ......................................................................................................... 11
Figure 13 up down counter using JK flipflop ................................................................................... 12
Figure 14 UP/ Down counter schematic ........................................................................................... 12
Figure 15magnified view of implemented counter........................................................................... 13
Figure 16 Up Down Counter simulation waveform ......................................................................... 13
Figure 17 PLL implemented Schematic ........................................................................................... 15
Figure 18 Fin = 10MHz, Divider = 64 bits and Fout = 1. 54 GHz ................................................... 15
Figure 19 output frequency simulation result ................................................................................... 16
Figure 20 Jitter waveform................................................................................................................. 17
Figure 21 Output Waveform............................................................................................................. 17
Figure 22 eye diagram , Bit Period =302 ps ..................................................................................... 18
Figure 23 Eye diagram of the PLL drawn for 1.53GHz frequency. ................................................. 18

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Introduction
Crystal oscillators generate accurate, low-jitter clocks with a frequency range from 10’s of
Megahertz to approximately 200MHz. To generate a higher frequency required by digital circuits,
a phase-locked loop (PLL) structure is typi cally used. A PLL takes an external low-frequency
reference crystal frequency signal and multiplies its frequency by a rational number N. Phase
Locked Loops find application in nearly every communication system, serving various purposes
such as recovering the clock from digital data signals, performing frequency and phase modulation
and demodulation, reclaiming the carrier from satellite transmission signals, and operating as a
frequency synthesizer. Typically implemented using analog components, known as analog PLLs
(APLL), these systems have been widely utilized for clock generation and frequency synthesis,
offering commendable performance across a broad frequency range. However, they face challenges
such as high power consumption, large area requirements, scalability issues, and elevated noise
levels arising from matching and process variations in the layout.

The DPLL design involves using a phase-frequency detector instead of a phase detector, a Digitally
Controlled Oscillator (DCO) instead of a Voltage-Controlled Oscillator (VCO), and a control circuit
emulating the functionality of a loop filter alongside a fixed frequency detector. This design is
particularly suitable for System- on-Chip (SoC) applications and can be automatically
implemented with standard cell libraries.

A PLL is a complex, nonlinear feedback circuit, and its basic operation is understood below.
The voltage-controlled oscillator (VCO) takes an analog control input and generates a clock
signal of the desired frequency. In general, there is a non-linear relationship between the
control voltage (vcont) and the output frequency. To synthesize a system clock of a
particular frequency, it necessary to set the control voltage to the appropriate value. This is
function of the rest of the blocks (i.e.,feedback loop) in the PLL. The feedback loop is
critical to tracking process and environmental variations. The feedback also allows
frequency multiplication.
The advantages of ADPLL, irrespective of technology differences, include low power
consumption, a compact footprint, and scalability across different technology nodes. However,
considerations such as frequency range, jitter, and lock time are disadvantages that must be

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acknowledged, albeit mitigated by the conversion from VCO to DCO. While analog PLLs
demonstrate high performance characteristics, such as low jitter and a broad frequency range, their
drawbacks, namely high power consumption and large area requirements, have fueled the growing
interest in replacing them with the more agile and adaptable ADPLLs over the last decade. The
switch to ADPLLs is primarily driven by the desire for fast time-to-market and reduced design
effort when migrating between different technology nodes. ADPLLs achieve this transition by
replacing analog blocks with their digital counterparts, such as replacing the RC LPF with a digital
controller and the VCO with a Digitally Controlled Oscillator (DCO).

Design Description
Digital PLLs are a type of PLL used to synchronize digital signals. While DPLLs input and outputs
are typically all digital, they do have internal functions which are dependent on analog signals.
There are three basic components of a DPLL:
● Phase Detector
● Loop Filter
● Voltage Controlled Oscillator (VCO)

Figure 1 PLL Schematic

DPLLs are designed by replacing the analog blocks in the AAPLL by their digital counterpart. RC
LPF is replaced by a digital controller, and the VCO is replaced by a Digitally Controlled Oscillator
(DCO).

Figure 2 illustrated modified section

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 Phase frequency detector (PFD)

The phase-frequency detector (PFD) is the most commonly used form of phase detector, and it solves
several of the shortcomings of the detectors dis cussed above. As the name implies, the output of the
PFD is dependent both on the phase and frequency difference of the applied signals. Accordingly, it
cannot lock to an incorrect multiple of the frequency. The PFD takes two clock inputs and produces
two outputs, UP and DOWN as shown in Figure.

Figure 3 switching states

Figure 4 PFD Schematic

In the Phase-Frequency Detector (PFD), two D-Flops are employed. Similar to regular D-Flops,
each of these units features a clock input, a data input, an inverted clear input, and two opposite
outputs, Q and Q bar. The 2-input NAND gate receives inputs from the two 'Q' outputs of the D-
flops and provides feedback to the inverted clear input of the D-flops. This configuration ensures
the effective operation of the PFD in the context of phase detection. The PFD is a state machine
with 3 states. Assume that both UP and DN output are Initially low. When input A leads B, the
UP output is asserted on the rising edge of input A. The UP signal remain in this state until a low-
to-high transition occurs on input B. At That time, the DN output is asserted, causing both flip-
flop store set through the asynchronous reset signal. Notice that a short pulse proportional to the
phase error is generated on the DN signal, and that there is a Small pulse on the DN output, whose
duration is equal to the delay through the AND gate and register reset delay. The pulse width of
the UP pulse is equal to the phase error between the two signal.

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 Figure 5 PFD implemented Schematic

Simulation waveform

Figure 6 simulated waveform

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Figure 7 reference clock is slower

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 Digital controlled oscillator (DCO)
The Digital Controlled Oscillator (DCO) serves as the signal generator in the PLL, distinguishing
itself from standard analog oscillators by digitally adjusting its frequency for exact tuning. The
Phase-Frequency Detector's (PFD) error signal is used to modify its output frequency. By
guaranteeing that the DCO generates an output signal with a frequency that is precisely calibrated
based on feedback from the PFD, this digital control mechanism improves the PLL's flexibility and
accuracy in maintaining synchronization. (Note: DCDE is the delay element utilized in this image;
DCO_9, which contains the control inv element, was used for simulation purposes.)

Figure 8 digitally controllled delay element

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 Figure 9 Digitally Controlled Oscillator

Simulation waveform

Figure 10 Simulation Waveform of DCO

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Frequency divider
In a PLL, the Frequency Divider is crucial for reducing the DCO's output signal frequency. This
lower frequency is compared with the reference signal in the PFD, enabling the PLL to lock onto
a wide range of input frequencies. Understanding the role of the Frequency Divider is essential for
designing PLL-based systems with precise frequency control and synchronization across varying
input signals, ensuring stable and accurate performance in different conditions.

Figure 11 frequency divider

Simulation waveform

Figure 12 simulated waveform

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Up/Down counter

The above figures show design of up/down counter designed using J-K- Flip Flops. It consists of
J-K FlipFlops, AND gates and OR gates interconnected in a manner to get the functionality of an
up/down counter. Up and Down signals are generated by the PFD based on whether feedback
signal or the ref signal is leading or lagging. Q3Q2Q1Q0 is the 4-bit output from the counter which
is then used to determine the frequency of the DCO.
When the down signal is high then the bottom AND gates become enabled the counter value
decrements and when then Up value is high then the top AND gates become enabled the counter
value increments. The simulation results of up/down counter are displayed below.

Figure 13 up down counter using JK flipflop

Figure 14 UP/ Down counter schematic

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 Figure 15magnified view of implemented counter

Simulation waveform

Figure 16 Up Down Counter simulation waveform

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 Integration and simulation results
The Phase-Frequency Detector (PFD) receives two inputs: the reference frequency set at 10MHz
from the off-chip crystal oscillator and another from the frequency divider, configured with N =
64 to achieve a PLL output frequency of 1.53GHz. When the reference signal frequency surpasses
the divider output, the PFD produces an "Up" pulse; otherwise, it generates a "Down" pulse. These
UP/DOWN pulses dictate the counting direction of a 4-bit counter, serving as input to the Digital
Controlled Oscillator (DCO), which adjusts its frequency accordingly. The DCO's output is fed
back into the divider, divided by N, and looped back to the PFD. This iterative process continues
until the PLL achieves the desired phase lock with the required frequency.

Working
➢ The freq Divider is set to a fixed value of 64 to achieve a range of 10 MHz to 1.53GHz
inprogrammable stage DCO enabled DPLL.
➢ Output signal from the divider is given to the PFD block along with the reference
signal (10MHz) for comparison.
➢ The output of the PFD would be an UP if reference signal have higher frequency than
thedivider output and DOWN signal if reference signal have lower frequency than the
divideroutput.
➢ Based on the UP/DOWN pulses the 4 bit counter will count 1 step upwards or
downwardswhich will feed as input to the DCO.
➢ The DCO will result in the respective frequency based on the 4 bit input provided by
the counter.
➢ The frequency from the DCO goes as input to the divider block in feedback and would
bedivided by N whose output is given as input to PFD.
➢ The cycle repeats till the desired frequency is achieved and the Phase is locked.

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PLL Schematic

Figure 17 PLL implemented Schematic

PLL Simulated Waveform

Figure 18 Fin = 10MHz, Divider = 64 bits and Fout = 1. 54 GHz

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 Frequency plot

Figure 19 output frequency simulation result

Locked frequency @ 1.53 GHz

Locked frequency @ 1.62 GH

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Jitter Calculation

Figure 20 Jitter waveform

Jitter = 32 ps

Output waveform

Figure 21 Output Waveform

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Eye diagram

Figure 22 eye diagram , Bit Period =302 ps

Figure 23 Eye diagram of the PLL drawn for 1.53GHz frequency.

Time Uncertainty = 400 ps

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Conclusions & Summery
The designs were simulated in 0.18μm CMOS technology. A review of the measured
performance of the design is shown in Table 1.

Table 1. Simulated Result Table

Specification Simulated Results

DCO Frequency Range 327 MHz – 595 MHz
Locked frequency 1.53 GHz
Jitter 32 ps
Technology 180nm
Process Parameter tt_18
Frequency divider 64
Timing uncertainty 400ps

Innovation & Challenges

1. The reference paper's current DCO design was a three-bit control word DCO. Increasing
the control word size to 6 or 7 bits long allows for fine customization. However, this led to
increased capacitance because the width of the control transistor doubles with each bit
increase in the control word. Additionally, a 6/7 bit counter is needed for a 6/7 bit DCO,
increasing the power budget. Therefore, taking into account all the compromises, the
design was created at a 4 bit control word.

2. Challenges faced while integrating different blocks of digital PLL.

3. For designing D ff master slave configuration is adopted with TG and inverter circuits .

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