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CPE344 - Digital System Design - Assignment-3

The assignment for Digital System Design at COMSATS University requires students to convert C-like code into a high-level state machine and subsequently design a controller and datapath. It involves optimizing combinational logic, redesigning for concurrency, and analyzing the performance of various designs based on logic size and delay. Students must also discuss trade-offs in their design choices and compute the total computation time based on given delays for different components.

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2 views1 page

CPE344 - Digital System Design - Assignment-3

The assignment for Digital System Design at COMSATS University requires students to convert C-like code into a high-level state machine and subsequently design a controller and datapath. It involves optimizing combinational logic, redesigning for concurrency, and analyzing the performance of various designs based on logic size and delay. Students must also discuss trade-offs in their design choices and compute the total computation time based on given delays for different components.

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mahmadali99.09
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COMSATS University Islamabad, Lahore Campus

Department of Electrical & Computer Engineering


Assignment No. 3
Course Title: Digital System Design Course Code: CPE/EEE 344 Credit Hours 4(3,1)

Ms. Wajeeha Khan


Course Instructor: Programme Name:

Semester: 7th Batch: Date: 6/05/2025


Last Date: 12/05/2025 Maximum Marks: 20

Question # 1: (PLO3-CLO2-C5)

(a) Convert the following C-like code to a high-level state machine. Ignore overflow.

Inputs: byte a[256J, byte b[256J, byte cy


Output: byte sumy, byte c [256]
MULT OR ADD:
int i =O;
int sumy

while ( i < 256) {


c[i] = a[i] * (b[i] + cy);
sumy = sumy + c[i];
}
i++;
}
(b) Use the RTL design process to convert the HLSM to a controller and a datapath. Design the
datapath to structure but design the controller to the point of an FSM only.

(c) Optimize the combinational logic of controller by using state encoding technique. Compare
the logic size (number of gate inputs) and the delay (number of gate delays) of a minimum binary
encoding, with your selected state encoding technique.

(d) Redesign your datapath to allow for concurrency in which two comparisons, two additions,
and two multiplications can be performed concurrently.

(e) Redesign the datapath and controller designed in (b) by allowing up to nine concurrent
additions and inserting pipeline registers, updating the controller as necessary. Assuming a
comparator has a delay of 4 ns, an adder has a delay of 2 ns, and a multiplier has a delay of 20 ns,
how long will the circuit take to finish its computation?

(f) Compare the logic size (number of gate inputs) and the delay (number of gate delays) of your
designs. You are free to choose any optimization technique and any type of datapath components.
Discuss the tradeoffs of your designs.

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