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Binary addition by hand

• You can add two binary numbers one column at a time starting from the
right, just as you add two decimal numbers.
• But remember that it’s binary. For example, 1 + 1 = 10 and you have to
carry!

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 Half Adder
• We start with a half adder, which adds two bits and produces a
two-bit result: a sum (the right bit) and a carry out (the left
bit).
• Here are truth tables, equations, circuit and block symbol.

X Y C S
0 0 0 0 0 + 0 =0
0 1 0 1 0 + 1 =1
1 0 0 1 1 + 0 =1
1 1 1 0 1 + 1 = 10

C = XY
S = X’ Y + X Y’
= X  Y

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 Full Adder

A full adder circuit takes three bits of input, and

produces a two-bit output consisting of a sum and a
carry out.

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 Full adder equations
• Using Boolean algebra, we get the equations shown here.
– XOR operations simplify the equations a bit.
– We used algebra because you can’t easily derive XORs from K-maps.

S = m(1,2,4,7)
= X’ Y’ Cin + X’ Y Cin’ + X Y’ Cin’ + X Y Cin
= X’ (Y’ Cin + Y Cin’) + X (Y’ Cin’ + Y Cin)
= X’ (Y  Cin) + X (Y  Cin)’
= X  Y  Cin

Cout = m(3,5,6,7)
= X’ Y Cin + X Y’ Cin + X Y Cin’ + X Y Cin
= (X’ Y + X Y’) Cin + XY(Cin’ + Cin)
= (X  Y) Cin + XY
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 Full adder circuit
• The Full Adder can be designed using two half adders ( 2 x 2 Gates) and
an Or Gate. This brings down the implementation size to just 5 Gates!

S = X  Y  Cin
Cout = (X  Y) Cin + XY

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Implementation of Full adder using Half adders

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 A 4-bit adder

• Four full adders together make a 4-bit adder.

• There are nine total inputs:

– Two 4-bit numbers, A3 A2 A1 A0 and B3 B2 B1 B0

– An initial carry in, CI

• The five outputs are:

– A 4-bit sum, S3 S2 S1 S0

– A carry out, CO

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 An example of 4-bit addition
• Let’s try our initial example: A=1011 (eleven), B=1110 (fourteen).

1 1 1 0 1 1 0 1

0
1 1 0

1 1 0 0 1

1. Fill in all the inputs, including CI=0

2. The circuit produces C1 and S0 (1 + 0 + 0 = 01)
3. Use C1 to find C2 and S1 (1 + 1 + 0 = 10)
4. Use C2 to compute C3 and S2 (0 + 1 + 1 = 10)
5. Use C3 to compute CO and S3 (1 + 1 + 1 = 11)
Woohoo! The final answer is 11001 (twenty-five).

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 Hierarchical adder design
• Here is an 8-bit adder, for example.

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 Gate delays

• Every gate takes some small fraction of a second between the

time inputs are presented and the time the correct answer
appears on the outputs. This little fraction of a second is called
a gate delay.

• We can use a timing diagram to show gate delays graphically.

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 Delays in the ripple carry adder

• The diagram below shows a 4-bit adder completely drawn out.

• This is called a ripple carry adder, because the inputs A0, B0 and CI
“ripple” leftwards until CO and S3 are produced.

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 Delays in the ripple carry adder

• Ripple carry adders are slow!

– Our example addition with 4-bit inputs required 5 “steps.”

– There is a very long path from A0, B0 and CI to CO and S3.

– For an n-bit ripple carry adder, the longest path has 2n+1 gates.

– Imagine a 64-bit adder. The longest path would have 129 gates!

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 The carry ripple slows down the addition circuit,
especially as the number of bits in the adder increases.

Assume each gate in the full adder has a switching delay of 10 ns.

Thus sum output is valid after 3 gate delays (inverter, NAND,NAND) or 30 ns.

The carryout is valid after 2 gate delays (NAND,NAND) or 20 ns.

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 A faster way to compute carry outs

• Instead of waiting for the carry out from all the previous stages, we
could compute it directly with a two-level circuit, thus minimizing the
delay.

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 A faster way to compute carry outs
• First we define two functions.
– The “generate” function 𝒈𝒊 produces 1 when there must be a carry
out from position i (i.e., when Ai and Bi are both 1).
𝒈𝒊 = 𝑨𝒊 𝑩𝒊

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 A faster way to compute carry outs

– The “propagate” function 𝒑𝒊 is true when, if there is an incoming

carry, it is propagated (i.e, when Ai=1 or Bi=1, but not both).

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A faster way to compute carry outs

𝒈𝒊 = 𝑨𝒊 𝑩𝒊 ,
Then we can rewrite the carry out function:

𝑪𝒊+𝟏 = 𝒈𝒊 + 𝒑𝒊 𝑪𝒊

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 Algebraic carry out
c1 = g0 + p0c0

c2 = g1 + p1c1
= g1 + p1(g0 + p0c0)
= g1 + p1g0 + p1p0c0

c3 = g2 + p2c2
= g2 + p2(g1 + p1g0 + p1p0c0)
= g2 + p2g1 + p2p1g0 + p2p1p0c0

c4 = g3 + p3c3
= g3 + p3(g2 + p2g1 + p2p1g0 + p2p1p0c0)
= g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0

Note that c4 does not have to wait for c3 and c2 to propagate; in fact, c4 is
propagated at the same time of c3 and c2.

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 A 4-bit carry lookahead adder circuit

“carry-out”, not “c-zero”

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 To determine the effectiveness of the carry-lookahead procedure,
we need to determine the time required to calculate the carry terms.

To simplify the logic diagram, we write the propagate condition as:

𝑷𝒊 = 𝑨𝒊 𝑩𝒊 + 𝑨𝒊 𝑩𝒊 = 𝑨𝒊 𝑩𝒊 + 𝑨𝒊 𝑩𝒊

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As can be seen, 2 gate delays are associated with generating the
propagate condition.
Also, the carry expression has 2 level nature,
This will result in a total of 4 gate delays (40 ns)
to evaluate a carry term.

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Add times for a 4-bit and 32-bit adder using carry-lookahead logic
can be calculated as shown.

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 Magnitude Comparator
The logic circuit will have:
1. two inputs:
a) one for A and other
b) for B and have
2. three output terminals,
a) one for A > B condition,
b) one for A = B condition and
c) one for A < B condition.

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 1-Bit Magnitude Comparator

Consider the simple 1-bit comparator below.

1-bit Comparator

Then the operation of a 1-bit digital comparator is given in the

following Truth Table.

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 1-Bit Magnitude Comparator

Inputs Outputs
B A A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
From the above truth table logical expressions for each output can be expressed as
follows:

𝐴 > 𝐵: 𝐴 𝐵′
𝐴 < 𝐵: 𝐴′ 𝐵
𝐴 = 𝐵: 𝐴′ 𝐵′ + 𝐴𝐵 = 𝐴⨀𝐵
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 2-Bit Magnitude Comparator
• The comparison of two numbers Truth table
(2-bit numbers) A1 A0 B1 B0 E G L
– outputs: A>B, A=B, A<B 0 0 0 0 1 0 0

– 2-bit numbers 0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 1
A1 0

A0 A<B 0 1 0 0 0 1 0
0 1 0 1 1 0 0
Comparator A=B 0 1 1 0 0 1
0
B1 0 1 1 1 0 1
B0 A>B 1 0 0 0
0
1 0
0
1 0 0 1 0 1 0
1 0 1 0 1 0 0
1 0 1 1 0 0 1
1 1 0 0 0 1 0
1 1 0 1 0 1 0
1 1 1 0 1 0
0
1 1 1 1 1 0 0

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 A1 A0 B1 B0 E G L
0 0 0 0 1 0 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 0 1 0
0 1 0 1 1 0 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 0 1 0
1 0 0 1 0 1 0
1 0 1 0 1 0 0
𝐺 = 𝐴1𝐵1’ + 𝐴0𝐵1’𝐵0’ + 𝐴1𝐴0𝐵0’ 1 0 1 1 0 0 1
1 1 0 0 0 1 0
1 1 0 1 0 1 0
1 1 1 0 1 0
0
1 1 1 1 1 0 0

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A1 A0 B1 B0 E G L
0 0 0 0 1 0 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 0 1 0
0 1 0 1 1 0 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 0 1 0
1 0 0 1 0 1 0
1 0 1 0 1 0 0
1 0 1 1 0 0 1
1 1 0 0 0 1 0
1 1 0 1 0 1 0
1 1 1 0 1 0
0
1 1 1 1 1 0 0
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 A1 A0 B1 B0 E G L
0 0 0 0 1 0 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 0 1 0
0 1 0 1 1 0 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 0 1 0
1 0 0 1 0 1 0
1 0 1 0 1 0 0
1 0 1 1 0 0 1
1 1 0 0 0 1 0
1 1 0 1 0 1 0
1 1 1 0 1 0
0
1 1 1 1 1 0 0
𝐿 = 𝐴1’𝐵1 + 𝐴1’𝐴0’𝐵0 + 𝐴0’𝐵1𝐵0
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By using these Boolean expressions, we can implement a logic circuit for this
comparator as given below:

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